AuxXxilium/linux_dsm_epyc7002
1
0
Fork 0
mirror of https://github.com/AuxXxilium/linux_dsm_epyc7002.git synced 2024-11-30 08:56:45 +07:00
Code Issues Actions Packages Projects Releases Wiki Activity

gma500: Disable the clock gating of display controller to make DP/eDP work well

Browse Source 
I don't know why the DP/eDP is affected by the clock gating. But the test
shows that it really fixes the DP/eDP clock issue during enabling DP/eDP.

Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
[Updated to only apply the workaround if the device has DP. We don't want
 to do this on netbooks]
Signed-off-by: Alan Cox <alan@linux.intel.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
This commit is contained in:
Zhao Yakui 2012-08-08 13:57:01 +00:00 committed by Dave Airlie
parent d112a8163f
commit 9a9f5786fc
2 changed files with 28 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

24
drivers/gpu/drm/gma500/cdv_intel_dp.c
View File

@ -1778,6 +1778,28 @@ static bool cdv_intel_dpc_is_edp(struct drm_device *dev)
return false;
}
/* Cedarview display clock gating
We need this disable dot get correct behaviour while enabling
DP/eDP. TODO - investigate if we can turn it back to normality
after enabling */
static void cdv_disable_intel_clock_gating(struct drm_device *dev)
{
u32 reg_value;
reg_value = REG_READ(DSPCLK_GATE_D);
reg_value |= (DPUNIT_PIPEB_GATE_DISABLE |
DPUNIT_PIPEA_GATE_DISABLE |
DPCUNIT_CLOCK_GATE_DISABLE |
DPLSUNIT_CLOCK_GATE_DISABLE |
DPOUNIT_CLOCK_GATE_DISABLE |
DPIOUNIT_CLOCK_GATE_DISABLE);
REG_WRITE(DSPCLK_GATE_D, reg_value);
udelay(500);
}
void
cdv_intel_dp_init(struct drm_device *dev, struct psb_intel_mode_device *mode_dev, int output_reg)
{
@ -1841,6 +1863,8 @@ cdv_intel_dp_init(struct drm_device *dev, struct psb_intel_mode_device *mode_dev
break;
}
cdv_disable_intel_clock_gating(dev);
cdv_intel_dp_i2c_init(psb_intel_connector, psb_intel_encoder, name);
/* FIXME:fail check */
cdv_intel_dp_add_properties(connector);

4
drivers/gpu/drm/gma500/psb_intel_reg.h
View File

@ -1313,6 +1313,10 @@ No status bits are changed.
# define VRHUNIT_CLOCK_GATE_DISABLE (1 << 28) /* Fixed value on CDV */
# define DPOUNIT_CLOCK_GATE_DISABLE (1 << 11)
# define DPIOUNIT_CLOCK_GATE_DISABLE (1 << 6)
# define DPUNIT_PIPEB_GATE_DISABLE (1 << 30)
# define DPUNIT_PIPEA_GATE_DISABLE (1 << 25)
# define DPCUNIT_CLOCK_GATE_DISABLE (1 << 24)
# define DPLSUNIT_CLOCK_GATE_DISABLE (1 << 13)
#define RAMCLK_GATE_D 0x6210