mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-11-29 22:56:47 +07:00
drm/nouveau/pm: add initial NV3x/NVCx memtiming support, improve other cards
NV30: Create framework for memtm NV50: Improve reg creation, NV50: Use P.version instead of card codename/stepping, NVC0: Initial memtiming code for Fermi, Renamed regs for consistency, Overall redesign to improve readability, Avoid kfree on null-pointer Signed-off-by: Roy Spliet <r.spliet@student.tudelft.nl>
This commit is contained in:
Roy Spliet
Ben Skeggs
parent
1cb70b30e4
commit
9a78248876
@ -429,17 +429,43 @@ struct nouveau_pm_voltage {
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struct nouveau_pm_memtiming {
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int id;
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u32 reg_100220;
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u32 reg_100224;
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u32 reg_100228;
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u32 reg_10022c;
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u32 reg_100230;
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u32 reg_100234;
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u32 reg_100238;
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u32 reg_10023c;
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u32 reg_100240;
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u32 reg_0; /* 0x10f290 on Fermi, 0x100220 for older */
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u32 reg_1;
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u32 reg_2;
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u32 reg_3;
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u32 reg_4;
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u32 reg_5;
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u32 reg_6;
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u32 reg_7;
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u32 reg_8;
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};
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struct nouveau_pm_tbl_header{
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u8 version;
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u8 header_len;
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u8 entry_cnt;
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u8 entry_len;
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};
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struct nouveau_pm_tbl_entry{
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u8 tUNK_0, tUNK_1, tUNK_2;
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u8 tRP; /* Byte 3 */
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u8 empty_4;
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u8 tRAS; /* Byte 5 */
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u8 empty_6;
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u8 tRFC; /* Byte 7 */
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u8 empty_8;
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u8 tRC; /* Byte 9 */
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u8 tUNK_10, tUNK_11, tUNK_12, tUNK_13, tUNK_14;
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u8 empty_15,empty_16,empty_17;
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u8 tUNK_18, tUNK_19, tUNK_20, tUNK_21;
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};
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/* nouveau_mem.c */
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void nv30_mem_timing_entry(struct drm_device *dev, struct nouveau_pm_tbl_header *hdr,
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struct nouveau_pm_tbl_entry *e, uint8_t magic_number,
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struct nouveau_pm_memtiming *timing);
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#define NOUVEAU_PM_MAX_LEVEL 8
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struct nouveau_pm_level {
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struct device_attribute dev_attr;
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@ -648,7 +674,6 @@ struct drm_nouveau_private {
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enum nouveau_card_type card_type;
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/* exact chipset, derived from NV_PMC_BOOT_0 */
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int chipset;
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int stepping;
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int flags;
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void __iomem *mmio;
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@ -502,35 +502,146 @@ nouveau_mem_gart_init(struct drm_device *dev)
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return 0;
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}
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/* XXX: For now a dummy. More samples required, possibly even a card
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* Called from nouveau_perf.c */
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void nv30_mem_timing_entry(struct drm_device *dev, struct nouveau_pm_tbl_header *hdr,
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struct nouveau_pm_tbl_entry *e, uint8_t magic_number,
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struct nouveau_pm_memtiming *timing) {
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NV_DEBUG(dev,"Timing entry format unknown, please contact nouveau developers");
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}
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void nv40_mem_timing_entry(struct drm_device *dev, struct nouveau_pm_tbl_header *hdr,
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struct nouveau_pm_tbl_entry *e, uint8_t magic_number,
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struct nouveau_pm_memtiming *timing) {
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timing->reg_0 = (e->tRC << 24 | e->tRFC << 16 | e->tRAS << 8 | e->tRP);
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/* XXX: I don't trust the -1's and +1's... they must come
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* from somewhere! */
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timing->reg_1 = (e->tUNK_0 + 2 + magic_number) << 24 |
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1 << 16 |
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(e->tUNK_1 + 2 + magic_number) << 8 |
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(e->tUNK_2 + 2 - magic_number);
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timing->reg_2 = (magic_number << 24 | e->tUNK_12 << 16 | e->tUNK_11 << 8 | e->tUNK_10);
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timing->reg_2 |= 0x20200000;
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NV_DEBUG(dev, "Entry %d: 220: %08x %08x %08x\n", timing->id,
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timing->reg_0, timing->reg_1,timing->reg_2);
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}
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void nv50_mem_timing_entry(struct drm_device *dev, struct bit_entry *P, struct nouveau_pm_tbl_header *hdr,
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struct nouveau_pm_tbl_entry *e, uint8_t magic_number,struct nouveau_pm_memtiming *timing) {
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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uint8_t unk18 = 1,
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unk19 = 1,
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unk20 = 0,
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unk21 = 0;
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switch (min(hdr->entry_len, (u8) 22)) {
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case 22:
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unk21 = e->tUNK_21;
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case 21:
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unk20 = e->tUNK_20;
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case 20:
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unk19 = e->tUNK_19;
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case 19:
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unk18 = e->tUNK_18;
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break;
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}
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timing->reg_0 = (e->tRC << 24 | e->tRFC << 16 | e->tRAS << 8 | e->tRP);
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/* XXX: I don't trust the -1's and +1's... they must come
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* from somewhere! */
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timing->reg_1 = (e->tUNK_0 + unk19 + 1 + magic_number) << 24 |
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max(unk18, (u8) 1) << 16 |
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(e->tUNK_1 + unk19 + 1 + magic_number) << 8;
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if (dev_priv->chipset == 0xa8) {
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timing->reg_1 |= (e->tUNK_2 - 1);
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} else {
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timing->reg_1 |= (e->tUNK_2 + 2 - magic_number);
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}
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timing->reg_2 = (e->tUNK_12 << 16 | e->tUNK_11 << 8 | e->tUNK_10);
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timing->reg_5 = (e->tRAS << 24 | e->tRC);
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timing->reg_5 += max(e->tUNK_10, e->tUNK_11) << 16;
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if (P->version == 1) {
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timing->reg_2 |= magic_number << 24;
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timing->reg_3 = (0x14 + e->tUNK_2) << 24 |
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0x16 << 16 |
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(e->tUNK_2 - 1) << 8 |
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(e->tUNK_2 - 1);
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timing->reg_4 = (nv_rd32(dev,0x10022c) & 0xffff0000) | e->tUNK_13 << 8 | e->tUNK_13;
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timing->reg_5 |= (e->tUNK_2 + 2) << 8;
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timing->reg_7 = 0x4000202 | (e->tUNK_2 - 1) << 16;
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} else {
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timing->reg_2 |= (unk19 - 1) << 24;
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/* XXX: reg_10022c for recentish cards pretty much unknown*/
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timing->reg_3 = e->tUNK_2 - 1;
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timing->reg_4 = (unk20 << 24 | unk21 << 16 |
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e->tUNK_13 << 8 | e->tUNK_13);
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/* XXX: +6? */
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timing->reg_5 |= (unk19 + 6) << 8;
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/* XXX: reg_10023c currently unknown
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* 10023c seen as 06xxxxxx, 0bxxxxxx or 0fxxxxxx */
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timing->reg_7 = 0x202;
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}
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NV_DEBUG(dev, "Entry %d: 220: %08x %08x %08x %08x\n", timing->id,
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timing->reg_0, timing->reg_1,
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timing->reg_2, timing->reg_3);
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NV_DEBUG(dev, " 230: %08x %08x %08x %08x\n",
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timing->reg_4, timing->reg_5,
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timing->reg_6, timing->reg_7);
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NV_DEBUG(dev, " 240: %08x\n", timing->reg_8);
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}
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void nvc0_mem_timing_entry(struct drm_device *dev, struct nouveau_pm_tbl_header *hdr,
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struct nouveau_pm_tbl_entry *e, struct nouveau_pm_memtiming *timing) {
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timing->reg_0 = (e->tRC << 24 | (e->tRFC & 0x7f) << 17 | e->tRAS << 8 | e->tRP);
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timing->reg_1 = (nv_rd32(dev,0x10f294) & 0xff000000) | (e->tUNK_11&0x0f) << 20 | (e->tUNK_19 << 7) | (e->tUNK_2 & 0x0f);
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timing->reg_2 = (nv_rd32(dev,0x10f298) & 0xff0000ff) | e->tUNK_0 << 16 | e->tUNK_1 << 8;
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timing->reg_3 = e->tUNK_20 << 9 | e->tUNK_13;
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timing->reg_4 = (nv_rd32(dev,0x10f2a0) & 0xfff000ff) | e->tUNK_12 << 15;
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NV_DEBUG(dev, "Entry %d: 290: %08x %08x %08x %08x\n", timing->id,
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timing->reg_0, timing->reg_1,
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timing->reg_2, timing->reg_3);
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NV_DEBUG(dev, " 2a0: %08x %08x %08x %08x\n",
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timing->reg_4, timing->reg_5,
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timing->reg_6, timing->reg_7);
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}
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/**
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* Processes the Memory Timing BIOS table, stores generated
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* register values
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* @pre init scripts were run, memtiming regs are initialized
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*/
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void
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nouveau_mem_timing_init(struct drm_device *dev)
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{
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/* cards < NVC0 only */
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nouveau_pm_engine *pm = &dev_priv->engine.pm;
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struct nouveau_pm_memtimings *memtimings = &pm->memtimings;
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struct nvbios *bios = &dev_priv->vbios;
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struct bit_entry P;
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u8 tUNK_0, tUNK_1, tUNK_2;
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u8 tRP; /* Byte 3 */
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u8 tRAS; /* Byte 5 */
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u8 tRFC; /* Byte 7 */
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u8 tRC; /* Byte 9 */
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u8 tUNK_10, tUNK_11, tUNK_12, tUNK_13, tUNK_14;
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u8 tUNK_18, tUNK_19, tUNK_20, tUNK_21;
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u8 magic_number = 0; /* Yeah... sorry*/
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u8 *mem = NULL, *entry;
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int i, recordlen, entries;
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struct nouveau_pm_tbl_header *hdr = NULL;
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uint8_t magic_number;
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u8 *entry;
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int i;
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if (bios->type == NVBIOS_BIT) {
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if (bit_table(dev, 'P', &P))
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return;
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if (P.version == 1)
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mem = ROMPTR(bios, P.data[4]);
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hdr = (struct nouveau_pm_tbl_header *) ROMPTR(bios, P.data[4]);
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else
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if (P.version == 2)
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mem = ROMPTR(bios, P.data[8]);
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hdr = (struct nouveau_pm_tbl_header *) ROMPTR(bios, P.data[8]);
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else {
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NV_WARN(dev, "unknown mem for BIT P %d\n", P.version);
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}
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@ -539,150 +650,54 @@ nouveau_mem_timing_init(struct drm_device *dev)
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return;
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}
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if (!mem) {
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if (!hdr) {
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NV_DEBUG(dev, "memory timing table pointer invalid\n");
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return;
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}
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if (mem[0] != 0x10) {
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NV_WARN(dev, "memory timing table 0x%02x unknown\n", mem[0]);
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if (hdr->version != 0x10) {
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NV_WARN(dev, "memory timing table 0x%02x unknown\n", hdr->version);
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return;
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}
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/* validate record length */
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entries = mem[2];
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recordlen = mem[3];
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if (recordlen < 15) {
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NV_ERROR(dev, "mem timing table length unknown: %d\n", mem[3]);
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if (hdr->entry_len < 15) {
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NV_ERROR(dev, "mem timing table length unknown: %d\n", hdr->entry_len);
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return;
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}
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/* parse vbios entries into common format */
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memtimings->timing =
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kcalloc(entries, sizeof(*memtimings->timing), GFP_KERNEL);
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kcalloc(hdr->entry_cnt, sizeof(*memtimings->timing), GFP_KERNEL);
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if (!memtimings->timing)
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return;
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/* Get "some number" from the timing reg for NV_40 and NV_50
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* Used in calculations later */
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if (dev_priv->card_type >= NV_40 && dev_priv->chipset < 0x98) {
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* Used in calculations later... source unknown */
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magic_number = 0;
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if (P.version == 1) {
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magic_number = (nv_rd32(dev, 0x100228) & 0x0f000000) >> 24;
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}
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entry = mem + mem[1];
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for (i = 0; i < entries; i++, entry += recordlen) {
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entry = (u8*) hdr + hdr->header_len;
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for (i = 0; i < hdr->entry_cnt; i++, entry += hdr->entry_len) {
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struct nouveau_pm_memtiming *timing = &pm->memtimings.timing[i];
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if (entry[0] == 0)
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continue;
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tUNK_18 = 1;
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tUNK_19 = 1;
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tUNK_20 = 0;
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tUNK_21 = 0;
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switch (min(recordlen, 22)) {
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case 22:
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tUNK_21 = entry[21];
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case 21:
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tUNK_20 = entry[20];
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case 20:
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tUNK_19 = entry[19];
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case 19:
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tUNK_18 = entry[18];
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default:
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tUNK_0 = entry[0];
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tUNK_1 = entry[1];
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tUNK_2 = entry[2];
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tRP = entry[3];
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tRAS = entry[5];
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tRFC = entry[7];
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tRC = entry[9];
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tUNK_10 = entry[10];
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tUNK_11 = entry[11];
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tUNK_12 = entry[12];
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tUNK_13 = entry[13];
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tUNK_14 = entry[14];
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break;
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}
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timing->reg_100220 = (tRC << 24 | tRFC << 16 | tRAS << 8 | tRP);
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/* XXX: I don't trust the -1's and +1's... they must come
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* from somewhere! */
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timing->reg_100224 = (tUNK_0 + tUNK_19 + 1 + magic_number) << 24 |
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max(tUNK_18, (u8) 1) << 16 |
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(tUNK_1 + tUNK_19 + 1 + magic_number) << 8;
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if (dev_priv->chipset == 0xa8) {
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timing->reg_100224 |= (tUNK_2 - 1);
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} else {
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timing->reg_100224 |= (tUNK_2 + 2 - magic_number);
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}
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timing->reg_100228 = (tUNK_12 << 16 | tUNK_11 << 8 | tUNK_10);
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if (dev_priv->chipset >= 0xa3 && dev_priv->chipset < 0xaa)
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timing->reg_100228 |= (tUNK_19 - 1) << 24;
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else
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timing->reg_100228 |= magic_number << 24;
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if (dev_priv->card_type == NV_40) {
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/* NV40: don't know what the rest of the regs are..
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* And don't need to know either */
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timing->reg_100228 |= 0x20200000;
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} else if (dev_priv->card_type >= NV_50) {
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if (dev_priv->chipset < 0x98 ||
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(dev_priv->chipset == 0x98 &&
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dev_priv->stepping <= 0xa1)) {
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timing->reg_10022c = (0x14 + tUNK_2) << 24 |
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0x16 << 16 |
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(tUNK_2 - 1) << 8 |
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(tUNK_2 - 1);
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} else {
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/* XXX: reg_10022c for recentish cards */
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timing->reg_10022c = tUNK_2 - 1;
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}
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timing->reg_100230 = (tUNK_20 << 24 | tUNK_21 << 16 |
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tUNK_13 << 8 | tUNK_13);
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timing->reg_100234 = (tRAS << 24 | tRC);
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timing->reg_100234 += max(tUNK_10, tUNK_11) << 16;
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if (dev_priv->chipset < 0x98 ||
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(dev_priv->chipset == 0x98 &&
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dev_priv->stepping <= 0xa1)) {
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timing->reg_100234 |= (tUNK_2 + 2) << 8;
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} else {
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/* XXX: +6? */
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timing->reg_100234 |= (tUNK_19 + 6) << 8;
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}
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/* XXX; reg_100238
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* reg_100238: 0x00?????? */
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timing->reg_10023c = 0x202;
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if (dev_priv->chipset < 0x98 ||
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(dev_priv->chipset == 0x98 &&
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dev_priv->stepping <= 0xa1)) {
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timing->reg_10023c |= 0x4000000 | (tUNK_2 - 1) << 16;
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} else {
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/* XXX: reg_10023c
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* currently unknown
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* 10023c seen as 06xxxxxx, 0bxxxxxx or 0fxxxxxx */
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}
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/* XXX: reg_100240? */
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}
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timing->id = i;
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NV_DEBUG(dev, "Entry %d: 220: %08x %08x %08x %08x\n", i,
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timing->reg_100220, timing->reg_100224,
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timing->reg_100228, timing->reg_10022c);
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NV_DEBUG(dev, " 230: %08x %08x %08x %08x\n",
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timing->reg_100230, timing->reg_100234,
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timing->reg_100238, timing->reg_10023c);
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NV_DEBUG(dev, " 240: %08x\n", timing->reg_100240);
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if(dev_priv->card_type <= NV_40) {
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nv40_mem_timing_entry(dev,hdr,(struct nouveau_pm_tbl_entry*) entry,magic_number,&pm->memtimings.timing[i]);
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} else if(dev_priv->card_type == NV_50){
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nv50_mem_timing_entry(dev,&P,hdr,(struct nouveau_pm_tbl_entry*) entry,magic_number,&pm->memtimings.timing[i]);
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} else if(dev_priv->card_type == NV_C0) {
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nvc0_mem_timing_entry(dev,hdr,(struct nouveau_pm_tbl_entry*) entry,&pm->memtimings.timing[i]);
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}
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}
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memtimings->nr_timing = entries;
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memtimings->supported = (dev_priv->chipset <= 0x98);
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memtimings->nr_timing = hdr->entry_cnt;
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memtimings->supported = P.version == 1;
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}
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||||
|
||||
void
|
||||
@ -691,7 +706,10 @@ nouveau_mem_timing_fini(struct drm_device *dev)
|
||||
struct drm_nouveau_private *dev_priv = dev->dev_private;
|
||||
struct nouveau_pm_memtimings *mem = &dev_priv->engine.pm.memtimings;
|
||||
|
||||
kfree(mem->timing);
|
||||
if(mem->timing) {
|
||||
kfree(mem->timing);
|
||||
mem->timing = NULL;
|
||||
}
|
||||
}
|
||||
|
||||
static int
|
||||
|
||||
@ -185,6 +185,8 @@ nouveau_perf_init(struct drm_device *dev)
|
||||
struct nouveau_pm_engine *pm = &dev_priv->engine.pm;
|
||||
struct nvbios *bios = &dev_priv->vbios;
|
||||
struct bit_entry P;
|
||||
struct nouveau_pm_memtimings *memtimings = &pm->memtimings;
|
||||
struct nouveau_pm_tbl_header mt_hdr;
|
||||
u8 version, headerlen, recordlen, entries;
|
||||
u8 *perf, *entry;
|
||||
int vid, i;
|
||||
@ -232,6 +234,22 @@ nouveau_perf_init(struct drm_device *dev)
|
||||
}
|
||||
|
||||
entry = perf + headerlen;
|
||||
|
||||
/* For version 0x15, initialize memtiming table */
|
||||
if(version == 0x15) {
|
||||
memtimings->timing =
|
||||
kcalloc(entries, sizeof(*memtimings->timing), GFP_KERNEL);
|
||||
if(!memtimings) {
|
||||
NV_WARN(dev,"Could not allocate memtiming table\n");
|
||||
return;
|
||||
}
|
||||
|
||||
mt_hdr.entry_cnt = entries;
|
||||
mt_hdr.entry_len = 14;
|
||||
mt_hdr.version = version;
|
||||
mt_hdr.header_len = 4;
|
||||
}
|
||||
|
||||
for (i = 0; i < entries; i++) {
|
||||
struct nouveau_pm_level *perflvl = &pm->perflvl[pm->nr_perflvl];
|
||||
|
||||
@ -321,7 +339,11 @@ nouveau_perf_init(struct drm_device *dev)
|
||||
}
|
||||
|
||||
/* get the corresponding memory timings */
|
||||
if (version > 0x15) {
|
||||
if (version == 0x15) {
|
||||
memtimings->timing[i].id = i;
|
||||
nv30_mem_timing_entry(dev,&mt_hdr,(struct nouveau_pm_tbl_entry*) &entry[41],0,&memtimings->timing[i]);
|
||||
perflvl->timing = &memtimings->timing[i];
|
||||
} else if (version > 0x15) {
|
||||
/* last 3 args are for < 0x40, ignored for >= 0x40 */
|
||||
perflvl->timing =
|
||||
nouveau_perf_timing(dev, &P,
|
||||
|
||||
@ -1028,13 +1028,11 @@ int nouveau_load(struct drm_device *dev, unsigned long flags)
|
||||
|
||||
/* Time to determine the card architecture */
|
||||
reg0 = nv_rd32(dev, NV03_PMC_BOOT_0);
|
||||
dev_priv->stepping = 0; /* XXX: add stepping for pre-NV10? */
|
||||
|
||||
/* We're dealing with >=NV10 */
|
||||
if ((reg0 & 0x0f000000) > 0) {
|
||||
/* Bit 27-20 contain the architecture in hex */
|
||||
dev_priv->chipset = (reg0 & 0xff00000) >> 20;
|
||||
dev_priv->stepping = (reg0 & 0xff);
|
||||
/* NV04 or NV05 */
|
||||
} else if ((reg0 & 0xff00fff0) == 0x20004000) {
|
||||
if (reg0 & 0x00f00000)
|
||||
|
||||
Loading…
Reference in New Issue
Block a user