mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-16 13:46:44 +07:00
drm/bridge: tc358767: fix initial DP0/1_SRCCTRL value
Initially DP0_SRCCTRL is set to a static value which includes DP0_SRCCTRL_LANES_2 and DP0_SRCCTRL_BW27, even when only 1 lane of 1.62Gbps speed is used. DP1_SRCCTRL is configured to a magic number. This patch changes the configuration as follows: Configure DP0_SRCCTRL by using tc_srcctrl() which provides the correct value. DP1_SRCCTRL needs two bits to be set to the same value as DP0_SRCCTRL: SSCG and BW27. All other bits can be zero. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com> Reviewed-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190103115954.12785-5-tomi.valkeinen@ti.com
This commit is contained in:
parent
4d9d54a730
commit
9a63bd6fe1
@ -836,12 +836,11 @@ static int tc_main_link_setup(struct tc_data *tc)
|
|||||||
if (!tc->mode)
|
if (!tc->mode)
|
||||||
return -EINVAL;
|
return -EINVAL;
|
||||||
|
|
||||||
/* from excel file - DP0_SrcCtrl */
|
tc_write(DP0_SRCCTRL, tc_srcctrl(tc));
|
||||||
tc_write(DP0_SRCCTRL, DP0_SRCCTRL_SCRMBLDIS | DP0_SRCCTRL_EN810B |
|
/* SSCG and BW27 on DP1 must be set to the same as on DP0 */
|
||||||
DP0_SRCCTRL_LANESKEW | DP0_SRCCTRL_LANES_2 |
|
tc_write(DP1_SRCCTRL,
|
||||||
DP0_SRCCTRL_BW27 | DP0_SRCCTRL_AUTOCORRECT);
|
(tc->link.spread ? DP0_SRCCTRL_SSCG : 0) |
|
||||||
/* from excel file - DP1_SrcCtrl */
|
((tc->link.base.rate != 162000) ? DP0_SRCCTRL_BW27 : 0));
|
||||||
tc_write(DP1_SRCCTRL, 0x00003083);
|
|
||||||
|
|
||||||
rate = clk_get_rate(tc->refclk);
|
rate = clk_get_rate(tc->refclk);
|
||||||
switch (rate) {
|
switch (rate) {
|
||||||
|
Loading…
Reference in New Issue
Block a user