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drm/amd/display: Report stream as different on scaling change
When scaling is enabled, our preference is to scale up to the prefered (native) mode. This means that hardware timings will be the same across a modeset. Therefore, also report mode as changed if source or destination rectangle is different. Signed-off-by: Leo (Sunpeng) Li <sunpeng.li@amd.com> Reviewed-by: Harry Wentland <Harry.Wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -4428,12 +4428,13 @@ static int dm_update_crtcs_state(struct dc *dc,
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}
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}
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if (dc_is_stream_unchanged(new_stream, dm_old_crtc_state->stream)) {
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if (dc_is_stream_unchanged(new_stream, dm_old_crtc_state->stream) &&
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dc_is_stream_scaling_unchanged(new_stream, dm_old_crtc_state->stream)) {
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new_crtc_state->mode_changed = false;
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DRM_DEBUG_DRIVER("Mode change not required, setting mode_changed to %d",
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new_crtc_state->mode_changed);
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new_crtc_state->mode_changed);
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}
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@ -1335,6 +1335,28 @@ bool dc_is_stream_unchanged(
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return true;
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}
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bool dc_is_stream_scaling_unchanged(
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struct dc_stream_state *old_stream, struct dc_stream_state *stream)
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{
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if (old_stream == stream)
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return true;
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if (old_stream == NULL || stream == NULL)
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return false;
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if (memcmp(&old_stream->src,
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&stream->src,
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sizeof(struct rect)) != 0)
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return false;
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if (memcmp(&old_stream->dst,
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&stream->dst,
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sizeof(struct rect)) != 0)
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return false;
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return true;
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}
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/* Maximum TMDS single link pixel clock 165MHz */
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#define TMDS_MAX_PIXEL_CLOCK_IN_KHZ 165000
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@ -627,6 +627,8 @@ struct dc_stream_update {
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bool dc_is_stream_unchanged(
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struct dc_stream_state *old_stream, struct dc_stream_state *stream);
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bool dc_is_stream_scaling_unchanged(
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struct dc_stream_state *old_stream, struct dc_stream_state *stream);
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/*
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* Set up surface attributes and associate to a stream
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