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drm/amd/pm: fix pcie information for sienna cichlid

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Fix the function used for sienna cichlid to get correct PCIE information
by pp_dpm_pcie.

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org # 5.9.x
This commit is contained in:
Likun Gao 2020-10-20 16:29:30 +08:00 committed by Alex Deucher
parent d56b1980d7
commit 9a2f408f54
1 changed files with 2 additions and 2 deletions
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4
drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
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@ -962,8 +962,8 @@ static int sienna_cichlid_print_clk_levels(struct smu_context *smu,
}
break;
case SMU_PCIE:
gen_speed = smu_v11_0_get_current_pcie_link_speed(smu);
lane_width = smu_v11_0_get_current_pcie_link_width(smu);
gen_speed = smu_v11_0_get_current_pcie_link_speed_level(smu);
lane_width = smu_v11_0_get_current_pcie_link_width_level(smu);
for (i = 0; i < NUM_LINK_LEVELS; i++)
size += sprintf(buf + size, "%d: %s %s %dMhz %s\n", i,
(dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 0) ? "2.5GT/s," :