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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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x86/PCI: read root resources from IOH on Intel
For intel systems with multi IOH, we should read peer root resources directly from PCI config space, and don't trust _CRS. Signed-off-by: Yinghai Lu <yinghai.lu@sun.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
This commit is contained in:
Yinghai Lu
Jesse Barnes
parent
91d3f9bacd
commit
99935a7a59
@ -15,3 +15,4 @@ obj-$(CONFIG_X86_NUMAQ) += numaq_32.o
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obj-y += common.o early.o
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obj-y += amd_bus.o
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obj-$(CONFIG_X86_64) += intel_bus.o
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@ -10,6 +10,8 @@
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#include <linux/cpumask.h>
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#endif
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#include "bus_numa.h"
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/*
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* This discovers the pcibus <-> node mapping on AMD K8.
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* also get peer root bus resource for io,mmio
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@ -17,25 +19,9 @@
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#ifdef CONFIG_X86_64
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/*
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* sub bus (transparent) will use entres from 3 to store extra from root,
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* so need to make sure have enought slot there, increase PCI_BUS_NUM_RESOURCES?
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*/
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#define RES_NUM 16
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struct pci_root_info {
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char name[12];
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unsigned int res_num;
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struct resource res[RES_NUM];
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int bus_min;
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int bus_max;
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int node;
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int link;
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};
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/* 4 at this time, it may become to 32 */
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#define PCI_ROOT_NR 4
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static int pci_root_num;
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static struct pci_root_info pci_root_info[PCI_ROOT_NR];
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int pci_root_num;
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struct pci_root_info pci_root_info[PCI_ROOT_NR];
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static int found_all_numa_early;
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void x86_pci_root_bus_res_quirks(struct pci_bus *b)
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{
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@ -48,8 +34,11 @@ void x86_pci_root_bus_res_quirks(struct pci_bus *b)
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b->resource[1] != &iomem_resource)
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return;
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/* if only one root bus, don't need to anything */
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if (pci_root_num < 2)
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if (!pci_root_num)
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return;
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/* for amd, if only one root bus, don't need to do anything */
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if (pci_root_num < 2 && found_all_numa_early)
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return;
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for (i = 0; i < pci_root_num; i++) {
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@ -130,12 +119,15 @@ static void __init update_range(struct res_range *range, size_t start,
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}
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}
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static void __init update_res(struct pci_root_info *info, size_t start,
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void __init update_res(struct pci_root_info *info, size_t start,
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size_t end, unsigned long flags, int merge)
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{
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int i;
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struct resource *res;
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if (start > end)
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return;
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if (!merge)
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goto addit;
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@ -230,7 +222,6 @@ static int __init early_fill_mp_bus_info(void)
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int j;
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unsigned bus;
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unsigned slot;
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int found;
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int node;
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int link;
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int def_node;
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@ -247,7 +238,7 @@ static int __init early_fill_mp_bus_info(void)
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if (!early_pci_allowed())
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return -1;
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found = 0;
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found_all_numa_early = 0;
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for (i = 0; i < ARRAY_SIZE(pci_probes); i++) {
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u32 id;
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u16 device;
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@ -261,12 +252,12 @@ static int __init early_fill_mp_bus_info(void)
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device = (id>>16) & 0xffff;
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if (pci_probes[i].vendor == vendor &&
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pci_probes[i].device == device) {
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found = 1;
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found_all_numa_early = 1;
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break;
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}
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}
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if (!found)
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if (!found_all_numa_early)
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return 0;
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pci_root_num = 0;
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@ -488,7 +479,7 @@ static int __init early_fill_mp_bus_info(void)
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info = &pci_root_info[i];
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res_num = info->res_num;
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busnum = info->bus_min;
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printk(KERN_DEBUG "bus: [%02x,%02x] on node %x link %x\n",
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printk(KERN_DEBUG "bus: [%02x, %02x] on node %x link %x\n",
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info->bus_min, info->bus_max, info->node, info->link);
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for (j = 0; j < res_num; j++) {
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res = &info->res[j];
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26
arch/x86/pci/bus_numa.h
Normal file
26
arch/x86/pci/bus_numa.h
Normal file
@ -0,0 +1,26 @@
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#ifdef CONFIG_X86_64
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/*
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* sub bus (transparent) will use entres from 3 to store extra from
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* root, so need to make sure we have enought slot there, Should we
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* increase PCI_BUS_NUM_RESOURCES?
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*/
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#define RES_NUM 16
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struct pci_root_info {
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char name[12];
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unsigned int res_num;
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struct resource res[RES_NUM];
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int bus_min;
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int bus_max;
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int node;
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int link;
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};
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/* 4 at this time, it may become to 32 */
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#define PCI_ROOT_NR 4
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extern int pci_root_num;
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extern struct pci_root_info pci_root_info[PCI_ROOT_NR];
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extern void update_res(struct pci_root_info *info, size_t start,
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size_t end, unsigned long flags, int merge);
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#endif
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90
arch/x86/pci/intel_bus.c
Normal file
90
arch/x86/pci/intel_bus.c
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@ -0,0 +1,90 @@
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/*
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* to read io range from IOH pci conf, need to do it after mmconfig is there
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*/
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#include <linux/delay.h>
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#include <linux/dmi.h>
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#include <linux/pci.h>
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#include <linux/init.h>
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#include <asm/pci_x86.h>
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#include "bus_numa.h"
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static inline void print_ioh_resources(struct pci_root_info *info)
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{
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int res_num;
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int busnum;
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int i;
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printk(KERN_DEBUG "IOH bus: [%02x, %02x]\n",
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info->bus_min, info->bus_max);
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res_num = info->res_num;
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busnum = info->bus_min;
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for (i = 0; i < res_num; i++) {
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struct resource *res;
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res = &info->res[i];
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printk(KERN_DEBUG "IOH bus: %02x index %x %s: [%llx, %llx]\n",
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busnum, i,
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(res->flags & IORESOURCE_IO) ? "io port" :
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"mmio",
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res->start, res->end);
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}
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}
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#define IOH_LIO 0x108
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#define IOH_LMMIOL 0x10c
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#define IOH_LMMIOH 0x110
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#define IOH_LMMIOH_BASEU 0x114
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#define IOH_LMMIOH_LIMITU 0x118
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#define IOH_LCFGBUS 0x11c
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static void __devinit pci_root_bus_res(struct pci_dev *dev)
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{
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u16 word;
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u32 dword;
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struct pci_root_info *info;
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u16 io_base, io_end;
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u32 mmiol_base, mmiol_end;
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u64 mmioh_base, mmioh_end;
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int bus_base, bus_end;
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if (pci_root_num >= PCI_ROOT_NR) {
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printk(KERN_DEBUG "intel_bus.c: PCI_ROOT_NR is too small\n");
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return;
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}
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info = &pci_root_info[pci_root_num];
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pci_root_num++;
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pci_read_config_word(dev, IOH_LCFGBUS, &word);
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bus_base = (word & 0xff);
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bus_end = (word & 0xff00) >> 8;
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sprintf(info->name, "PCI Bus #%02x", bus_base);
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info->bus_min = bus_base;
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info->bus_max = bus_end;
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pci_read_config_word(dev, IOH_LIO, &word);
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io_base = (word & 0xf0) << (12 - 4);
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io_end = (word & 0xf000) | 0xfff;
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update_res(info, io_base, io_end, IORESOURCE_IO, 0);
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pci_read_config_dword(dev, IOH_LMMIOL, &dword);
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mmiol_base = (dword & 0xff00) << (24 - 8);
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mmiol_end = (dword & 0xff000000) | 0xffffff;
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update_res(info, mmiol_base, mmiol_end, IORESOURCE_MEM, 0);
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pci_read_config_dword(dev, IOH_LMMIOH, &dword);
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mmioh_base = ((u64)(dword & 0xfc00)) << (26 - 10);
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mmioh_end = ((u64)(dword & 0xfc000000) | 0x3ffffff);
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pci_read_config_dword(dev, IOH_LMMIOH_BASEU, &dword);
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mmioh_base |= ((u64)(dword & 0x7ffff)) << 32;
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pci_read_config_dword(dev, IOH_LMMIOH_LIMITU, &dword);
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mmioh_end |= ((u64)(dword & 0x7ffff)) << 32;
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update_res(info, mmioh_base, mmioh_end, IORESOURCE_MEM, 0);
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print_ioh_resources(info);
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}
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/* intel IOH */
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DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x342e, pci_root_bus_res);
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