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spi: atmel-quadspi: cache MR value to avoid a write access

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Set the controller by default in Serial Memory Mode (SMM) at probe.
Cache Mode Register (MR) value to avoid write access when setting
the controller in serial memory mode at exec_op().

Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Tudor Ambarus 2019-02-05 17:33:06 +00:00 committed by Mark Brown
parent 5ce3cc5674
commit 9958c8c39e
No known key found for this signature in database
GPG Key ID: 24D68B725D5487D0
1 changed files with 13 additions and 1 deletions
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14
drivers/spi/atmel-quadspi.c
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@ -155,6 +155,7 @@ struct atmel_qspi {
struct clk *clk;
struct platform_device *pdev;
u32 pending;
u32 mr;
struct completion cmd_completion;
};
@ -238,7 +239,14 @@ static int atmel_qspi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op)
icr = QSPI_ICR_INST(op->cmd.opcode);
ifr = QSPI_IFR_INSTEN;
qspi_writel(aq, QSPI_MR, QSPI_MR_SMM);
/*
* If the QSPI controller is set in regular SPI mode, set it in
* Serial Memory Mode (SMM).
*/
if (aq->mr != QSPI_MR_SMM) {
qspi_writel(aq, QSPI_MR, QSPI_MR_SMM);
aq->mr = QSPI_MR_SMM;
}
mode = find_mode(op);
if (mode < 0)
@ -381,6 +389,10 @@ static int atmel_qspi_init(struct atmel_qspi *aq)
/* Reset the QSPI controller */
qspi_writel(aq, QSPI_CR, QSPI_CR_SWRST);
/* Set the QSPI controller by default in Serial Memory Mode */
qspi_writel(aq, QSPI_MR, QSPI_MR_SMM);
aq->mr = QSPI_MR_SMM;
/* Enable the QSPI controller */
qspi_writel(aq, QSPI_CR, QSPI_CR_QSPIEN);