mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-06 12:46:40 +07:00
Merge branch 'topic/sprd' into for-linus
This commit is contained in:
commit
990beed934
@ -36,6 +36,8 @@
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#define SPRD_DMA_GLB_CHN_EN_STS 0x1c
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#define SPRD_DMA_GLB_DEBUG_STS 0x20
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#define SPRD_DMA_GLB_ARB_SEL_STS 0x24
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#define SPRD_DMA_GLB_2STAGE_GRP1 0x28
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#define SPRD_DMA_GLB_2STAGE_GRP2 0x2c
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#define SPRD_DMA_GLB_REQ_UID(uid) (0x4 * ((uid) - 1))
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#define SPRD_DMA_GLB_REQ_UID_OFFSET 0x2000
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@ -57,6 +59,18 @@
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#define SPRD_DMA_CHN_SRC_BLK_STEP 0x38
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#define SPRD_DMA_CHN_DES_BLK_STEP 0x3c
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/* SPRD_DMA_GLB_2STAGE_GRP register definition */
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#define SPRD_DMA_GLB_2STAGE_EN BIT(24)
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#define SPRD_DMA_GLB_CHN_INT_MASK GENMASK(23, 20)
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#define SPRD_DMA_GLB_LIST_DONE_TRG BIT(19)
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#define SPRD_DMA_GLB_TRANS_DONE_TRG BIT(18)
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#define SPRD_DMA_GLB_BLOCK_DONE_TRG BIT(17)
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#define SPRD_DMA_GLB_FRAG_DONE_TRG BIT(16)
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#define SPRD_DMA_GLB_TRG_OFFSET 16
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#define SPRD_DMA_GLB_DEST_CHN_MASK GENMASK(13, 8)
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#define SPRD_DMA_GLB_DEST_CHN_OFFSET 8
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#define SPRD_DMA_GLB_SRC_CHN_MASK GENMASK(5, 0)
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/* SPRD_DMA_CHN_INTC register definition */
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#define SPRD_DMA_INT_MASK GENMASK(4, 0)
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#define SPRD_DMA_INT_CLR_OFFSET 24
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@ -118,6 +132,10 @@
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#define SPRD_DMA_SRC_TRSF_STEP_OFFSET 0
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#define SPRD_DMA_TRSF_STEP_MASK GENMASK(15, 0)
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/* define DMA channel mode & trigger mode mask */
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#define SPRD_DMA_CHN_MODE_MASK GENMASK(7, 0)
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#define SPRD_DMA_TRG_MODE_MASK GENMASK(7, 0)
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/* define the DMA transfer step type */
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#define SPRD_DMA_NONE_STEP 0
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#define SPRD_DMA_BYTE_STEP 1
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@ -159,6 +177,7 @@ struct sprd_dma_chn_hw {
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struct sprd_dma_desc {
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struct virt_dma_desc vd;
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struct sprd_dma_chn_hw chn_hw;
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enum dma_transfer_direction dir;
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};
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/* dma channel description */
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@ -169,6 +188,8 @@ struct sprd_dma_chn {
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struct dma_slave_config slave_cfg;
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u32 chn_num;
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u32 dev_id;
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enum sprd_dma_chn_mode chn_mode;
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enum sprd_dma_trg_mode trg_mode;
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struct sprd_dma_desc *cur_desc;
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};
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@ -205,6 +226,16 @@ static inline struct sprd_dma_desc *to_sprd_dma_desc(struct virt_dma_desc *vd)
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return container_of(vd, struct sprd_dma_desc, vd);
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}
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static void sprd_dma_glb_update(struct sprd_dma_dev *sdev, u32 reg,
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u32 mask, u32 val)
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{
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u32 orig = readl(sdev->glb_base + reg);
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u32 tmp;
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tmp = (orig & ~mask) | val;
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writel(tmp, sdev->glb_base + reg);
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}
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static void sprd_dma_chn_update(struct sprd_dma_chn *schan, u32 reg,
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u32 mask, u32 val)
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{
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@ -331,6 +362,17 @@ static void sprd_dma_stop_and_disable(struct sprd_dma_chn *schan)
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sprd_dma_disable_chn(schan);
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}
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static unsigned long sprd_dma_get_src_addr(struct sprd_dma_chn *schan)
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{
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unsigned long addr, addr_high;
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addr = readl(schan->chn_base + SPRD_DMA_CHN_SRC_ADDR);
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addr_high = readl(schan->chn_base + SPRD_DMA_CHN_WARP_PTR) &
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SPRD_DMA_HIGH_ADDR_MASK;
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return addr | (addr_high << SPRD_DMA_HIGH_ADDR_OFFSET);
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}
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static unsigned long sprd_dma_get_dst_addr(struct sprd_dma_chn *schan)
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{
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unsigned long addr, addr_high;
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@ -377,6 +419,49 @@ static enum sprd_dma_req_mode sprd_dma_get_req_type(struct sprd_dma_chn *schan)
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return (frag_reg >> SPRD_DMA_REQ_MODE_OFFSET) & SPRD_DMA_REQ_MODE_MASK;
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}
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static int sprd_dma_set_2stage_config(struct sprd_dma_chn *schan)
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{
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struct sprd_dma_dev *sdev = to_sprd_dma_dev(&schan->vc.chan);
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u32 val, chn = schan->chn_num + 1;
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switch (schan->chn_mode) {
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case SPRD_DMA_SRC_CHN0:
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val = chn & SPRD_DMA_GLB_SRC_CHN_MASK;
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val |= BIT(schan->trg_mode - 1) << SPRD_DMA_GLB_TRG_OFFSET;
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val |= SPRD_DMA_GLB_2STAGE_EN;
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sprd_dma_glb_update(sdev, SPRD_DMA_GLB_2STAGE_GRP1, val, val);
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break;
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case SPRD_DMA_SRC_CHN1:
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val = chn & SPRD_DMA_GLB_SRC_CHN_MASK;
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val |= BIT(schan->trg_mode - 1) << SPRD_DMA_GLB_TRG_OFFSET;
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val |= SPRD_DMA_GLB_2STAGE_EN;
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sprd_dma_glb_update(sdev, SPRD_DMA_GLB_2STAGE_GRP2, val, val);
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break;
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case SPRD_DMA_DST_CHN0:
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val = (chn << SPRD_DMA_GLB_DEST_CHN_OFFSET) &
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SPRD_DMA_GLB_DEST_CHN_MASK;
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val |= SPRD_DMA_GLB_2STAGE_EN;
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sprd_dma_glb_update(sdev, SPRD_DMA_GLB_2STAGE_GRP1, val, val);
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break;
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case SPRD_DMA_DST_CHN1:
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val = (chn << SPRD_DMA_GLB_DEST_CHN_OFFSET) &
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SPRD_DMA_GLB_DEST_CHN_MASK;
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val |= SPRD_DMA_GLB_2STAGE_EN;
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sprd_dma_glb_update(sdev, SPRD_DMA_GLB_2STAGE_GRP2, val, val);
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break;
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default:
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dev_err(sdev->dma_dev.dev, "invalid channel mode setting %d\n",
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schan->chn_mode);
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return -EINVAL;
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}
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return 0;
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}
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static void sprd_dma_set_chn_config(struct sprd_dma_chn *schan,
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struct sprd_dma_desc *sdesc)
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{
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@ -410,6 +495,13 @@ static void sprd_dma_start(struct sprd_dma_chn *schan)
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list_del(&vd->node);
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schan->cur_desc = to_sprd_dma_desc(vd);
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/*
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* Set 2-stage configuration if the channel starts one 2-stage
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* transfer.
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*/
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if (schan->chn_mode && sprd_dma_set_2stage_config(schan))
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return;
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/*
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* Copy the DMA configuration from DMA descriptor to this hardware
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* channel.
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@ -427,6 +519,7 @@ static void sprd_dma_stop(struct sprd_dma_chn *schan)
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sprd_dma_stop_and_disable(schan);
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sprd_dma_unset_uid(schan);
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sprd_dma_clear_int(schan);
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schan->cur_desc = NULL;
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}
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static bool sprd_dma_check_trans_done(struct sprd_dma_desc *sdesc,
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@ -450,7 +543,7 @@ static irqreturn_t dma_irq_handle(int irq, void *dev_id)
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struct sprd_dma_desc *sdesc;
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enum sprd_dma_req_mode req_type;
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enum sprd_dma_int_type int_type;
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bool trans_done = false;
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bool trans_done = false, cyclic = false;
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u32 i;
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while (irq_status) {
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@ -465,13 +558,19 @@ static irqreturn_t dma_irq_handle(int irq, void *dev_id)
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sdesc = schan->cur_desc;
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/* Check if the dma request descriptor is done. */
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trans_done = sprd_dma_check_trans_done(sdesc, int_type,
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req_type);
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if (trans_done == true) {
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vchan_cookie_complete(&sdesc->vd);
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schan->cur_desc = NULL;
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sprd_dma_start(schan);
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/* cyclic mode schedule callback */
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cyclic = schan->linklist.phy_addr ? true : false;
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if (cyclic == true) {
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vchan_cyclic_callback(&sdesc->vd);
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} else {
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/* Check if the dma request descriptor is done. */
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trans_done = sprd_dma_check_trans_done(sdesc, int_type,
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req_type);
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if (trans_done == true) {
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vchan_cookie_complete(&sdesc->vd);
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schan->cur_desc = NULL;
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sprd_dma_start(schan);
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}
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}
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spin_unlock(&schan->vc.lock);
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}
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@ -534,7 +633,12 @@ static enum dma_status sprd_dma_tx_status(struct dma_chan *chan,
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else
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pos = 0;
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} else if (schan->cur_desc && schan->cur_desc->vd.tx.cookie == cookie) {
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pos = sprd_dma_get_dst_addr(schan);
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struct sprd_dma_desc *sdesc = to_sprd_dma_desc(vd);
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if (sdesc->dir == DMA_DEV_TO_MEM)
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pos = sprd_dma_get_dst_addr(schan);
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else
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pos = sprd_dma_get_src_addr(schan);
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} else {
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pos = 0;
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}
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@ -593,6 +697,7 @@ static int sprd_dma_fill_desc(struct dma_chan *chan,
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{
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struct sprd_dma_dev *sdev = to_sprd_dma_dev(chan);
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struct sprd_dma_chn *schan = to_sprd_dma_chan(chan);
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enum sprd_dma_chn_mode chn_mode = schan->chn_mode;
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u32 req_mode = (flags >> SPRD_DMA_REQ_SHIFT) & SPRD_DMA_REQ_MODE_MASK;
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u32 int_mode = flags & SPRD_DMA_INT_MASK;
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int src_datawidth, dst_datawidth, src_step, dst_step;
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@ -604,7 +709,16 @@ static int sprd_dma_fill_desc(struct dma_chan *chan,
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dev_err(sdev->dma_dev.dev, "invalid source step\n");
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return src_step;
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}
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dst_step = SPRD_DMA_NONE_STEP;
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/*
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* For 2-stage transfer, destination channel step can not be 0,
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* since destination device is AON IRAM.
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*/
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if (chn_mode == SPRD_DMA_DST_CHN0 ||
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chn_mode == SPRD_DMA_DST_CHN1)
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dst_step = src_step;
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else
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dst_step = SPRD_DMA_NONE_STEP;
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} else {
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dst_step = sprd_dma_get_step(slave_cfg->dst_addr_width);
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if (dst_step < 0) {
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@ -674,13 +788,11 @@ static int sprd_dma_fill_desc(struct dma_chan *chan,
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/* link-list configuration */
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if (schan->linklist.phy_addr) {
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if (sg_index == sglen - 1)
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hw->frg_len |= SPRD_DMA_LLIST_END;
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hw->cfg |= SPRD_DMA_LINKLIST_EN;
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/* link-list index */
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temp = (sg_index + 1) % sglen;
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temp = sglen ? (sg_index + 1) % sglen : 0;
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/* Next link-list configuration's physical address offset */
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temp = temp * sizeof(*hw) + SPRD_DMA_CHN_SRC_ADDR;
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/*
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@ -804,6 +916,8 @@ sprd_dma_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
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if (!sdesc)
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return NULL;
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sdesc->dir = dir;
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for_each_sg(sgl, sg, sglen, i) {
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len = sg_dma_len(sg);
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@ -831,6 +945,12 @@ sprd_dma_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
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}
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}
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/* Set channel mode and trigger mode for 2-stage transfer */
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schan->chn_mode =
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(flags >> SPRD_DMA_CHN_MODE_SHIFT) & SPRD_DMA_CHN_MODE_MASK;
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schan->trg_mode =
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(flags >> SPRD_DMA_TRG_MODE_SHIFT) & SPRD_DMA_TRG_MODE_MASK;
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ret = sprd_dma_fill_desc(chan, &sdesc->chn_hw, 0, 0, src, dst, len,
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dir, flags, slave_cfg);
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if (ret) {
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@ -847,9 +967,6 @@ static int sprd_dma_slave_config(struct dma_chan *chan,
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struct sprd_dma_chn *schan = to_sprd_dma_chan(chan);
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struct dma_slave_config *slave_cfg = &schan->slave_cfg;
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if (!is_slave_direction(config->direction))
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return -EINVAL;
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memcpy(slave_cfg, config, sizeof(*config));
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return 0;
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}
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@ -1109,4 +1226,5 @@ module_platform_driver(sprd_dma_driver);
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MODULE_LICENSE("GPL v2");
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MODULE_DESCRIPTION("DMA driver for Spreadtrum");
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MODULE_AUTHOR("Baolin Wang <baolin.wang@spreadtrum.com>");
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MODULE_AUTHOR("Eric Long <eric.long@spreadtrum.com>");
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MODULE_ALIAS("platform:sprd-dma");
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@ -3,9 +3,65 @@
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#ifndef _SPRD_DMA_H_
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#define _SPRD_DMA_H_
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#define SPRD_DMA_REQ_SHIFT 16
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#define SPRD_DMA_FLAGS(req_mode, int_type) \
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((req_mode) << SPRD_DMA_REQ_SHIFT | (int_type))
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#define SPRD_DMA_REQ_SHIFT 8
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#define SPRD_DMA_TRG_MODE_SHIFT 16
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#define SPRD_DMA_CHN_MODE_SHIFT 24
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#define SPRD_DMA_FLAGS(chn_mode, trg_mode, req_mode, int_type) \
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((chn_mode) << SPRD_DMA_CHN_MODE_SHIFT | \
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(trg_mode) << SPRD_DMA_TRG_MODE_SHIFT | \
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(req_mode) << SPRD_DMA_REQ_SHIFT | (int_type))
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/*
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* The Spreadtrum DMA controller supports channel 2-stage tansfer, that means
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* we can request 2 dma channels, one for source channel, and another one for
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* destination channel. Each channel is independent, and has its own
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* configurations. Once the source channel's transaction is done, it will
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* trigger the destination channel's transaction automatically by hardware
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* signal.
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*
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* To support 2-stage tansfer, we must configure the channel mode and trigger
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* mode as below definition.
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*/
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/*
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* enum sprd_dma_chn_mode: define the DMA channel mode for 2-stage transfer
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* @SPRD_DMA_CHN_MODE_NONE: No channel mode setting which means channel doesn't
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* support the 2-stage transfer.
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* @SPRD_DMA_SRC_CHN0: Channel used as source channel 0.
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* @SPRD_DMA_SRC_CHN1: Channel used as source channel 1.
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* @SPRD_DMA_DST_CHN0: Channel used as destination channel 0.
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* @SPRD_DMA_DST_CHN1: Channel used as destination channel 1.
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*
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* Now the DMA controller can supports 2 groups 2-stage transfer.
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*/
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enum sprd_dma_chn_mode {
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SPRD_DMA_CHN_MODE_NONE,
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SPRD_DMA_SRC_CHN0,
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SPRD_DMA_SRC_CHN1,
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SPRD_DMA_DST_CHN0,
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SPRD_DMA_DST_CHN1,
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};
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/*
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* enum sprd_dma_trg_mode: define the DMA channel trigger mode for 2-stage
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* transfer
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* @SPRD_DMA_NO_TRG: No trigger setting.
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* @SPRD_DMA_FRAG_DONE_TRG: Trigger the transaction of destination channel
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* automatically once the source channel's fragment request is done.
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* @SPRD_DMA_BLOCK_DONE_TRG: Trigger the transaction of destination channel
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* automatically once the source channel's block request is done.
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* @SPRD_DMA_TRANS_DONE_TRG: Trigger the transaction of destination channel
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* automatically once the source channel's transfer request is done.
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* @SPRD_DMA_LIST_DONE_TRG: Trigger the transaction of destination channel
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* automatically once the source channel's link-list request is done.
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*/
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enum sprd_dma_trg_mode {
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SPRD_DMA_NO_TRG,
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SPRD_DMA_FRAG_DONE_TRG,
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SPRD_DMA_BLOCK_DONE_TRG,
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SPRD_DMA_TRANS_DONE_TRG,
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SPRD_DMA_LIST_DONE_TRG,
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};
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/*
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* enum sprd_dma_req_mode: define the DMA request mode
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|
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