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arm64: barriers: make use of barrier options with explicit barriers

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When calling our low-level barrier macros directly, we can often suffice
with more relaxed behaviour than the default "all accesses, full system"
option.

This patch updates the users of dsb() to specify the option which they
actually require.

Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
This commit is contained in:
Will Deacon 2014-05-02 16:24:10 +01:00 committed by Catalin Marinas
parent fa48e6f780
commit 98f7685ee6
6 changed files with 15 additions and 15 deletions
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2
arch/arm64/include/asm/barrier.h
View File

@ -28,7 +28,7 @@
#define dmb(opt) asm volatile("dmb sy" : : : "memory")
#define dsb(opt) asm volatile("dsb sy" : : : "memory")
#define mb() dsb()
#define mb() dsb(sy)
#define rmb() asm volatile("dsb ld" : : : "memory")
#define wmb() asm volatile("dsb st" : : : "memory")

4
arch/arm64/include/asm/cacheflush.h
View File

@ -123,7 +123,7 @@ extern void flush_dcache_page(struct page *);
static inline void __flush_icache_all(void)
{
asm("ic ialluis");
dsb();
dsb(ish);
}
#define flush_dcache_mmap_lock(mapping) \
@ -150,7 +150,7 @@ static inline void flush_cache_vmap(unsigned long start, unsigned long end)
* set_pte_at() called from vmap_pte_range() does not
* have a DSB after cleaning the cache line.
*/
dsb();
dsb(ish);
}
static inline void flush_cache_vunmap(unsigned long start, unsigned long end)

4
arch/arm64/include/asm/pgtable.h
View File

@ -303,7 +303,7 @@ extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
static inline void set_pmd(pmd_t *pmdp, pmd_t pmd)
{
*pmdp = pmd;
dsb();
dsb(ishst);
}
static inline void pmd_clear(pmd_t *pmdp)
@ -333,7 +333,7 @@ static inline pte_t *pmd_page_vaddr(pmd_t pmd)
static inline void set_pud(pud_t *pudp, pud_t pud)
{
*pudp = pud;
dsb();
dsb(ishst);
}
static inline void pud_clear(pud_t *pudp)

14
arch/arm64/include/asm/tlbflush.h
View File

@ -72,9 +72,9 @@ extern struct cpu_tlb_fns cpu_tlb;
*/
static inline void flush_tlb_all(void)
{
dsb();
dsb(ishst);
asm("tlbi vmalle1is");
dsb();
dsb(ish);
isb();
}
@ -82,9 +82,9 @@ static inline void flush_tlb_mm(struct mm_struct *mm)
{
unsigned long asid = (unsigned long)ASID(mm) << 48;
dsb();
dsb(ishst);
asm("tlbi aside1is, %0" : : "r" (asid));
dsb();
dsb(ish);
}
static inline void flush_tlb_page(struct vm_area_struct *vma,
@ -93,9 +93,9 @@ static inline void flush_tlb_page(struct vm_area_struct *vma,
unsigned long addr = uaddr >> 12 |
((unsigned long)ASID(vma->vm_mm) << 48);
dsb();
dsb(ishst);
asm("tlbi vae1is, %0" : : "r" (addr));
dsb();
dsb(ish);
}
static inline void flush_tlb_range(struct vm_area_struct *vma,
@ -134,7 +134,7 @@ static inline void update_mmu_cache(struct vm_area_struct *vma,
* set_pte() does not have a DSB, so make sure that the page table
* write is visible.
*/
dsb();
dsb(ishst);
}
#define update_mmu_cache_pmd(vma, address, pmd) do { } while (0)

2
arch/arm64/kernel/process.c
View File

@ -300,7 +300,7 @@ struct task_struct *__switch_to(struct task_struct *prev,
* Complete any pending TLB or cache maintenance on this CPU in case
* the thread migrates to a different CPU.
*/
dsb();
dsb(ish);
/* the actual thread switch */
last = cpu_switch_to(prev, next);

4
arch/arm64/kvm/sys_regs.c
View File

@ -71,13 +71,13 @@ static u32 get_ccsidr(u32 csselr)
static void do_dc_cisw(u32 val)
{
asm volatile("dc cisw, %x0" : : "r" (val));
dsb();
dsb(ish);
}
static void do_dc_csw(u32 val)
{
asm volatile("dc csw, %x0" : : "r" (val));
dsb();
dsb(ish);
}
/* See note at ARM ARM B1.14.4 */