drm/amdgpu: add vcn nbio doorbell range setting for 2nd vcn instance

add vcn nbio doorbell range setting for 2nd vcn instance

Signed-off-by: James Zhu <James.Zhu@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
James Zhu 2019-07-10 10:50:24 -05:00 committed by Alex Deucher
parent 8b75a521c0
commit 989b6a0549
5 changed files with 21 additions and 7 deletions

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@ -674,7 +674,7 @@ struct amdgpu_nbio_funcs {
void (*sdma_doorbell_range)(struct amdgpu_device *adev, int instance,
bool use_doorbell, int doorbell_index, int doorbell_size);
void (*vcn_doorbell_range)(struct amdgpu_device *adev, bool use_doorbell,
int doorbell_index);
int doorbell_index, int instance);
void (*enable_doorbell_aperture)(struct amdgpu_device *adev,
bool enable);
void (*enable_doorbell_selfring_aperture)(struct amdgpu_device *adev,

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@ -92,7 +92,7 @@ static void nbio_v2_3_sdma_doorbell_range(struct amdgpu_device *adev, int instan
}
static void nbio_v2_3_vcn_doorbell_range(struct amdgpu_device *adev, bool use_doorbell,
int doorbell_index)
int doorbell_index, int instance)
{
u32 reg = SOC15_REG_OFFSET(NBIO, 0, mmBIF_MMSCH0_DOORBELL_RANGE);

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@ -42,6 +42,14 @@
#define GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK 0x00010000L
#define GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK 0x00020000L
#define mmBIF_MMSCH1_DOORBELL_RANGE 0x01dc
#define mmBIF_MMSCH1_DOORBELL_RANGE_BASE_IDX 2
//BIF_MMSCH1_DOORBELL_RANGE
#define BIF_MMSCH1_DOORBELL_RANGE__OFFSET__SHIFT 0x2
#define BIF_MMSCH1_DOORBELL_RANGE__SIZE__SHIFT 0x10
#define BIF_MMSCH1_DOORBELL_RANGE__OFFSET_MASK 0x00000FFCL
#define BIF_MMSCH1_DOORBELL_RANGE__SIZE_MASK 0x001F0000L
static void nbio_v7_4_remap_hdp_registers(struct amdgpu_device *adev)
{
WREG32_SOC15(NBIO, 0, mmREMAP_HDP_MEM_FLUSH_CNTL,
@ -115,11 +123,17 @@ static void nbio_v7_4_sdma_doorbell_range(struct amdgpu_device *adev, int instan
}
static void nbio_v7_4_vcn_doorbell_range(struct amdgpu_device *adev, bool use_doorbell,
int doorbell_index)
int doorbell_index, int instance)
{
u32 reg = SOC15_REG_OFFSET(NBIO, 0, mmBIF_MMSCH0_DOORBELL_RANGE);
u32 reg;
u32 doorbell_range;
u32 doorbell_range = RREG32(reg);
if (instance)
reg = SOC15_REG_OFFSET(NBIO, 0, mmBIF_MMSCH1_DOORBELL_RANGE);
else
reg = SOC15_REG_OFFSET(NBIO, 0, mmBIF_MMSCH0_DOORBELL_RANGE);
doorbell_range = RREG32(reg);
if (use_doorbell) {
doorbell_range = REG_SET_FIELD(doorbell_range,

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@ -245,7 +245,7 @@ static int vcn_v2_0_hw_init(void *handle)
int i, r;
adev->nbio_funcs->vcn_doorbell_range(adev, ring->use_doorbell,
ring->doorbell_index);
ring->doorbell_index, 0);
ring->sched.ready = true;
r = amdgpu_ring_test_ring(ring);

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@ -212,7 +212,7 @@ static int vcn_v2_5_hw_init(void *handle)
int i, r;
adev->nbio_funcs->vcn_doorbell_range(adev, ring->use_doorbell,
ring->doorbell_index);
ring->doorbell_index, 0);
r = amdgpu_ring_test_ring(ring);
if (r) {