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Samsung S5PV210 DT support for v3.17

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- support common clock framework for s5pv210 clock
 - add generic PHY driver on s5pv210 to support it via DT
 - add dt support for s5pv210-goni, smdkc110, smdkv210 and torbreck boards
 - remove board files from mach-s5pv210 and unused codes
 - enable multiplatform for s5pv210
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Merge tag 's5pv210-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into next/soc

Merge "Samsung S5PV210 DT support for v3.17" from Kukjin Kim:

- support common clock framework for s5pv210 clock
- add generic PHY driver on s5pv210 to support it via DT
- add dt support for s5pv210-goni, smdkc110, smdkv210 and torbreck boards
- remove board files from mach-s5pv210 and unused codes
- enable multiplatform for s5pv210

* tag 's5pv210-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung:
  clk: samsung: s5pv210: Remove legacy board support
  ARM: SAMSUNG: Remove remaining legacy code
  gpio: samsung: Remove legacy support of S5PV210
  ARM: S5PV210: Enable multi-platform build support
  cpufreq: s5pv210: Make the driver multiplatform aware
  ARM: S5PV210: Register cpufreq platform device
  ARM: S5PV210: move debug-macro.S into the common space
  ARM: S5PV210: Untie PM support from legacy code
  ARM: S5PV210: Remove support for board files
  ARM: dts: Add Device tree for s5pc110/s5pv210 boards
  ARM: dts: Add Device tree for s5pv210 SoC
  ARM: S5PV210: Add board file for boot using Device Tree
  phy: Add support for S5PV210 to the Exynos USB 2.0 PHY driver
  clk: samsung: Add S5PV210 Audio Subsystem clock driver
  ARM: SAMSUNG: Remove legacy clock code
  serial: samsung: Remove support for legacy clock code
  cpufreq: s3c24xx: Remove some dead code
  ARM: S5PV210: Migrate clock handling to Common Clock Framework
  clk: samsung: Add clock driver for S5PV210 and compatible SoCs

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2014-07-26 12:01:10 +02:00
commit 96bda115ec
123 changed files with 4788 additions and 9354 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

53
Documentation/devicetree/bindings/clock/clk-s5pv210-audss.txt Normal file
View File

@ -0,0 +1,53 @@
* Samsung Audio Subsystem Clock Controller
The Samsung Audio Subsystem clock controller generates and supplies clocks
to Audio Subsystem block available in the S5PV210 and compatible SoCs.
Required Properties:
- compatible: should be "samsung,s5pv210-audss-clock".
- reg: physical base address and length of the controller's register set.
- #clock-cells: should be 1.
- clocks:
- hclk: AHB bus clock of the Audio Subsystem.
- xxti: Optional fixed rate PLL reference clock, parent of mout_audss. If
not specified (i.e. xusbxti is used for PLL reference), it is fixed to
a clock named "xxti".
- fout_epll: Input PLL to the AudioSS block, parent of mout_audss.
- iiscdclk0: Optional external i2s clock, parent of mout_i2s. If not
specified, it is fixed to a clock named "iiscdclk0".
- sclk_audio0: Audio bus clock, parent of mout_i2s.
- clock-names: Aliases for the above clocks. They should be "hclk",
"xxti", "fout_epll", "iiscdclk0", and "sclk_audio0" respectively.
All available clocks are defined as preprocessor macros in
dt-bindings/clock/s5pv210-audss-clk.h header and can be used in device
tree sources.
Example: Clock controller node.
clk_audss: clock-controller@c0900000 {
compatible = "samsung,s5pv210-audss-clock";
reg = <0xc0900000 0x1000>;
#clock-cells = <1>;
clock-names = "hclk", "xxti",
"fout_epll", "sclk_audio0";
clocks = <&clocks DOUT_HCLKP>, <&xxti>,
<&clocks FOUT_EPLL>, <&clocks SCLK_AUDIO0>;
};
Example: I2S controller node that consumes the clock generated by the clock
controller. Refer to the standard clock bindings for information
about 'clocks' and 'clock-names' property.
i2s0: i2s@03830000 {
/* ... */
clock-names = "iis", "i2s_opclk0",
"i2s_opclk1";
clocks = <&clk_audss CLK_I2S>, <&clk_audss CLK_I2S>,
<&clk_audss CLK_DOUT_AUD_BUS>;
/* ... */
};

78
Documentation/devicetree/bindings/clock/samsung,s5pv210-clock.txt Normal file
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@ -0,0 +1,78 @@
* Samsung S5P6442/S5PC110/S5PV210 Clock Controller
Samsung S5P6442, S5PC110 and S5PV210 SoCs contain integrated clock
controller, which generates and supplies clock to various controllers
within the SoC.
Required Properties:
- compatible: should be one of following:
- "samsung,s5pv210-clock" : for clock controller of Samsung
S5PC110/S5PV210 SoCs,
- "samsung,s5p6442-clock" : for clock controller of Samsung
S5P6442 SoC.
- reg: physical base address of the controller and length of memory mapped
region.
- #clock-cells: should be 1.
All available clocks are defined as preprocessor macros in
dt-bindings/clock/s5pv210.h header and can be used in device tree sources.
External clocks:
There are several clocks that are generated outside the SoC. It is expected
that they are defined using standard clock bindings with following
clock-output-names:
- "xxti": external crystal oscillator connected to XXTI and XXTO pins of
the SoC,
- "xusbxti": external crystal oscillator connected to XUSBXTI and XUSBXTO
pins of the SoC,
A subset of above clocks available on given board shall be specified in
board device tree, including the system base clock, as selected by XOM[0]
pin of the SoC. Refer to generic fixed rate clock bindings
documentation[1] for more information how to specify these clocks.
[1] Documentation/devicetree/bindings/clock/fixed-clock.txt
Example: Clock controller node:
clock: clock-controller@7e00f000 {
compatible = "samsung,s5pv210-clock";
reg = <0x7e00f000 0x1000>;
#clock-cells = <1>;
};
Example: Required external clocks:
xxti: clock-xxti {
compatible = "fixed-clock";
clock-output-names = "xxti";
clock-frequency = <24000000>;
#clock-cells = <0>;
};
xusbxti: clock-xusbxti {
compatible = "fixed-clock";
clock-output-names = "xusbxti";
clock-frequency = <24000000>;
#clock-cells = <0>;
};
Example: UART controller node that consumes the clock generated by the clock
controller (refer to the standard clock bindings for information about
"clocks" and "clock-names" properties):
uart0: serial@e2900000 {
compatible = "samsung,s5pv210-uart";
reg = <0xe2900000 0x400>;
interrupt-parent = <&vic1>;
interrupts = <10>;
clock-names = "uart", "clk_uart_baud0",
"clk_uart_baud1";
clocks = <&clocks UART0>, <&clocks UART0>,
<&clocks SCLK_UART0>;
status = "disabled";
};

1
Documentation/devicetree/bindings/phy/samsung-phy.txt
View File

@ -26,6 +26,7 @@ Samsung S5P/EXYNOS SoC series USB PHY
Required properties:
- compatible : should be one of the listed compatibles:
- "samsung,s5pv210-usb2-phy"
- "samsung,exynos4210-usb2-phy"
- "samsung,exynos4x12-usb2-phy"
- "samsung,exynos5250-usb2-phy"

22
arch/arm/Kconfig
View File

@ -744,25 +744,6 @@ config ARCH_S3C64XX
help
Samsung S3C64XX series based systems
config ARCH_S5PV210
bool "Samsung S5PV210/S5PC110"
select ARCH_HAS_HOLES_MEMORYMODEL
select ARCH_SPARSEMEM_ENABLE
select ATAGS
select CLKDEV_LOOKUP
select CLKSRC_SAMSUNG_PWM
select CPU_V7
select GENERIC_CLOCKEVENTS
select GPIO_SAMSUNG
select HAVE_S3C2410_I2C if I2C
select HAVE_S3C2410_WATCHDOG if WATCHDOG
select HAVE_S3C_RTC if RTC_CLASS
select NEED_MACH_GPIO_H
select NEED_MACH_MEMORY_H
select SAMSUNG_ATAGS
help
Samsung S5PV210/S5PC110 series based systems
config ARCH_DAVINCI
bool "TI DaVinci"
select ARCH_HAS_HOLES_MEMORYMODEL
@ -1500,7 +1481,8 @@ config ARM_PSCI
config ARCH_NR_GPIO
int
default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX
default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \
SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210
default 416 if ARCH_SUNXI
default 392 if ARCH_U8500
default 352 if ARCH_VT8500

12
arch/arm/Kconfig.debug
View File

@ -617,6 +617,7 @@ choice
depends on PLAT_SAMSUNG
select DEBUG_EXYNOS_UART if ARCH_EXYNOS
select DEBUG_S3C24XX_UART if ARCH_S3C24XX
select DEBUG_S5PV210_UART if ARCH_S5PV210
bool "Use Samsung S3C UART 0 for low-level debug"
help
Say Y here if you want the debug print routines to direct
@ -627,6 +628,7 @@ choice
depends on PLAT_SAMSUNG
select DEBUG_EXYNOS_UART if ARCH_EXYNOS
select DEBUG_S3C24XX_UART if ARCH_S3C24XX
select DEBUG_S5PV210_UART if ARCH_S5PV210
bool "Use Samsung S3C UART 1 for low-level debug"
help
Say Y here if you want the debug print routines to direct
@ -637,6 +639,7 @@ choice
depends on PLAT_SAMSUNG
select DEBUG_EXYNOS_UART if ARCH_EXYNOS
select DEBUG_S3C24XX_UART if ARCH_S3C24XX
select DEBUG_S5PV210_UART if ARCH_S5PV210
bool "Use Samsung S3C UART 2 for low-level debug"
help
Say Y here if you want the debug print routines to direct
@ -644,8 +647,9 @@ choice
by the boot-loader before use.
config DEBUG_S3C_UART3
depends on PLAT_SAMSUNG && ARCH_EXYNOS
select DEBUG_EXYNOS_UART
depends on PLAT_SAMSUNG && (ARCH_EXYNOS || ARCH_S5PV210)
select DEBUG_EXYNOS_UART if ARCH_EXYNOS
select DEBUG_S5PV210_UART if ARCH_S5PV210
bool "Use Samsung S3C UART 3 for low-level debug"
help
Say Y here if you want the debug print routines to direct
@ -945,6 +949,9 @@ config DEBUG_S3C2410_UART
config DEBUG_S3C24XX_UART
bool
config DEBUG_S5PV210_UART
bool
config DEBUG_OMAP2PLUS_UART
bool
depends on ARCH_OMAP2PLUS
@ -1005,6 +1012,7 @@ config DEBUG_LL_INCLUDE
default "debug/msm.S" if DEBUG_MSM_UART || DEBUG_QCOM_UARTDM
default "debug/omap2plus.S" if DEBUG_OMAP2PLUS_UART
default "debug/s3c24xx.S" if DEBUG_S3C24XX_UART
default "debug/s5pv210.S" if DEBUG_S5PV210_UART
default "debug/sirf.S" if DEBUG_SIRFPRIMA2_UART1 || DEBUG_SIRFMARCO_UART1
default "debug/sti.S" if DEBUG_STI_UART
default "debug/tegra.S" if DEBUG_TEGRA_UART

4
arch/arm/Makefile
View File

@ -210,11 +210,11 @@ machine-$(CONFIG_PLAT_SPEAR) += spear
plat-$(CONFIG_ARCH_EXYNOS) += samsung
plat-$(CONFIG_ARCH_OMAP) += omap
plat-$(CONFIG_ARCH_S3C64XX) += samsung
plat-$(CONFIG_ARCH_S5PV210) += samsung
plat-$(CONFIG_PLAT_IOP) += iop
plat-$(CONFIG_PLAT_ORION) += orion
plat-$(CONFIG_PLAT_PXA) += pxa
plat-$(CONFIG_PLAT_S3C24XX) += samsung
plat-$(CONFIG_PLAT_S5P) += samsung
plat-$(CONFIG_PLAT_VERSATILE) += versatile
ifeq ($(CONFIG_ARCH_EBSA110),y)
@ -238,7 +238,7 @@ MACHINE :=
endif
machdirs := $(patsubst %,arch/arm/mach-%/,$(machine-y))
platdirs := $(patsubst %,arch/arm/plat-%/,$(plat-y))
platdirs := $(patsubst %,arch/arm/plat-%/,$(sort $(plat-y)))
ifneq ($(CONFIG_ARCH_MULTIPLATFORM),y)
ifeq ($(KBUILD_SRC),)

5
arch/arm/boot/dts/Makefile
View File

@ -318,6 +318,11 @@ dtb-$(CONFIG_ARCH_QCOM) += \
dtb-$(CONFIG_ARCH_S3C24XX) += s3c2416-smdk2416.dtb
dtb-$(CONFIG_ARCH_S3C64XX) += s3c6410-mini6410.dtb \
s3c6410-smdk6410.dtb
dtb-$(CONFIG_ARCH_S5PV210) += s5pv210-aquila.dtb \
s5pv210-goni.dtb \
s5pv210-smdkc110.dtb \
s5pv210-smdkv210.dtb \
s5pv210-torbreck.dtb
dtb-$(CONFIG_ARCH_SHMOBILE_LEGACY) += r7s72100-genmai.dtb \
r8a7740-armadillo800eva.dtb \
r8a7778-bockw.dtb \

392
arch/arm/boot/dts/s5pv210-aquila.dts Normal file
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@ -0,0 +1,392 @@
/*
* Samsung's S5PV210 SoC device tree source
*
* Copyright (c) 2013-2014 Samsung Electronics, Co. Ltd.
*
* Mateusz Krawczuk <m.krawczuk@partner.samsung.com>
* Tomasz Figa <t.figa@samsung.com>
*
* Board device tree source for Samsung Aquila board.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/dts-v1/;
#include <dt-bindings/input/input.h>
#include "s5pv210.dtsi"
/ {
model = "Samsung Aquila based on S5PC110";
compatible = "samsung,aquila", "samsung,s5pv210";
aliases {
i2c3 = &i2c_pmic;
};
chosen {
bootargs = "console=ttySAC2,115200n8 root=/dev/mmcblk1p5 rw rootwait ignore_loglevel earlyprintk";
};
memory {
device_type = "memory";
reg = <0x30000000 0x05000000
0x40000000 0x18000000>;
};
regulators {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
vtf_reg: fixed-regulator@0 {
compatible = "regulator-fixed";
reg = <0>;
regulator-name = "V_TF_2.8V";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
gpios = <&mp05 4 0>;
enable-active-high;
};
pda_reg: fixed-regulator@1 {
compatible = "regulator-fixed";
regulator-name = "VCC_1.8V_PDA";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
reg = <1>;
};
bat_reg: fixed-regulator@2 {
compatible = "regulator-fixed";
regulator-name = "V_BAT";
regulator-min-microvolt = <3700000>;
regulator-max-microvolt = <3700000>;
reg = <2>;
};
};
i2c_pmic: i2c-pmic {
compatible = "i2c-gpio";
gpios = <&gpj4 0 0>, /* sda */
<&gpj4 3 0>; /* scl */
i2c-gpio,delay-us = <2>; /* ~100 kHz */
#address-cells = <1>;
#size-cells = <0>;
pmic@66 {
compatible = "national,lp3974";
reg = <0x66>;
max8998,pmic-buck1-default-dvs-idx = <0>;
max8998,pmic-buck1-dvs-gpios = <&gph0 3 0>,
<&gph0 4 0>;
max8998,pmic-buck1-dvs-voltage = <1200000>, <1200000>,
<1200000>, <1200000>;
max8998,pmic-buck2-default-dvs-idx = <0>;
max8998,pmic-buck2-dvs-gpio = <&gph0 5 0>;
max8998,pmic-buck2-dvs-voltage = <1200000>, <1200000>;
regulators {
ldo2_reg: LDO2 {
regulator-name = "VALIVE_1.1V";
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1100000>;
regulator-always-on;
};
ldo3_reg: LDO3 {
regulator-name = "VUSB+MIPI_1.1V";
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1100000>;
regulator-always-on;
};
ldo4_reg: LDO4 {
regulator-name = "VADC_3.3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
ldo5_reg: LDO5 {
regulator-name = "VTF_2.8V";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
regulator-always-on;
};
ldo6_reg: LDO6 {
regulator-name = "VCC_3.3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
ldo7_reg: LDO7 {
regulator-name = "VCC_3.0V";
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
regulator-always-on;
regulator-boot-on;
};
ldo8_reg: LDO8 {
regulator-name = "VUSB+VDAC_3.3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
ldo9_reg: LDO9 {
regulator-name = "VCC+VCAM_2.8V";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
regulator-always-on;
};
ldo10_reg: LDO10 {
regulator-name = "VPLL_1.1V";
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1100000>;
regulator-always-on;
regulator-boot-on;
};
ldo11_reg: LDO11 {
regulator-name = "CAM_IO_2.8V";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
regulator-always-on;
};
ldo12_reg: LDO12 {
regulator-name = "CAM_ISP_1.2V";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-always-on;
};
ldo13_reg: LDO13 {
regulator-name = "CAM_A_2.8V";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
regulator-always-on;
};
ldo14_reg: LDO14 {
regulator-name = "CAM_CIF_1.8V";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
};
ldo15_reg: LDO15 {
regulator-name = "CAM_AF_3.3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
ldo16_reg: LDO16 {
regulator-name = "VMIPI_1.8V";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
};
ldo17_reg: LDO17 {
regulator-name = "CAM_8M_1.8V";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
};
buck1_reg: BUCK1 {
regulator-name = "VARM_1.2V";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-always-on;
};
buck2_reg: BUCK2 {
regulator-name = "VINT_1.2V";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-always-on;
};
buck3_reg: BUCK3 {
regulator-name = "VCC_1.8V";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
};
buck4_reg: BUCK4 {
regulator-name = "CAM_CORE_1.2V";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-always-on;
};
vichg_reg: ENVICHG {
regulator-name = "VICHG";
};
safeout1_reg: ESAFEOUT1 {
regulator-name = "SAFEOUT1";
regulator-always-on;
};
safeout2_reg: ESAFEOUT2 {
regulator-name = "SAFEOUT2";
regulator-boot-on;
};
};
};
};
gpio-keys {
compatible = "gpio-keys";
power-key {
gpios = <&gph2 6 1>;
linux,code = <KEY_POWER>;
label = "power";
debounce-interval = <1>;
gpio-key,wakeup;
};
};
};
&xusbxti {
clock-frequency = <24000000>;
};
&keypad {
linux,input-no-autorepeat;
linux,input-wakeup;
samsung,keypad-num-rows = <3>;
samsung,keypad-num-columns = <3>;
pinctrl-names = "default";
pinctrl-0 = <&keypad_row0>, <&keypad_row1>, <&keypad_row2>,
<&keypad_col0>, <&keypad_col1>, <&keypad_col2>;
status = "okay";
key_1 {
keypad,row = <0>;
keypad,column = <1>;
linux,code = <KEY_CONNECT>;
};
key_2 {
keypad,row = <0>;
keypad,column = <2>;
linux,code = <KEY_BACK>;
};
key_3 {
keypad,row = <1>;
keypad,column = <1>;
linux,code = <KEY_CAMERA_FOCUS>;
};
key_4 {
keypad,row = <1>;
keypad,column = <2>;
linux,code = <KEY_VOLUMEUP>;
};
key_5 {
keypad,row = <2>;
keypad,column = <1>;
linux,code = <KEY_CAMERA>;
};
key_6 {
keypad,row = <2>;
keypad,column = <2>;
linux,code = <KEY_VOLUMEDOWN>;
};
};
&uart0 {
status = "okay";
};
&uart1 {
status = "okay";
};
&uart2 {
status = "okay";
};
&uart3 {
status = "okay";
};
&sdhci0 {
bus-width = <4>;
non-removable;
status = "okay";
vmmc-supply = <&ldo5_reg>;
pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4>;
pinctrl-names = "default";
};
&sdhci2 {
bus-width = <4>;
cd-gpios = <&gph3 4 1>;
vmmc-supply = <&vtf_reg>;
cd-inverted;
pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus4 &t_flash_detect>;
pinctrl-names = "default";
status = "okay";
};
&onenand {
status = "okay";
};
&hsotg {
vusb_a-supply = <&ldo3_reg>;
vusb_d-supply = <&ldo8_reg>;
status = "okay";
};
&usbphy {
status = "okay";
};
&fimd {
pinctrl-0 = <&lcd_clk &lcd_data24 &pwm1_out>;
pinctrl-names = "default";
status = "okay";
display-timings {
native-mode = <&timing0>;
timing0: timing {
clock-frequency = <0>;
hactive = <800>;
vactive = <480>;
hfront-porch = <16>;
hback-porch = <16>;
hsync-len = <2>;
vback-porch = <3>;
vfront-porch = <28>;
vsync-len = <1>;
};
};
};
&pinctrl0 {
t_flash_detect: t-flash-detect {
samsung,pins = "gph3-4";
samsung,pin-function = <0>;
samsung,pin-pud = <0>;
};
};

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/*
* Samsung's S5PV210 SoC device tree source
*
* Copyright (c) 2013-2014 Samsung Electronics, Co. Ltd.
*
* Mateusz Krawczuk <m.krawczuk@partner.samsung.com>
* Tomasz Figa <t.figa@samsung.com>
*
* Board device tree source for Samsung Goni board.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/dts-v1/;
#include <dt-bindings/input/input.h>
#include "s5pv210.dtsi"
/ {
model = "Samsung Goni based on S5PC110";
compatible = "samsung,goni", "samsung,s5pv210";
aliases {
i2c3 = &i2c_pmic;
};
chosen {
bootargs = "console=ttySAC0,115200n8 root=/dev/mmcblk0p5 rw rootwait ignore_loglevel earlyprintk";
};
memory {
device_type = "memory";
reg = <0x30000000 0x05000000
0x40000000 0x10000000
0x50000000 0x08000000>;
};
regulators {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
vtf_reg: fixed-regulator@0 {
compatible = "regulator-fixed";
regulator-name = "V_TF_2.8V";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
reg = <0>;
gpios = <&mp05 4 0>;
enable-active-high;
};
pda_reg: fixed-regulator@1 {
compatible = "regulator-fixed";
regulator-name = "VCC_1.8V_PDA";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
reg = <1>;
};
bat_reg: fixed-regulator@2 {
compatible = "regulator-fixed";
regulator-name = "V_BAT";
regulator-min-microvolt = <3700000>;
regulator-max-microvolt = <3700000>;
reg = <2>;
};
tsp_reg: fixed-regulator@3 {
compatible = "regulator-fixed";
regulator-name = "TSP_VDD";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
reg = <3>;
gpios = <&gpj1 3 0>;
enable-active-high;
};
};
i2c_pmic: i2c-pmic {
compatible = "i2c-gpio";
gpios = <&gpj4 0 0>, /* sda */
<&gpj4 3 0>; /* scl */
i2c-gpio,delay-us = <2>; /* ~100 kHz */
#address-cells = <1>;
#size-cells = <0>;
pmic@66 {
compatible = "national,lp3974";
reg = <0x66>;
max8998,pmic-buck1-default-dvs-idx = <0>;
max8998,pmic-buck1-dvs-gpios = <&gph0 3 0>,
<&gph0 4 0>;
max8998,pmic-buck1-dvs-voltage = <1200000>, <1200000>,
<1200000>, <1200000>;
max8998,pmic-buck2-default-dvs-idx = <0>;
max8998,pmic-buck2-dvs-gpio = <&gph0 5 0>;
max8998,pmic-buck2-dvs-voltage = <1200000>, <1200000>;
regulators {
ldo2_reg: LDO2 {
regulator-name = "VALIVE_1.1V";
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1100000>;
regulator-always-on;
};
ldo3_reg: LDO3 {
regulator-name = "VUSB+MIPI_1.1V";
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1100000>;
regulator-always-on;
};
ldo4_reg: LDO4 {
regulator-name = "VADC_3.3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
ldo5_reg: LDO5 {
regulator-name = "VTF_2.8V";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
};
ldo6_reg: LDO6 {
regulator-name = "VCC_3.3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
ldo7_reg: LDO7 {
regulator-name = "VLCD_1.8V";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
};
ldo8_reg: LDO8 {
regulator-name = "VUSB+VDAC_3.3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
ldo9_reg: LDO9 {
regulator-name = "VCC+VCAM_2.8V";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
};
ldo10_reg: LDO10 {
regulator-name = "VPLL_1.1V";
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1100000>;
regulator-boot-on;
};
ldo11_reg: LDO11 {
regulator-name = "CAM_IO_2.8V";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
};
ldo12_reg: LDO12 {
regulator-name = "CAM_ISP_1.2V";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
};
ldo13_reg: LDO13 {
regulator-name = "CAM_A_2.8V";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
};
ldo14_reg: LDO14 {
regulator-name = "CAM_CIF_1.8V";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
ldo15_reg: LDO15 {
regulator-name = "CAM_AF_3.3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
ldo16_reg: LDO16 {
regulator-name = "VMIPI_1.8V";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
ldo17_reg: LDO17 {
regulator-name = "CAM_8M_1.8V";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
};
buck1_reg: BUCK1 {
regulator-name = "VARM_1.2V";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
};
buck2_reg: BUCK2 {
regulator-name = "VINT_1.2V";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
};
buck3_reg: BUCK3 {
regulator-name = "VCC_1.8V";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
};
buck4_reg: BUCK4 {
regulator-name = "CAM_CORE_1.2V";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-always-on;
};
};
};
};
gpio-keys {
compatible = "gpio-keys";
power-key {
gpios = <&gph2 6 1>;
linux,code = <KEY_POWER>;
label = "power";
debounce-interval = <1>;
gpio-key,wakeup;
};
};
};
&xusbxti {
clock-frequency = <24000000>;
};
&keypad {
linux,input-no-autorepeat;
linux,input-wakeup;
samsung,keypad-num-rows = <3>;
samsung,keypad-num-columns = <3>;
pinctrl-names = "default";
pinctrl-0 = <&keypad_row0>, <&keypad_row1>, <&keypad_row2>,
<&keypad_col0>, <&keypad_col1>, <&keypad_col2>;
status = "okay";
key_1 {
keypad,row = <0>;
keypad,column = <1>;
linux,code = <KEY_CONNECT>;
};
key_2 {
keypad,row = <0>;
keypad,column = <2>;
linux,code = <KEY_BACK>;
};
key_3 {
keypad,row = <1>;
keypad,column = <1>;
linux,code = <KEY_CAMERA_FOCUS>;
};
key_4 {
keypad,row = <1>;
keypad,column = <2>;
linux,code = <KEY_VOLUMEUP>;
};
key_5 {
keypad,row = <2>;
keypad,column = <1>;
linux,code = <KEY_CAMERA>;
};
key_6 {
keypad,row = <2>;
keypad,column = <2>;
linux,code = <KEY_VOLUMEDOWN>;
};
};
&uart0 {
status = "okay";
};
&uart1 {
status = "okay";
};
&uart2 {
status = "okay";
};
&uart3 {
status = "okay";
};
&sdhci0 {
bus-width = <4>;
non-removable;
vmmc-supply = <&ldo5_reg>;
pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_bus1 &sd0_bus4>;
pinctrl-names = "default";
status = "okay";
};
&sdhci2 {
bus-width = <4>;
cd-gpios = <&gph3 4 1>;
vmmc-supply = <&vtf_reg>;
cd-inverted;
pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus4>;
pinctrl-names = "default";
status = "okay";
};
&hsotg {
vusb_a-supply = <&ldo3_reg>;
vusb_d-supply = <&ldo8_reg>;
status = "okay";
};
&usbphy {
status = "okay";
};
&i2c2 {
samsung,i2c-sda-delay = <100>;
samsung,i2c-max-bus-freq = <400000>;
samsung,i2c-slave-addr = <0x10>;
status = "okay";
tsp@4a {
compatible = "atmel,maxtouch";
reg = <0x4a>;
interrupt-parent = <&gpj0>;
interrupts = <5 2>;
atmel,x-line = <17>;
atmel,y-line = <11>;
atmel,x-size = <800>;
atmel,y-size = <480>;
atmel,burst-length = <0x21>;
atmel,threshold = <0x28>;
atmel,orientation = <1>;
vdd-supply = <&tsp_reg>;
};
};
&i2c0 {
samsung,i2c-sda-delay = <100>;
samsung,i2c-max-bus-freq = <100000>;
samsung,i2c-slave-addr = <0x10>;
status = "okay";
noon010pc30: sensor@30 {
compatible = "siliconfile,noon010pc30";
reg = <0x30>;
vddio-supply = <&ldo11_reg>;
vdda-supply = <&ldo13_reg>;
vdd_core-supply = <&ldo14_reg>;
clock-frequency = <16000000>;
clocks = <&clock_cam 0>;
clock-names = "mclk";
nreset-gpios = <&gpb 2 0>;
nstby-gpios = <&gpb 0 0>;
port {
noon010pc30_ep: endpoint {
remote-endpoint = <&fimc0_ep>;
bus-width = <8>;
hsync-active = <0>;
vsync-active = <1>;
pclk-sample = <1>;
};
};
};
};
&camera {
pinctrl-0 = <&cam_port_a_io &cam_port_a_clk_active>;
pinctrl-1 = <&cam_port_a_io &cam_port_a_clk_idle>;
pinctrl-names = "default", "idle";
parallel-ports {
#address-cells = <1>;
#size-cells = <0>;
/* camera A input */
port@1 {
reg = <1>;
fimc0_ep: endpoint {
remote-endpoint = <&noon010pc30_ep>;
bus-width = <8>;
hsync-active = <1>;
vsync-active = <1>;
pclk-sample = <0>;
};
};
};
};
&fimd {
pinctrl-0 = <&lcd_clk &lcd_data24>;
pinctrl-names = "default";
status = "okay";
display-timings {
native-mode = <&timing0>;
timing0: timing {
/* 480x800@55Hz */
clock-frequency = <23439570>;
hactive = <480>;
hfront-porch = <16>;
hback-porch = <16>;
hsync-len = <2>;
vactive = <800>;
vback-porch = <2>;
vfront-porch = <28>;
vsync-len = <1>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <0>;
pixelclk-active = <0>;
};
};
};
&onenand {
status = "okay";
};

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/*
* Samsung's S5PV210 SoC device tree source
*
* Copyright (c) 2013-2014 Samsung Electronics, Co. Ltd.
*
* Mateusz Krawczuk <m.krawczuk@partner.samsung.com>
* Tomasz Figa <t.figa@samsung.com>
*
* Samsung's S5PV210 SoC device nodes are listed in this file. S5PV210
* based board files can include this file and provide values for board specfic
* bindings.
*
* Note: This file does not include device nodes for all the controllers in
* S5PV210 SoC. As device tree coverage for S5PV210 increases, additional
* nodes can be added to this file.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
&pinctrl0 {
gpa0: gpa0 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpa1: gpa1 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpb: gpb {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpc0: gpc0 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpc1: gpc1 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpd0: gpd0 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpd1: gpd1 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpe0: gpe0 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpe1: gpe1 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpf0: gpf0 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpf1: gpf1 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpf2: gpf2 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpf3: gpf3 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpg0: gpg0 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpg1: gpg1 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpg2: gpg2 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpg3: gpg3 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpj0: gpj0 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpj1: gpj1 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpj2: gpj2 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpj3: gpj3 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpj4: gpj4 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpgi: gpgi {
gpio-controller;
#gpio-cells = <2>;
};
mp01: mp01 {
gpio-controller;
#gpio-cells = <2>;
};
mp02: mp02 {
gpio-controller;
#gpio-cells = <2>;
};
mp03: mp03 {
gpio-controller;
#gpio-cells = <2>;
};
mp04: mp04 {
gpio-controller;
#gpio-cells = <2>;
};
mp05: mp05 {
gpio-controller;
#gpio-cells = <2>;
};
mp06: mp06 {
gpio-controller;
#gpio-cells = <2>;
};
mp07: mp07 {
gpio-controller;
#gpio-cells = <2>;
};
gph0: gph0 {
gpio-controller;
interrupt-controller;
interrupt-parent = <&vic0>;
interrupts = <0>, <1>, <2>, <3>,
<4>, <5>, <6>, <7>;
#gpio-cells = <2>;
#interrupt-cells = <2>;
};
gph1: gph1 {
gpio-controller;
interrupt-controller;
interrupt-parent = <&vic0>;
interrupts = <8>, <9>, <10>, <11>,
<12>, <13>, <14>, <15>;
#gpio-cells = <2>;
#interrupt-cells = <2>;
};
gph2: gph2 {
gpio-controller;
#gpio-cells = <2>;
#interrupt-cells = <2>;
};
gph3: gph3 {
gpio-controller;
#gpio-cells = <2>;
#interrupt-cells = <2>;
};
uart0_data: uart0-data {
samsung,pins = "gpa0-0", "gpa0-1";
samsung,pin-function = <2>;
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
};
uart0_fctl: uart0-fctl {
samsung,pins = "gpa0-2", "gpa0-3";
samsung,pin-function = <2>;
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
};
uart1_data: uart1-data {
samsung,pins = "gpa0-4", "gpa0-5";
samsung,pin-function = <2>;
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
};
uart1_fctl: uart1-fctl {
samsung,pins = "gpa0-6", "gpa0-7";
samsung,pin-function = <2>;
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
};
uart2_data: uart2-data {
samsung,pins = "gpa1-0", "gpa1-1";
samsung,pin-function = <2>;
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
};
uart2_fctl: uart2-fctl {
samsung,pins = "gpa1-2", "gpa1-3";
samsung,pin-function = <3>;
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
};
uart3_data: uart3-data {
samsung,pins = "gpa1-2", "gpa1-3";
samsung,pin-function = <2>;
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
};
uart_audio: uart-audio {
samsung,pins = "gpa1-2", "gpa1-3";
samsung,pin-function = <4>;
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
};
spi0_bus: spi0-bus {
samsung,pins = "gpb-0", "gpb-2", "gpb-3";
samsung,pin-function = <2>;
samsung,pin-pud = <2>;
samsung,pin-drv = <0>;
};
spi1_bus: spi1-bus {
samsung,pins = "gpb-4", "gpb-6", "gpb-7";
samsung,pin-function = <2>;
samsung,pin-pud = <2>;
samsung,pin-drv = <0>;
};
i2s0_bus: i2s0-bus {
samsung,pins = "gpi-0", "gpi-1", "gpi-2", "gpi-3",
"gpi-4", "gpi-5", "gpi-6";
samsung,pin-function = <2>;
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
};
i2s1_bus: i2s1-bus {
samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3",
"gpc0-4";
samsung,pin-function = <2>;
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
};
i2s2_bus: i2s2-bus {
samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3",
"gpc1-4";
samsung,pin-function = <4>;
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
};
pcm1_bus: pcm1-bus {
samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3",
"gpc0-4";
samsung,pin-function = <3>;
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
};
ac97_bus: ac97-bus {
samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3",
"gpc0-4";
samsung,pin-function = <4>;
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
};
i2s2_bus: i2s2-bus {
samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3",
"gpc1-4";
samsung,pin-function = <2>;
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
};
pcm2_bus: pcm2-bus {
samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3",
"gpc1-4";
samsung,pin-function = <3>;
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
};
spdif_bus: spdif-bus {
samsung,pins = "gpc1-0", "gpc1-1";
samsung,pin-function = <4>;
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
};
spi2_bus: spi2-bus {
samsung,pins = "gpc1-1", "gpc1-2", "gpc1-3", "gpc1-4";
samsung,pin-function = <5>;
samsung,pin-pud = <2>;
samsung,pin-drv = <0>;
};
i2c0_bus: i2c0-bus {
samsung,pins = "gpd1-0", "gpd1-1";
samsung,pin-function = <2>;
samsung,pin-pud = <2>;
samsung,pin-drv = <0>;
};
i2c1_bus: i2c1-bus {
samsung,pins = "gpd1-2", "gpd1-3";
samsung,pin-function = <2>;
samsung,pin-pud = <2>;
samsung,pin-drv = <0>;
};
i2c2_bus: i2c2-bus {
samsung,pins = "gpd1-4", "gpd1-5";
samsung,pin-function = <2>;
samsung,pin-pud = <2>;
samsung,pin-drv = <0>;
};
pwm0_out: pwm0-out {
samsung,pins = "gpd0-0";
samsung,pin-function = <2>;
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
};
pwm1_out: pwm1-out {
samsung,pins = "gpd0-1";
samsung,pin-function = <2>;
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
};
pwm2_out: pwm2-out {
samsung,pins = "gpd0-2";
samsung,pin-function = <2>;
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
};
pwm3_out: pwm3-out {
samsung,pins = "gpd0-3";
samsung,pin-function = <2>;
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
};
keypad_row0: keypad-row-0 {
samsung,pins = "gph3-0";
samsung,pin-function = <3>;
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
};
keypad_row1: keypad-row-1 {
samsung,pins = "gph3-1";
samsung,pin-function = <3>;
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
};
keypad_row2: keypad-row-2 {
samsung,pins = "gph3-2";
samsung,pin-function = <3>;
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
};
keypad_row3: keypad-row-3 {
samsung,pins = "gph3-3";
samsung,pin-function = <3>;
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
};
keypad_row4: keypad-row-4 {
samsung,pins = "gph3-4";
samsung,pin-function = <3>;
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
};
keypad_row5: keypad-row-5 {
samsung,pins = "gph3-5";
samsung,pin-function = <3>;
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
};
keypad_row6: keypad-row-6 {
samsung,pins = "gph3-6";
samsung,pin-function = <3>;
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
};
keypad_row7: keypad-row-7 {
samsung,pins = "gph3-7";
samsung,pin-function = <3>;
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
};
keypad_col0: keypad-col-0 {
samsung,pins = "gph2-0";
samsung,pin-function = <3>;
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
};
keypad_col1: keypad-col-1 {
samsung,pins = "gph2-1";
samsung,pin-function = <3>;
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
};
keypad_col2: keypad-col-2 {
samsung,pins = "gph2-2";
samsung,pin-function = <3>;
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
};
keypad_col3: keypad-col-3 {
samsung,pins = "gph2-3";
samsung,pin-function = <3>;
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
};
keypad_col4: keypad-col-4 {
samsung,pins = "gph2-4";
samsung,pin-function = <3>;
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
};
keypad_col5: keypad-col-5 {
samsung,pins = "gph2-5";
samsung,pin-function = <3>;
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
};
keypad_col6: keypad-col-6 {
samsung,pins = "gph2-6";
samsung,pin-function = <3>;
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
};
keypad_col7: keypad-col-7 {
samsung,pins = "gph2-7";
samsung,pin-function = <3>;
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
};
sd0_clk: sd0-clk {
samsung,pins = "gpg0-0";
samsung,pin-function = <2>;
samsung,pin-pud = <0>;
samsung,pin-drv = <3>;
};
sd0_cmd: sd0-cmd {
samsung,pins = "gpg0-1";
samsung,pin-function = <2>;
samsung,pin-pud = <0>;
samsung,pin-drv = <3>;
};
sd0_cd: sd0-cd {
samsung,pins = "gpg0-2";
samsung,pin-function = <2>;
samsung,pin-pud = <2>;
samsung,pin-drv = <3>;
};
sd0_bus1: sd0-bus-width1 {
samsung,pins = "gpg0-3";
samsung,pin-function = <2>;
samsung,pin-pud = <2>;
samsung,pin-drv = <3>;
};
sd0_bus4: sd0-bus-width4 {
samsung,pins = "gpg0-3", "gpg0-4", "gpg0-5", "gpg0-6";
samsung,pin-function = <2>;
samsung,pin-pud = <2>;
samsung,pin-drv = <3>;
};
sd0_bus8: sd0-bus-width8 {
samsung,pins = "gpg1-3", "gpg1-4", "gpg1-5", "gpg1-6";
samsung,pin-function = <3>;
samsung,pin-pud = <2>;
samsung,pin-drv = <3>;
};
sd1_clk: sd1-clk {
samsung,pins = "gpg1-0";
samsung,pin-function = <2>;
samsung,pin-pud = <0>;
samsung,pin-drv = <3>;
};
sd1_cmd: sd1-cmd {
samsung,pins = "gpg1-1";
samsung,pin-function = <2>;
samsung,pin-pud = <0>;
samsung,pin-drv = <3>;
};
sd1_cd: sd1-cd {
samsung,pins = "gpg1-2";
samsung,pin-function = <2>;
samsung,pin-pud = <2>;
samsung,pin-drv = <3>;
};
sd1_bus1: sd1-bus-width1 {
samsung,pins = "gpg1-3";
samsung,pin-function = <2>;
samsung,pin-pud = <2>;
samsung,pin-drv = <3>;
};
sd1_bus4: sd1-bus-width4 {
samsung,pins = "gpg1-3", "gpg1-4", "gpg1-5", "gpg1-6";
samsung,pin-function = <2>;
samsung,pin-pud = <2>;
samsung,pin-drv = <3>;
};
sd2_clk: sd2-clk {
samsung,pins = "gpg2-0";
samsung,pin-function = <2>;
samsung,pin-pud = <0>;
samsung,pin-drv = <3>;
};
sd2_cmd: sd2-cmd {
samsung,pins = "gpg2-1";
samsung,pin-function = <2>;
samsung,pin-pud = <0>;
samsung,pin-drv = <3>;
};
sd2_cd: sd2-cd {
samsung,pins = "gpg2-2";
samsung,pin-function = <2>;
samsung,pin-pud = <2>;
samsung,pin-drv = <3>;
};
sd2_bus1: sd2-bus-width1 {
samsung,pins = "gpg2-3";
samsung,pin-function = <2>;
samsung,pin-pud = <2>;
samsung,pin-drv = <3>;
};
sd2_bus4: sd2-bus-width4 {
samsung,pins = "gpg2-3", "gpg2-4", "gpg2-5", "gpg2-6";
samsung,pin-function = <2>;
samsung,pin-pud = <2>;
samsung,pin-drv = <3>;
};
sd2_bus8: sd2-bus-width8 {
samsung,pins = "gpg3-3", "gpg3-4", "gpg3-5", "gpg3-6";
samsung,pin-function = <3>;
samsung,pin-pud = <2>;
samsung,pin-drv = <3>;
};
sd3_clk: sd3-clk {
samsung,pins = "gpg3-0";
samsung,pin-function = <2>;
samsung,pin-pud = <0>;
samsung,pin-drv = <3>;
};
sd3_cmd: sd3-cmd {
samsung,pins = "gpg3-1";
samsung,pin-function = <2>;
samsung,pin-pud = <0>;
samsung,pin-drv = <3>;
};
sd3_cd: sd3-cd {
samsung,pins = "gpg3-2";
samsung,pin-function = <2>;
samsung,pin-pud = <2>;
samsung,pin-drv = <3>;
};
sd3_bus1: sd3-bus-width1 {
samsung,pins = "gpg3-3";
samsung,pin-function = <2>;
samsung,pin-pud = <2>;
samsung,pin-drv = <3>;
};
sd3_bus4: sd3-bus-width4 {
samsung,pins = "gpg3-3", "gpg3-4", "gpg3-5", "gpg3-6";
samsung,pin-function = <2>;
samsung,pin-pud = <2>;
samsung,pin-drv = <3>;
};
eint0: ext-int0 {
samsung,pins = "gph0-0";
samsung,pin-function = <0xf>;
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
};
eint8: ext-int8 {
samsung,pins = "gph1-0";
samsung,pin-function = <0xf>;
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
};
eint15: ext-int15 {
samsung,pins = "gph1-7";
samsung,pin-function = <0xf>;
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
};
eint16: ext-int16 {
samsung,pins = "gph2-0";
samsung,pin-function = <0xf>;
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
};
eint31: ext-int31 {
samsung,pins = "gph3-7";
samsung,pin-function = <0xf>;
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
};
cam_port_a_io: cam-port-a-io {
samsung,pins = "gpe0-0", "gpe0-1", "gpe0-2", "gpe0-3",
"gpe0-4", "gpe0-5", "gpe0-6", "gpe0-7",
"gpe1-0", "gpe1-1", "gpe1-2", "gpe1-4";
samsung,pin-function = <2>;
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
};
cam_port_a_clk_active: cam-port-a-clk-active {
samsung,pins = "gpe1-3";
samsung,pin-function = <2>;
samsung,pin-pud = <0>;
samsung,pin-drv = <3>;
};
cam_port_a_clk_idle: cam-port-a-clk-idle {
samsung,pins = "gpe1-3";
samsung,pin-function = <0>;
samsung,pin-pud = <1>;
samsung,pin-drv = <0>;
};
cam_port_b_io: cam-port-b-io {
samsung,pins = "gpj0-0", "gpj0-1", "gpj0-2", "gpj0-3",
"gpj0-4", "gpj0-5", "gpj0-6", "gpj0-7",
"gpj1-0", "gpj1-1", "gpj1-2", "gpj1-4";
samsung,pin-function = <3>;
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
};
cam_port_b_clk_active: cam-port-b-clk-active {
samsung,pins = "gpj1-3";
samsung,pin-function = <3>;
samsung,pin-pud = <0>;
samsung,pin-drv = <3>;
};
cam_port_b_clk_idle: cam-port-b-clk-idle {
samsung,pins = "gpj1-3";
samsung,pin-function = <0>;
samsung,pin-pud = <1>;
samsung,pin-drv = <0>;
};
lcd_ctrl: lcd-ctrl {
samsung,pins = "gpd0-0", "gpd0-1";
samsung,pin-function = <3>;
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
};
lcd_sync: lcd-sync {
samsung,pins = "gpf0-0", "gpf0-1";
samsung,pin-function = <2>;
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
};
lcd_clk: lcd-clk {
samsung,pins = "gpf0-0", "gpf0-1", "gpf0-2", "gpf0-3";
samsung,pin-function = <2>;
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
};
lcd_data24: lcd-data-width24 {
samsung,pins = "gpf0-4", "gpf0-5", "gpf0-6", "gpf0-7",
"gpf1-0", "gpf1-1", "gpf1-2", "gpf1-3",
"gpf1-4", "gpf1-5", "gpf1-6", "gpf1-7",
"gpf2-0", "gpf2-1", "gpf2-2", "gpf2-3",
"gpf2-4", "gpf2-5", "gpf2-6", "gpf2-7",
"gpf3-0", "gpf3-1", "gpf3-2", "gpf3-3";
samsung,pin-function = <2>;
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
};
};

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arch/arm/boot/dts/s5pv210-smdkc110.dts Normal file
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/*
* Samsung's S5PV210 SoC device tree source
*
* Copyright (c) 2013-2014 Samsung Electronics, Co. Ltd.
*
* Mateusz Krawczuk <m.krawczuk@partner.samsung.com>
* Tomasz Figa <t.figa@samsung.com>
*
* Board device tree source for YIC System SMDC110 board.
*
* NOTE: This file is completely based on original board file for mach-smdkc110
* available in Linux 3.15 and intends to provide equivalent level of hardware
* support. Due to lack of hardware, _no_ testing has been performed.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/dts-v1/;
#include <dt-bindings/input/input.h>
#include "s5pv210.dtsi"
/ {
model = "YIC System SMDKC110 based on S5PC110";
compatible = "yic,smdkc110", "samsung,s5pv210";
chosen {
bootargs = "console=ttySAC0,115200n8 root=/dev/mmcblk0p1 rw rootwait ignore_loglevel earlyprintk";
};
memory {
device_type = "memory";
reg = <0x20000000 0x20000000>;
};
};
&xusbxti {
clock-frequency = <24000000>;
};
&uart0 {
status = "okay";
};
&uart1 {
status = "okay";
};
&uart2 {
status = "okay";
};
&uart3 {
status = "okay";
};
&rtc {
status = "okay";
};
&i2c0 {
status = "okay";
audio-codec@1b {
compatible = "wlf,wm8580";
reg = <0x1b>;
};
eeprom@50 {
compatible = "atmel,24c08";
reg = <0x50>;
};
};
&i2s0 {
status = "okay";
};

238
arch/arm/boot/dts/s5pv210-smdkv210.dts Normal file
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/*
* Samsung's S5PV210 SoC device tree source
*
* Copyright (c) 2013-2014 Samsung Electronics, Co. Ltd.
*
* Mateusz Krawczuk <m.krawczuk@partner.samsung.com>
* Tomasz Figa <t.figa@samsung.com>
*
* Board device tree source for YIC System SMDV210 board.
*
* NOTE: This file is completely based on original board file for mach-smdkv210
* available in Linux 3.15 and intends to provide equivalent level of hardware
* support. Due to lack of hardware, _no_ testing has been performed.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/dts-v1/;
#include <dt-bindings/input/input.h>
#include "s5pv210.dtsi"
/ {
model = "YIC System SMDKV210 based on S5PV210";
compatible = "yic,smdkv210", "samsung,s5pv210";
chosen {
bootargs = "console=ttySAC0,115200n8 root=/dev/mmcblk0p1 rw rootwait ignore_loglevel earlyprintk";
};
memory {
device_type = "memory";
reg = <0x20000000 0x40000000>;
};
ethernet@18000000 {
compatible = "davicom,dm9000";
reg = <0xA8000000 0x2 0xA8000002 0x2>;
interrupt-parent = <&gph1>;
interrupts = <1 4>;
local-mac-address = [00 00 de ad be ef];
davicom,no-eeprom;
};
backlight {
compatible = "pwm-backlight";
pwms = <&pwm 3 5000000 0>;
brightness-levels = <0 4 8 16 32 64 128 255>;
default-brightness-level = <6>;
pinctrl-names = "default";
pinctrl-0 = <&pwm3_out>;
};
};
&xusbxti {
clock-frequency = <24000000>;
};
&keypad {
linux,input-no-autorepeat;
linux,input-wakeup;
samsung,keypad-num-rows = <8>;
samsung,keypad-num-columns = <8>;
pinctrl-names = "default";
pinctrl-0 = <&keypad_row0>, <&keypad_row1>, <&keypad_row2>,
<&keypad_row3>, <&keypad_row4>, <&keypad_row5>,
<&keypad_row6>, <&keypad_row7>,
<&keypad_col0>, <&keypad_col1>, <&keypad_col2>,
<&keypad_col3>, <&keypad_col4>, <&keypad_col5>,
<&keypad_col6>, <&keypad_col7>;
status = "okay";
key_1 {
keypad,row = <0>;
keypad,column = <3>;
linux,code = <KEY_1>;
};
key_2 {
keypad,row = <0>;
keypad,column = <4>;
linux,code = <KEY_2>;
};
key_3 {
keypad,row = <0>;
keypad,column = <5>;
linux,code = <KEY_3>;
};
key_4 {
keypad,row = <0>;
keypad,column = <6>;
linux,code = <KEY_4>;
};
key_5 {
keypad,row = <0
>;
keypad,column = <7>;
linux,code = <KEY_5>;
};
key_6 {
keypad,row = <1>;
keypad,column = <3>;
linux,code = <KEY_A>;
};
key_7 {
keypad,row = <1>;
keypad,column = <4>;
linux,code = <KEY_B>;
};
key_8 {
keypad,row = <1>;
keypad,column = <5>;
linux,code = <KEY_C>;
};
key_9 {
keypad,row = <1>;
keypad,column = <6>;
linux,code = <KEY_D>;
};
key_10 {
keypad,row = <1>;
keypad,column = <7>;
linux,code = <KEY_E>;
};
};
&uart0 {
status = "okay";
};
&uart1 {
status = "okay";
};
&uart2 {
status = "okay";
};
&uart3 {
status = "okay";
};
&rtc {
status = "okay";
};
&sdhci0 {
bus-width = <4>;
pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_bus1 &sd0_bus4>;
pinctrl-names = "default";
status = "okay";
};
&sdhci1 {
bus-width = <4>;
pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_cd &sd1_bus1 &sd1_bus4>;
pinctrl-names = "default";
status = "okay";
};
&sdhci2 {
bus-width = <4>;
pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus1 &sd2_bus4>;
pinctrl-names = "default";
status = "okay";
};
&sdhci3 {
bus-width = <4>;
pinctrl-0 = <&sd3_clk &sd3_cmd &sd3_cd &sd3_bus1 &sd3_bus4>;
pinctrl-names = "default";
status = "okay";
};
&hsotg {
status = "okay";
};
&usbphy {
status = "okay";
};
&fimd {
pinctrl-0 = <&lcd_clk &lcd_data24>;
pinctrl-names = "default";
status = "okay";
display-timings {
native-mode = <&timing0>;
timing0: timing@0 {
/* 800x480@60Hz */
clock-frequency = <24373920>;
hactive = <800>;
vactive = <480>;
hfront-porch = <8>;
hback-porch = <13>;
hsync-len = <3>;
vback-porch = <7>;
vfront-porch = <5>;
vsync-len = <1>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <1>;
pixelclk-active = <1>;
};
};
};
&pwm {
samsung,pwm-outputs = <3>;
};
&i2c0 {
status = "okay";
audio-codec@1b {
compatible = "wlf,wm8580";
reg = <0x1b>;
};
eeprom@50 {
compatible = "atmel,24c08";
reg = <0x50>;
};
};
&i2s0 {
status = "okay";
};

92
arch/arm/boot/dts/s5pv210-torbreck.dts Normal file
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/*
* Samsung's S5PV210 SoC device tree source
*
* Copyright (c) 2013-2014 Samsung Electronics, Co. Ltd.
*
* Mateusz Krawczuk <m.krawczuk@partner.samsung.com>
* Tomasz Figa <t.figa@samsung.com>
*
* Board device tree source for Torbreck board.
*
* NOTE: This file is completely based on original board file for mach-torbreck
* available in Linux 3.15 and intends to provide equivalent level of hardware
* support. Due to lack of hardware, _no_ testing has been performed.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/dts-v1/;
#include <dt-bindings/input/input.h>
#include "s5pv210.dtsi"
/ {
model = "aESOP Torbreck based on S5PV210";
compatible = "aesop,torbreck", "samsung,s5pv210";
chosen {
bootargs = "console=ttySAC0,115200n8 root=/dev/mmcblk0p1 rw rootwait ignore_loglevel earlyprintk";
};
memory {
device_type = "memory";
reg = <0x20000000 0x20000000>;
};
};
&xusbxti {
clock-frequency = <24000000>;
};
&uart0 {
status = "okay";
};
&uart1 {
status = "okay";
};
&uart2 {
status = "okay";
};
&uart3 {
status = "okay";
};
&rtc {
status = "okay";
};
&sdhci0 {
bus-width = <4>;
pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_bus1 &sd0_bus4>;
pinctrl-names = "default";
status = "okay";
};
&sdhci1 {
bus-width = <4>;
pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_cd &sd1_bus1 &sd1_bus4>;
pinctrl-names = "default";
status = "okay";
};
&sdhci2 {
bus-width = <4>;
pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus1 &sd2_bus4>;
pinctrl-names = "default";
status = "okay";
};
&sdhci3 {
bus-width = <4>;
pinctrl-0 = <&sd3_clk &sd3_cmd &sd3_cd &sd3_bus1 &sd3_bus4>;
pinctrl-names = "default";
status = "okay";
};
&i2s0 {
status = "okay";
};

633
arch/arm/boot/dts/s5pv210.dtsi Normal file
View File

@ -0,0 +1,633 @@
/*
* Samsung's S5PV210 SoC device tree source
*
* Copyright (c) 2013-2014 Samsung Electronics, Co. Ltd.
*
* Mateusz Krawczuk <m.krawczuk@partner.samsung.com>
* Tomasz Figa <t.figa@samsung.com>
*
* Samsung's S5PV210 SoC device nodes are listed in this file. S5PV210
* based board files can include this file and provide values for board specfic
* bindings.
*
* Note: This file does not include device nodes for all the controllers in
* S5PV210 SoC. As device tree coverage for S5PV210 increases, additional
* nodes can be added to this file.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include "skeleton.dtsi"
#include <dt-bindings/clock/s5pv210.h>
#include <dt-bindings/clock/s5pv210-audss.h>
/ {
aliases {
csis0 = &csis0;
fimc0 = &fimc0;
fimc1 = &fimc1;
fimc2 = &fimc2;
i2c0 = &i2c0;
i2c1 = &i2c1;
i2c2 = &i2c2;
i2s0 = &i2s0;
i2s1 = &i2s1;
i2s2 = &i2s2;
pinctrl0 = &pinctrl0;
spi0 = &spi0;
spi1 = &spi1;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a8";
reg = <0>;
};
};
soc {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges;
external-clocks {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
xxti: oscillator@0 {
compatible = "fixed-clock";
reg = <0>;
clock-frequency = <0>;
clock-output-names = "xxti";
#clock-cells = <0>;
};
xusbxti: oscillator@1 {
compatible = "fixed-clock";
reg = <1>;
clock-frequency = <0>;
clock-output-names = "xusbxti";
#clock-cells = <0>;
};
};
onenand: onenand@b0000000 {
compatible = "samsung,s5pv210-onenand";
reg = <0xb0600000 0x2000>,
<0xb0000000 0x20000>,
<0xb0040000 0x20000>;
interrupt-parent = <&vic1>;
interrupts = <31>;
clocks = <&clocks CLK_NANDXL>, <&clocks DOUT_FLASH>;
clock-names = "bus", "onenand";
#address-cells = <1>;
#size-cells = <1>;
status = "disabled";
};
chipid@e0000000 {
compatible = "samsung,s5pv210-chipid";
reg = <0xe0000000 0x1000>;
};
clocks: clock-controller@e0100000 {
compatible = "samsung,s5pv210-clock", "simple-bus";
reg = <0xe0100000 0x10000>;
clock-names = "xxti", "xusbxti";
clocks = <&xxti>, <&xusbxti>;
#clock-cells = <1>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
pmu_syscon: syscon@e0108000 {
compatible = "samsung-s5pv210-pmu", "syscon";
reg = <0xe0108000 0x8000>;
};
};
pinctrl0: pinctrl@e0200000 {
compatible = "samsung,s5pv210-pinctrl";
reg = <0xe0200000 0x1000>;
interrupt-parent = <&vic0>;
interrupts = <30>;
wakeup-interrupt-controller {
compatible = "samsung,exynos4210-wakeup-eint";
interrupts = <16>;
interrupt-parent = <&vic0>;
};
};
amba {
#address-cells = <1>;
#size-cells = <1>;
compatible = "arm,amba-bus";
ranges;
pdma0: dma@e0900000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0xe0900000 0x1000>;
interrupt-parent = <&vic0>;
interrupts = <19>;
clocks = <&clocks CLK_PDMA0>;
clock-names = "apb_pclk";
#dma-cells = <1>;
#dma-channels = <8>;
#dma-requests = <32>;
};
pdma1: dma@e0a00000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0xe0a00000 0x1000>;
interrupt-parent = <&vic0>;
interrupts = <20>;
clocks = <&clocks CLK_PDMA1>;
clock-names = "apb_pclk";
#dma-cells = <1>;
#dma-channels = <8>;
#dma-requests = <32>;
};
};
spi0: spi@e1300000 {
compatible = "samsung,s5pv210-spi";
reg = <0xe1300000 0x1000>;
interrupt-parent = <&vic1>;
interrupts = <15>;
dmas = <&pdma0 7>, <&pdma0 6>;
dma-names = "tx", "rx";
clocks = <&clocks SCLK_SPI0>, <&clocks CLK_SPI0>;
clock-names = "spi", "spi_busclk0";
pinctrl-names = "default";
pinctrl-0 = <&spi0_bus>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spi1: spi@e1400000 {
compatible = "samsung,s5pv210-spi";
reg = <0xe1400000 0x1000>;
interrupt-parent = <&vic1>;
interrupts = <16>;
dmas = <&pdma1 7>, <&pdma1 6>;
dma-names = "tx", "rx";
clocks = <&clocks SCLK_SPI1>, <&clocks CLK_SPI1>;
clock-names = "spi", "spi_busclk0";
pinctrl-names = "default";
pinctrl-0 = <&spi1_bus>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
keypad: keypad@e1600000 {
compatible = "samsung,s5pv210-keypad";
reg = <0xe1600000 0x1000>;
interrupt-parent = <&vic2>;
interrupts = <25>;
clocks = <&clocks CLK_KEYIF>;
clock-names = "keypad";
status = "disabled";
};
i2c0: i2c@e1800000 {
compatible = "samsung,s3c2440-i2c";
reg = <0xe1800000 0x1000>;
interrupt-parent = <&vic1>;
interrupts = <14>;
clocks = <&clocks CLK_I2C0>;
clock-names = "i2c";
pinctrl-names = "default";
pinctrl-0 = <&i2c0_bus>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c2: i2c@e1a00000 {
compatible = "samsung,s3c2440-i2c";
reg = <0xe1a00000 0x1000>;
interrupt-parent = <&vic1>;
interrupts = <19>;
clocks = <&clocks CLK_I2C2>;
clock-names = "i2c";
pinctrl-0 = <&i2c2_bus>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
audio-subsystem {
compatible = "samsung,s5pv210-audss", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges;
clk_audss: clock-controller@eee10000 {
compatible = "samsung,s5pv210-audss-clock";
reg = <0xeee10000 0x1000>;
clock-names = "hclk", "xxti",
"fout_epll",
"sclk_audio0";
clocks = <&clocks DOUT_HCLKP>, <&xxti>,
<&clocks FOUT_EPLL>,
<&clocks SCLK_AUDIO0>;
#clock-cells = <1>;
};
i2s0: i2s@eee30000 {
compatible = "samsung,s5pv210-i2s";
reg = <0xeee30000 0x1000>;
interrupt-parent = <&vic2>;
interrupts = <16>;
dma-names = "rx", "tx", "tx-sec";
dmas = <&pdma1 9>, <&pdma1 10>, <&pdma1 11>;
clock-names = "iis",
"i2s_opclk0",
"i2s_opclk1";
clocks = <&clk_audss CLK_I2S>,
<&clk_audss CLK_I2S>,
<&clk_audss CLK_DOUT_AUD_BUS>;
samsung,idma-addr = <0xc0010000>;
pinctrl-names = "default";
pinctrl-0 = <&i2s0_bus>;
#sound-dai-cells = <0>;
status = "disabled";
};
};
i2s1: i2s@e2100000 {
compatible = "samsung,s3c6410-i2s";
reg = <0xe2100000 0x1000>;
interrupt-parent = <&vic2>;
interrupts = <17>;
dma-names = "rx", "tx";
dmas = <&pdma1 12>, <&pdma1 13>;
clock-names = "iis", "i2s_opclk0";
clocks = <&clocks CLK_I2S1>, <&clocks SCLK_AUDIO1>;
pinctrl-names = "default";
pinctrl-0 = <&i2s1_bus>;
#sound-dai-cells = <0>;
status = "disabled";
};
i2s2: i2s@e2a00000 {
compatible = "samsung,s3c6410-i2s";
reg = <0xe2a00000 0x1000>;
interrupt-parent = <&vic2>;
interrupts = <18>;
dma-names = "rx", "tx";
dmas = <&pdma1 14>, <&pdma1 15>;
clock-names = "iis", "i2s_opclk0";
clocks = <&clocks CLK_I2S2>, <&clocks SCLK_AUDIO2>;
pinctrl-names = "default";
pinctrl-0 = <&i2s2_bus>;
#sound-dai-cells = <0>;
status = "disabled";
};
pwm: pwm@e2500000 {
compatible = "samsung,s5pc100-pwm";
reg = <0xe2500000 0x1000>;
interrupt-parent = <&vic0>;
interrupts = <21>, <22>, <23>, <24>, <25>;
clock-names = "timers";
clocks = <&clocks CLK_PWM>;
#pwm-cells = <3>;
};
watchdog: watchdog@e2700000 {
compatible = "samsung,s3c2410-wdt";
reg = <0xe2700000 0x1000>;
interrupt-parent = <&vic0>;
interrupts = <26>;
clock-names = "watchdog";
clocks = <&clocks CLK_WDT>;
};
rtc: rtc@e2800000 {
compatible = "samsung,s3c6410-rtc";
reg = <0xe2800000 0x100>;
interrupt-parent = <&vic0>;
interrupts = <28>, <29>;
clocks = <&clocks CLK_RTC>;
clock-names = "rtc";
status = "disabled";
};
uart0: serial@e2900000 {
compatible = "samsung,s5pv210-uart";
reg = <0xe2900000 0x400>;
interrupt-parent = <&vic1>;
interrupts = <10>;
clock-names = "uart", "clk_uart_baud0",
"clk_uart_baud1";
clocks = <&clocks CLK_UART0>, <&clocks CLK_UART0>,
<&clocks SCLK_UART0>;
status = "disabled";
};
uart1: serial@e2900400 {
compatible = "samsung,s5pv210-uart";
reg = <0xe2900400 0x400>;
interrupt-parent = <&vic1>;
interrupts = <11>;
clock-names = "uart", "clk_uart_baud0",
"clk_uart_baud1";
clocks = <&clocks CLK_UART1>, <&clocks CLK_UART1>,
<&clocks SCLK_UART1>;
status = "disabled";
};
uart2: serial@e2900800 {
compatible = "samsung,s5pv210-uart";
reg = <0xe2900800 0x400>;
interrupt-parent = <&vic1>;
interrupts = <12>;
clock-names = "uart", "clk_uart_baud0",
"clk_uart_baud1";
clocks = <&clocks CLK_UART2>, <&clocks CLK_UART2>,
<&clocks SCLK_UART2>;
status = "disabled";
};
uart3: serial@e2900c00 {
compatible = "samsung,s5pv210-uart";
reg = <0xe2900c00 0x400>;
interrupt-parent = <&vic1>;
interrupts = <13>;
clock-names = "uart", "clk_uart_baud0",
"clk_uart_baud1";
clocks = <&clocks CLK_UART3>, <&clocks CLK_UART3>,
<&clocks SCLK_UART3>;
status = "disabled";
};
sdhci0: sdhci@eb000000 {
compatible = "samsung,s3c6410-sdhci";
reg = <0xeb000000 0x100000>;
interrupt-parent = <&vic1>;
interrupts = <26>;
clock-names = "hsmmc", "mmc_busclk.0", "mmc_busclk.2";
clocks = <&clocks CLK_HSMMC0>, <&clocks CLK_HSMMC0>,
<&clocks SCLK_MMC0>;
status = "disabled";
};
sdhci1: sdhci@eb100000 {
compatible = "samsung,s3c6410-sdhci";
reg = <0xeb100000 0x100000>;
interrupt-parent = <&vic1>;
interrupts = <27>;
clock-names = "hsmmc", "mmc_busclk.0", "mmc_busclk.2";
clocks = <&clocks CLK_HSMMC1>, <&clocks CLK_HSMMC1>,
<&clocks SCLK_MMC1>;
status = "disabled";
};
sdhci2: sdhci@eb200000 {
compatible = "samsung,s3c6410-sdhci";
reg = <0xeb200000 0x100000>;
interrupt-parent = <&vic1>;
interrupts = <28>;
clock-names = "hsmmc", "mmc_busclk.0", "mmc_busclk.2";
clocks = <&clocks CLK_HSMMC2>, <&clocks CLK_HSMMC2>,
<&clocks SCLK_MMC2>;
status = "disabled";
};
sdhci3: sdhci@eb300000 {
compatible = "samsung,s3c6410-sdhci";
reg = <0xeb300000 0x100000>;
interrupt-parent = <&vic3>;
interrupts = <2>;
clock-names = "hsmmc", "mmc_busclk.0", "mmc_busclk.3";
clocks = <&clocks CLK_HSMMC3>, <&clocks CLK_HSMMC3>,
<&clocks SCLK_MMC3>;
status = "disabled";
};
hsotg: hsotg@ec000000 {
compatible = "samsung,s3c6400-hsotg";
reg = <0xec000000 0x20000>;
interrupt-parent = <&vic1>;
interrupts = <24>;
clocks = <&clocks CLK_USB_OTG>;
clock-names = "otg";
phy-names = "usb2-phy";
phys = <&usbphy 0>;
status = "disabled";
};
usbphy: usbphy@ec100000 {
compatible = "samsung,s5pv210-usb2-phy";
reg = <0xec100000 0x100>;
samsung,pmureg-phandle = <&pmu_syscon>;
clocks = <&clocks CLK_USB_OTG>, <&xusbxti>;
clock-names = "phy", "ref";
#phy-cells = <1>;
status = "disabled";
};
ehci: ehci@ec200000 {
compatible = "samsung,exynos4210-ehci";
reg = <0xec200000 0x100>;
interrupts = <23>;
interrupt-parent = <&vic1>;
clocks = <&clocks CLK_USB_HOST>;
clock-names = "usbhost";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
port@0 {
reg = <0>;
phys = <&usbphy 1>;
};
};
ohci: ohci@ec300000 {
compatible = "samsung,exynos4210-ohci";
reg = <0xec300000 0x100>;
interrupts = <23>;
clocks = <&clocks CLK_USB_HOST>;
clock-names = "usbhost";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
port@0 {
reg = <0>;
phys = <&usbphy 1>;
};
};
mfc: codec@f1700000 {
compatible = "samsung,mfc-v5";
reg = <0xf1700000 0x10000>;
interrupt-parent = <&vic2>;
interrupts = <14>;
clocks = <&clocks DOUT_MFC>, <&clocks CLK_MFC>;
clock-names = "sclk_mfc", "mfc";
};
vic0: interrupt-controller@f2000000 {
compatible = "arm,pl192-vic";
interrupt-controller;
reg = <0xf2000000 0x1000>;
#interrupt-cells = <1>;
};
vic1: interrupt-controller@f2100000 {
compatible = "arm,pl192-vic";
interrupt-controller;
reg = <0xf2100000 0x1000>;
#interrupt-cells = <1>;
};
vic2: interrupt-controller@f2200000 {
compatible = "arm,pl192-vic";
interrupt-controller;
reg = <0xf2200000 0x1000>;
#interrupt-cells = <1>;
};
vic3: interrupt-controller@f2300000 {
compatible = "arm,pl192-vic";
interrupt-controller;
reg = <0xf2300000 0x1000>;
#interrupt-cells = <1>;
};
fimd: fimd@f8000000 {
compatible = "samsung,exynos4210-fimd";
interrupt-parent = <&vic2>;
reg = <0xf8000000 0x20000>;
interrupt-names = "fifo", "vsync", "lcd_sys";
interrupts = <0>, <1>, <2>;
clocks = <&clocks SCLK_FIMD>, <&clocks CLK_FIMD>;
clock-names = "sclk_fimd", "fimd";
status = "disabled";
};
g2d: g2d@fa000000 {
compatible = "samsung,s5pv210-g2d";
reg = <0xfa000000 0x1000>;
interrupt-parent = <&vic2>;
interrupts = <9>;
clocks = <&clocks DOUT_G2D>, <&clocks CLK_G2D>;
clock-names = "sclk_fimg2d", "fimg2d";
};
mdma1: mdma@fa200000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0xfa200000 0x1000>;
interrupt-parent = <&vic0>;
interrupts = <18>;
clocks = <&clocks CLK_MDMA>;
clock-names = "apb_pclk";
#dma-cells = <1>;
#dma-channels = <8>;
#dma-requests = <1>;
};
i2c1: i2c@fab00000 {
compatible = "samsung,s3c2440-i2c";
reg = <0xfab00000 0x1000>;
interrupt-parent = <&vic2>;
interrupts = <13>;
clocks = <&clocks CLK_I2C1>;
clock-names = "i2c";
pinctrl-names = "default";
pinctrl-0 = <&i2c1_bus>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
camera: camera {
compatible = "samsung,fimc", "simple-bus";
pinctrl-names = "default";
pinctrl-0 = <>;
clocks = <&clocks SCLK_CAM0>, <&clocks SCLK_CAM1>;
clock-names = "sclk_cam0", "sclk_cam1";
#address-cells = <1>;
#size-cells = <1>;
ranges;
clock_cam: clock-controller {
#clock-cells = <1>;
};
csis0: csis@fa600000 {
compatible = "samsung,s5pv210-csis";
reg = <0xfa600000 0x4000>;
interrupt-parent = <&vic2>;
interrupts = <29>;
clocks = <&clocks CLK_CSIS>,
<&clocks SCLK_CSIS>;
clock-names = "clk_csis",
"sclk_csis";
bus-width = <4>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
fimc0: fimc@fb200000 {
compatible = "samsung,s5pv210-fimc";
reg = <0xfb200000 0x1000>;
interrupts = <5>;
interrupt-parent = <&vic2>;
clocks = <&clocks CLK_FIMC0>,
<&clocks SCLK_FIMC0>;
clock-names = "fimc",
"sclk_fimc";
samsung,pix-limits = <4224 8192 1920 4224>;
samsung,mainscaler-ext;
samsung,cam-if;
};
fimc1: fimc@fb300000 {
compatible = "samsung,s5pv210-fimc";
reg = <0xfb300000 0x1000>;
interrupt-parent = <&vic2>;
interrupts = <6>;
clocks = <&clocks CLK_FIMC1>,
<&clocks SCLK_FIMC1>;
clock-names = "fimc",
"sclk_fimc";
samsung,pix-limits = <4224 8192 1920 4224>;
samsung,mainscaler-ext;
samsung,cam-if;
};
fimc2: fimc@fb400000 {
compatible = "samsung,s5pv210-fimc";
reg = <0xfb400000 0x1000>;
interrupt-parent = <&vic2>;
interrupts = <7>;
clocks = <&clocks CLK_FIMC2>,
<&clocks SCLK_FIMC2>;
clock-names = "fimc",
"sclk_fimc";
samsung,pix-limits = <4224 8192 1920 4224>;
samsung,mainscaler-ext;
samsung,lcd-wb;
};
};
};
};
#include "s5pv210-pinctrl.dtsi"

23
arch/arm/mach-s5pv210/include/mach/debug-macro.S → arch/arm/include/debug/s5pv210.S
View File

@ -1,9 +1,6 @@
/* linux/arch/arm/mach-s5pv210/include/mach/debug-macro.S
*
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
* http://www.samsung.com/
*
* Based on arch/arm/mach-s3c6400/include/mach/debug-macro.S
/*
* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
@ -12,8 +9,9 @@
/* pull in the relevant register and map files. */
#include <linux/serial_s3c.h>
#include <mach/map.h>
#define S3C_ADDR_BASE 0xF6000000
#define S3C_VA_UART S3C_ADDR_BASE + 0x01000000
#define S5PV210_PA_UART 0xe2900000
/* note, for the boot process to work we have to keep the UART
* virtual address aligned to an 1MiB boundary for the L1
@ -22,8 +20,8 @@
*/
.macro addruart, rp, rv, tmp
ldr \rp, = S3C_PA_UART
ldr \rv, = S3C_VA_UART
ldr \rp, =S5PV210_PA_UART
ldr \rv, =S3C_VA_UART
#if CONFIG_DEBUG_S3C_UART != 0
add \rp, \rp, #(0x400 * CONFIG_DEBUG_S3C_UART)
add \rv, \rv, #(0x400 * CONFIG_DEBUG_S3C_UART)
@ -33,9 +31,4 @@
#define fifo_full fifo_full_s5pv210
#define fifo_level fifo_level_s5pv210
/* include the reset of the code which will do the work, we're only
* compiling for a single cpu processor type so the default of s3c2440
* will be fine with us.
*/
#include <debug/samsung.S>

1
arch/arm/mach-exynos/pm.c
View File

@ -28,7 +28,6 @@
#include <asm/suspend.h>
#include <plat/pm-common.h>
#include <plat/pll.h>
#include <plat/regs-srom.h>
#include <mach/map.h>

2
arch/arm/mach-s3c24xx/common.c
View File

@ -49,9 +49,7 @@
#include <plat/cpu.h>
#include <plat/devs.h>
#include <plat/clock.h>
#include <plat/cpu-freq.h>
#include <plat/pll.h>
#include <plat/pwm-core.h>
#include <plat/watchdog-reset.h>

1
arch/arm/mach-s3c24xx/iotiming-s3c2412.c
View File

@ -29,7 +29,6 @@
#include <plat/cpu.h>
#include <plat/cpu-freq-core.h>
#include <plat/clock.h>
#include <mach/s3c2412.h>

5
arch/arm/mach-s3c24xx/mach-h1940.c
View File

@ -60,7 +60,6 @@
#include <plat/cpu.h>
#include <plat/devs.h>
#include <plat/gpio-cfg.h>
#include <plat/pll.h>
#include <plat/pm.h>
#include <plat/samsung-time.h>
@ -73,6 +72,10 @@
#define H1940_LATCH_BIT(x) (1 << ((x) + 16 - S3C_GPIO_END))
#define S3C24XX_PLL_MDIV_SHIFT (12)
#define S3C24XX_PLL_PDIV_SHIFT (4)
#define S3C24XX_PLL_SDIV_SHIFT (0)
static struct map_desc h1940_iodesc[] __initdata = {
[0] = {
.virtual = (unsigned long)H1940_LATCH,

1
arch/arm/mach-s3c24xx/mach-jive.c
View File

@ -48,7 +48,6 @@
#include <linux/mtd/partitions.h>
#include <plat/gpio-cfg.h>
#include <plat/clock.h>
#include <plat/devs.h>
#include <plat/cpu.h>
#include <plat/pm.h>

1
arch/arm/mach-s3c24xx/mach-smdk2413.c
View File

@ -43,7 +43,6 @@
#include <mach/gpio-samsung.h>
#include <mach/fb.h>
#include <plat/clock.h>
#include <plat/devs.h>
#include <plat/cpu.h>
#include <plat/samsung-time.h>

1
arch/arm/mach-s3c24xx/mach-smdk2416.c
View File

@ -44,7 +44,6 @@
#include <linux/platform_data/i2c-s3c2410.h>
#include <plat/gpio-cfg.h>
#include <plat/clock.h>
#include <plat/devs.h>
#include <plat/cpu.h>
#include <linux/platform_data/mtd-nand-s3c2410.h>

1
arch/arm/mach-s3c24xx/mach-smdk2443.c
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@ -38,7 +38,6 @@
#include <mach/fb.h>
#include <linux/platform_data/i2c-s3c2410.h>
#include <plat/clock.h>
#include <plat/devs.h>
#include <plat/cpu.h>
#include <plat/samsung-time.h>

1
arch/arm/mach-s3c24xx/mach-vstms.c
View File

@ -42,7 +42,6 @@
#include <linux/platform_data/i2c-s3c2410.h>
#include <linux/platform_data/mtd-nand-s3c2410.h>
#include <plat/clock.h>
#include <plat/devs.h>
#include <plat/cpu.h>
#include <plat/samsung-time.h>

6
arch/arm/mach-s3c24xx/s3c2410.c
View File

@ -41,8 +41,6 @@
#include <plat/cpu.h>
#include <plat/devs.h>
#include <plat/clock.h>
#include <plat/pll.h>
#include <plat/pm.h>
#include <plat/watchdog-reset.h>
@ -83,10 +81,6 @@ void __init s3c2410_map_io(void)
iotable_init(s3c2410_iodesc, ARRAY_SIZE(s3c2410_iodesc));
}
void __init_or_cpufreq s3c2410_setup_clocks(void)
{
}
struct bus_type s3c2410_subsys = {
.name = "s3c2410-core",
.dev_name = "s3c2410-core",

6
arch/arm/mach-s3c24xx/s3c2412.c
View File

@ -37,12 +37,10 @@
#include <mach/regs-clock.h>
#include <mach/regs-gpio.h>
#include <plat/clock.h>
#include <plat/cpu.h>
#include <plat/cpu-freq.h>
#include <plat/devs.h>
#include <plat/nand-core.h>
#include <plat/pll.h>
#include <plat/pm.h>
#include <plat/regs-spi.h>
@ -171,10 +169,6 @@ void __init s3c2412_map_io(void)
iotable_init(s3c2412_iodesc, ARRAY_SIZE(s3c2412_iodesc));
}
void __init_or_cpufreq s3c2412_setup_clocks(void)
{
}
/* need to register the subsystem before we actually register the device, and
* we also need to ensure that it has been initialised before any of the
* drivers even try to use it (even if not on an s3c2412 based system)

1
arch/arm/mach-s3c24xx/s3c2442.c
View File

@ -43,7 +43,6 @@
#include <mach/regs-clock.h>
#include <plat/clock.h>
#include <plat/cpu.h>
#include <plat/pm.h>

6
arch/arm/mach-s3c24xx/s3c244x.c
View File

@ -38,11 +38,9 @@
#include <mach/regs-clock.h>
#include <mach/regs-gpio.h>
#include <plat/clock.h>
#include <plat/devs.h>
#include <plat/cpu.h>
#include <plat/pm.h>
#include <plat/pll.h>
#include <plat/nand-core.h>
#include <plat/watchdog-reset.h>
@ -78,10 +76,6 @@ void __init s3c244x_map_io(void)
s3c2410_device_dclk.name = "s3c2440-dclk";
}
void __init_or_cpufreq s3c244x_setup_clocks(void)
{
}
/* Since the S3C2442 and S3C2440 share items, put both subsystems here */
struct bus_type s3c2440_subsys = {

1
arch/arm/mach-s3c64xx/mach-anw6410.c
View File

@ -45,7 +45,6 @@
#include <linux/platform_data/i2c-s3c2410.h>
#include <plat/fb.h>
#include <plat/clock.h>
#include <plat/devs.h>
#include <plat/cpu.h>
#include <mach/regs-gpio.h>

1
arch/arm/mach-s3c64xx/mach-crag6410.c
View File

@ -58,7 +58,6 @@
#include <linux/platform_data/spi-s3c64xx.h>
#include <plat/keypad.h>
#include <plat/clock.h>
#include <plat/devs.h>
#include <plat/cpu.h>
#include <plat/adc.h>

1
arch/arm/mach-s3c64xx/mach-hmt.c
View File

@ -39,7 +39,6 @@
#include <plat/fb.h>
#include <linux/platform_data/mtd-nand-s3c2410.h>
#include <plat/clock.h>
#include <plat/devs.h>
#include <plat/cpu.h>
#include <plat/samsung-time.h>

1
arch/arm/mach-s3c64xx/mach-ncp.c
View File

@ -40,7 +40,6 @@
#include <linux/platform_data/i2c-s3c2410.h>
#include <plat/fb.h>
#include <plat/clock.h>
#include <plat/devs.h>
#include <plat/cpu.h>
#include <plat/samsung-time.h>

1
arch/arm/mach-s3c64xx/mach-smartq.c
View File

@ -28,7 +28,6 @@
#include <mach/regs-gpio.h>
#include <mach/gpio-samsung.h>
#include <plat/clock.h>
#include <plat/cpu.h>
#include <plat/devs.h>
#include <linux/platform_data/i2c-s3c2410.h>

1
arch/arm/mach-s3c64xx/mach-smdk6400.c
View File

@ -30,7 +30,6 @@
#include <mach/hardware.h>
#include <mach/map.h>
#include <plat/clock.h>
#include <plat/devs.h>
#include <plat/cpu.h>
#include <linux/platform_data/i2c-s3c2410.h>

1
arch/arm/mach-s3c64xx/mach-smdk6410.c
View File

@ -63,7 +63,6 @@
#include <plat/fb.h>
#include <plat/gpio-cfg.h>
#include <plat/clock.h>
#include <plat/devs.h>
#include <plat/cpu.h>
#include <plat/adc.h>

1
arch/arm/mach-s3c64xx/s3c6400.c
View File

@ -39,7 +39,6 @@
#include <plat/cpu.h>
#include <plat/devs.h>
#include <plat/clock.h>
#include <plat/sdhci.h>
#include <plat/iic-core.h>
#include <plat/onenand-core.h>

1
arch/arm/mach-s3c64xx/s3c6410.c
View File

@ -40,7 +40,6 @@
#include <plat/cpu.h>
#include <plat/devs.h>
#include <plat/clock.h>
#include <plat/sdhci.h>
#include <plat/ata-core.h>
#include <plat/adc-core.h>

197
arch/arm/mach-s5pv210/Kconfig
View File

@ -7,193 +7,28 @@
# Configuration options for the S5PV210/S5PC110
config ARCH_S5PV210
bool "Samsung S5PV210/S5PC110" if ARCH_MULTI_V7
select ARCH_HAS_HOLES_MEMORYMODEL
select ARCH_REQUIRE_GPIOLIB
select ARM_VIC
select CLKSRC_SAMSUNG_PWM
select COMMON_CLK_SAMSUNG
select HAVE_S3C2410_I2C if I2C
select HAVE_S3C2410_WATCHDOG if WATCHDOG
select HAVE_S3C_RTC if RTC_CLASS
select PINCTRL
select PINCTRL_EXYNOS
help
Samsung S5PV210/S5PC110 series based systems
if ARCH_S5PV210
config CPU_S5PV210
bool
def_bool y
select ARM_AMBA
select PL330_DMA if DMADEVICES
select S5P_EXT_INT
select S5P_PM if PM
select S5P_SLEEP if PM
help
Enable S5PV210 CPU support
config S5PV210_SETUP_I2C1
bool
help
Common setup code for i2c bus 1.
config S5PV210_SETUP_I2C2
bool
help
Common setup code for i2c bus 2.
config S5PV210_SETUP_IDE
bool
help
Common setup code for S5PV210 IDE GPIO configurations
config S5PV210_SETUP_FB_24BPP
bool
help
Common setup code for S5PV210 with an 24bpp RGB display helper.
config S5PV210_SETUP_KEYPAD
bool
help
Common setup code for keypad.
config S5PV210_SETUP_SDHCI
bool
select S5PV210_SETUP_SDHCI_GPIO
help
Internal helper functions for S5PV210 based SDHCI systems
config S5PV210_SETUP_SDHCI_GPIO
bool
help
Common setup code for SDHCI gpio.
config S5PV210_SETUP_FIMC
bool
help
Common setup code for the camera interfaces.
config S5PV210_SETUP_SPI
bool
help
Common setup code for SPI GPIO configurations.
config S5PV210_SETUP_USB_PHY
bool
help
Common setup code for USB PHY controller
menu "S5PC110 Machines"
config MACH_AQUILA
bool "Aquila"
select CPU_S5PV210
select S3C_DEV_FB
select S3C_DEV_HSMMC
select S3C_DEV_HSMMC1
select S3C_DEV_HSMMC2
select S5PV210_SETUP_FB_24BPP
select S5PV210_SETUP_SDHCI
select S5PV210_SETUP_USB_PHY
select S5P_DEV_FIMC0
select S5P_DEV_FIMC1
select S5P_DEV_FIMC2
select S5P_DEV_ONENAND
help
Machine support for the Samsung Aquila target based on S5PC110 SoC
config MACH_GONI
bool "GONI"
select CPU_S5PV210
select S3C_DEV_FB
select S3C_DEV_HSMMC
select S3C_DEV_HSMMC1
select S3C_DEV_HSMMC2
select S3C_DEV_I2C1
select S3C_DEV_I2C2
select S3C_DEV_USB_HSOTG
select S5PV210_SETUP_FB_24BPP
select S5PV210_SETUP_FIMC
select S5PV210_SETUP_I2C1
select S5PV210_SETUP_I2C2
select S5PV210_SETUP_KEYPAD
select S5PV210_SETUP_SDHCI
select S5PV210_SETUP_USB_PHY
select S5P_DEV_FIMC0
select S5P_DEV_FIMC1
select S5P_DEV_FIMC2
select S5P_DEV_MFC
select S5P_DEV_ONENAND
select S5P_DEV_TV
select S5P_GPIO_INT
select SAMSUNG_DEV_KEYPAD
help
Machine support for Samsung GONI board
S5PC110(MCP) is one of package option of S5PV210
config MACH_SMDKC110
bool "SMDKC110"
select CPU_S5PV210
select S3C_DEV_I2C1
select S3C_DEV_I2C2
select S3C_DEV_RTC
select S3C_DEV_WDT
select S5PV210_SETUP_I2C1
select S5PV210_SETUP_I2C2
select S5PV210_SETUP_IDE
select S5P_DEV_FIMC0
select S5P_DEV_FIMC1
select S5P_DEV_FIMC2
select S5P_DEV_MFC
select SAMSUNG_DEV_IDE
help
Machine support for Samsung SMDKC110
S5PC110(MCP) is one of package option of S5PV210
endmenu
menu "S5PV210 Machines"
config MACH_SMDKV210
bool "SMDKV210"
select CPU_S5PV210
select S3C_DEV_FB
select S3C_DEV_HSMMC
select S3C_DEV_HSMMC1
select S3C_DEV_HSMMC2
select S3C_DEV_HSMMC3
select S3C_DEV_I2C1
select S3C_DEV_I2C2
select S3C_DEV_RTC
select S3C_DEV_USB_HSOTG
select S3C_DEV_WDT
select S5PV210_SETUP_FB_24BPP
select S5PV210_SETUP_I2C1
select S5PV210_SETUP_I2C2
select S5PV210_SETUP_IDE
select S5PV210_SETUP_KEYPAD
select S5PV210_SETUP_SDHCI
select S5PV210_SETUP_USB_PHY
select S5P_DEV_FIMC0
select S5P_DEV_FIMC1
select S5P_DEV_FIMC2
select S5P_DEV_JPEG
select S5P_DEV_MFC
select SAMSUNG_DEV_ADC
select SAMSUNG_DEV_BACKLIGHT
select SAMSUNG_DEV_IDE
select SAMSUNG_DEV_KEYPAD
select SAMSUNG_DEV_PWM
select SAMSUNG_DEV_TS
help
Machine support for Samsung SMDKV210
config MACH_TORBRECK
bool "Torbreck"
select ARCH_SPARSEMEM_ENABLE
select CPU_S5PV210
select S3C_DEV_HSMMC
select S3C_DEV_HSMMC1
select S3C_DEV_HSMMC2
select S3C_DEV_HSMMC3
select S3C_DEV_I2C1
select S3C_DEV_I2C2
select S3C_DEV_RTC
select S3C_DEV_WDT
select S5PV210_SETUP_I2C1
select S5PV210_SETUP_I2C2
select S5PV210_SETUP_SDHCI
select SAMSUNG_DEV_IDE
help
Machine support for aESOP Torbreck
endmenu
endif

29
arch/arm/mach-s5pv210/Makefile
View File

@ -5,6 +5,8 @@
#
# Licensed under GPLv2
ccflags-$(CONFIG_ARCH_MULTIPLATFORM) += -I$(srctree)/$(src)/include -I$(srctree)/arch/arm/plat-samsung/include
obj-y :=
obj-m :=
obj-n :=
@ -12,31 +14,8 @@ obj- :=
# Core
obj-y += common.o clock.o
obj-$(CONFIG_PM) += pm.o
obj-y += dma.o
obj-$(CONFIG_PM_SLEEP) += pm.o sleep.o
# machine support
obj-$(CONFIG_MACH_AQUILA) += mach-aquila.o
obj-$(CONFIG_MACH_GONI) += mach-goni.o
obj-$(CONFIG_MACH_SMDKC110) += mach-smdkc110.o
obj-$(CONFIG_MACH_SMDKV210) += mach-smdkv210.o
obj-$(CONFIG_MACH_TORBRECK) += mach-torbreck.o
# device support
obj-y += dev-audio.o
obj-y += setup-i2c0.o
obj-$(CONFIG_S5PV210_SETUP_FB_24BPP) += setup-fb-24bpp.o
obj-$(CONFIG_S5PV210_SETUP_FIMC) += setup-fimc.o
obj-$(CONFIG_S5PV210_SETUP_I2C1) += setup-i2c1.o
obj-$(CONFIG_S5PV210_SETUP_I2C2) += setup-i2c2.o
obj-$(CONFIG_S5PV210_SETUP_IDE) += setup-ide.o
obj-$(CONFIG_S5PV210_SETUP_KEYPAD) += setup-keypad.o
obj-$(CONFIG_S5PV210_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o
obj-$(CONFIG_S5PV210_SETUP_SPI) += setup-spi.o
obj-$(CONFIG_S5PV210_SETUP_USB_PHY) += setup-usb-phy.o
obj-y += s5pv210.o

2
arch/arm/mach-s5pv210/Makefile.boot
View File

@ -1,2 +0,0 @@
zreladdr-y += 0x20008000
params_phys-y := 0x20000100

1365
arch/arm/mach-s5pv210/clock.c
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File diff suppressed because it is too large Load Diff

279
arch/arm/mach-s5pv210/common.c
View File

@ -1,279 +0,0 @@
/*
* Copyright (c) 2009-2011 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* Common Codes for S5PV210
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/interrupt.h>
#include <linux/list.h>
#include <linux/timer.h>
#include <linux/init.h>
#include <linux/module.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/device.h>
#include <clocksource/samsung_pwm.h>
#include <linux/platform_device.h>
#include <linux/sched.h>
#include <linux/dma-mapping.h>
#include <linux/serial_core.h>
#include <linux/serial_s3c.h>
#include <asm/proc-fns.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/irq.h>
#include <mach/map.h>
#include <mach/regs-clock.h>
#include <plat/cpu.h>
#include <plat/clock.h>
#include <plat/devs.h>
#include <plat/sdhci.h>
#include <plat/adc-core.h>
#include <plat/ata-core.h>
#include <plat/fb-core.h>
#include <plat/fimc-core.h>
#include <plat/iic-core.h>
#include <plat/keypad-core.h>
#include <plat/pwm-core.h>
#include <plat/tv-core.h>
#include <plat/spi-core.h>
#include "common.h"
static const char name_s5pv210[] = "S5PV210/S5PC110";
static struct cpu_table cpu_ids[] __initdata = {
{
.idcode = S5PV210_CPU_ID,
.idmask = S5PV210_CPU_MASK,
.map_io = s5pv210_map_io,
.init_clocks = s5pv210_init_clocks,
.init_uarts = s5pv210_init_uarts,
.init = s5pv210_init,
.name = name_s5pv210,
},
};
/* Initial IO mappings */
static struct map_desc s5pv210_iodesc[] __initdata = {
{
.virtual = (unsigned long)S5P_VA_CHIPID,
.pfn = __phys_to_pfn(S5PV210_PA_CHIPID),
.length = SZ_4K,
.type = MT_DEVICE,
}, {
.virtual = (unsigned long)S3C_VA_SYS,
.pfn = __phys_to_pfn(S5PV210_PA_SYSCON),
.length = SZ_64K,
.type = MT_DEVICE,
}, {
.virtual = (unsigned long)S3C_VA_TIMER,
.pfn = __phys_to_pfn(S5PV210_PA_TIMER),
.length = SZ_16K,
.type = MT_DEVICE,
}, {
.virtual = (unsigned long)S3C_VA_WATCHDOG,
.pfn = __phys_to_pfn(S5PV210_PA_WATCHDOG),
.length = SZ_4K,
.type = MT_DEVICE,
}, {
.virtual = (unsigned long)S5P_VA_SROMC,
.pfn = __phys_to_pfn(S5PV210_PA_SROMC),
.length = SZ_4K,
.type = MT_DEVICE,
}, {
.virtual = (unsigned long)S5P_VA_SYSTIMER,
.pfn = __phys_to_pfn(S5PV210_PA_SYSTIMER),
.length = SZ_4K,
.type = MT_DEVICE,
}, {
.virtual = (unsigned long)S5P_VA_GPIO,
.pfn = __phys_to_pfn(S5PV210_PA_GPIO),
.length = SZ_4K,
.type = MT_DEVICE,
}, {
.virtual = (unsigned long)VA_VIC0,
.pfn = __phys_to_pfn(S5PV210_PA_VIC0),
.length = SZ_16K,
.type = MT_DEVICE,
}, {
.virtual = (unsigned long)VA_VIC1,
.pfn = __phys_to_pfn(S5PV210_PA_VIC1),
.length = SZ_16K,
.type = MT_DEVICE,
}, {
.virtual = (unsigned long)VA_VIC2,
.pfn = __phys_to_pfn(S5PV210_PA_VIC2),
.length = SZ_16K,
.type = MT_DEVICE,
}, {
.virtual = (unsigned long)VA_VIC3,
.pfn = __phys_to_pfn(S5PV210_PA_VIC3),
.length = SZ_16K,
.type = MT_DEVICE,
}, {
.virtual = (unsigned long)S3C_VA_UART,
.pfn = __phys_to_pfn(S3C_PA_UART),
.length = SZ_512K,
.type = MT_DEVICE,
}, {
.virtual = (unsigned long)S5P_VA_DMC0,
.pfn = __phys_to_pfn(S5PV210_PA_DMC0),
.length = SZ_4K,
.type = MT_DEVICE,
}, {
.virtual = (unsigned long)S5P_VA_DMC1,
.pfn = __phys_to_pfn(S5PV210_PA_DMC1),
.length = SZ_4K,
.type = MT_DEVICE,
}, {
.virtual = (unsigned long)S3C_VA_USB_HSPHY,
.pfn =__phys_to_pfn(S5PV210_PA_HSPHY),
.length = SZ_4K,
.type = MT_DEVICE,
}
};
void s5pv210_restart(enum reboot_mode mode, const char *cmd)
{
__raw_writel(0x1, S5P_SWRESET);
}
static struct samsung_pwm_variant s5pv210_pwm_variant = {
.bits = 32,
.div_base = 0,
.has_tint_cstat = true,
.tclk_mask = (1 << 5),
};
void __init samsung_set_timer_source(unsigned int event, unsigned int source)
{
s5pv210_pwm_variant.output_mask = BIT(SAMSUNG_PWM_NUM) - 1;
s5pv210_pwm_variant.output_mask &= ~(BIT(event) | BIT(source));
}
void __init samsung_timer_init(void)
{
unsigned int timer_irqs[SAMSUNG_PWM_NUM] = {
IRQ_TIMER0_VIC, IRQ_TIMER1_VIC, IRQ_TIMER2_VIC,
IRQ_TIMER3_VIC, IRQ_TIMER4_VIC,
};
samsung_pwm_clocksource_init(S3C_VA_TIMER,
timer_irqs, &s5pv210_pwm_variant);
}
/*
* s5pv210_map_io
*
* register the standard cpu IO areas
*/
void __init s5pv210_init_io(struct map_desc *mach_desc, int size)
{
/* initialize the io descriptors we need for initialization */
iotable_init(s5pv210_iodesc, ARRAY_SIZE(s5pv210_iodesc));
if (mach_desc)
iotable_init(mach_desc, size);
/* detect cpu id and rev. */
s5p_init_cpu(S5P_VA_CHIPID);
s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
samsung_pwm_set_platdata(&s5pv210_pwm_variant);
}
void __init s5pv210_map_io(void)
{
/* initialise device information early */
s5pv210_default_sdhci0();
s5pv210_default_sdhci1();
s5pv210_default_sdhci2();
s5pv210_default_sdhci3();
s3c_adc_setname("samsung-adc-v3");
s3c_cfcon_setname("s5pv210-pata");
s3c_fimc_setname(0, "s5pv210-fimc");
s3c_fimc_setname(1, "s5pv210-fimc");
s3c_fimc_setname(2, "s5pv210-fimc");
/* the i2c devices are directly compatible with s3c2440 */
s3c_i2c0_setname("s3c2440-i2c");
s3c_i2c1_setname("s3c2440-i2c");
s3c_i2c2_setname("s3c2440-i2c");
s3c_fb_setname("s5pv210-fb");
/* Use s5pv210-keypad instead of samsung-keypad */
samsung_keypad_setname("s5pv210-keypad");
/* setup TV devices */
s5p_hdmi_setname("s5pv210-hdmi");
s3c64xx_spi_setname("s5pv210-spi");
}
void __init s5pv210_init_clocks(int xtal)
{
printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
s3c24xx_register_baseclocks(xtal);
s5p_register_clocks(xtal);
s5pv210_register_clocks();
s5pv210_setup_clocks();
}
void __init s5pv210_init_irq(void)
{
u32 vic[4]; /* S5PV210 supports 4 VIC */
/* All the VICs are fully populated. */
vic[0] = ~0;
vic[1] = ~0;
vic[2] = ~0;
vic[3] = ~0;
s5p_init_irq(vic, ARRAY_SIZE(vic));
}
struct bus_type s5pv210_subsys = {
.name = "s5pv210-core",
.dev_name = "s5pv210-core",
};
static struct device s5pv210_dev = {
.bus = &s5pv210_subsys,
};
static int __init s5pv210_core_init(void)
{
return subsys_system_register(&s5pv210_subsys, NULL);
}
core_initcall(s5pv210_core_init);
int __init s5pv210_init(void)
{
printk(KERN_INFO "S5PV210: Initializing architecture\n");
return device_register(&s5pv210_dev);
}
/* uart registration process */
void __init s5pv210_init_uarts(struct s3c2410_uartcfg *cfg, int no)
{
s3c24xx_init_uartdevs("s5pv210-uart", s5p_uart_resources, cfg, no);
}

21
arch/arm/mach-s5pv210/common.h
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@ -12,19 +12,12 @@
#ifndef __ARCH_ARM_MACH_S5PV210_COMMON_H
#define __ARCH_ARM_MACH_S5PV210_COMMON_H
#include <linux/reboot.h>
void s5pv210_init_io(struct map_desc *mach_desc, int size);
void s5pv210_init_irq(void);
void s5pv210_register_clocks(void);
void s5pv210_setup_clocks(void);
void s5pv210_restart(enum reboot_mode mode, const char *cmd);
extern int s5pv210_init(void);
extern void s5pv210_map_io(void);
extern void s5pv210_init_clocks(int xtal);
extern void s5pv210_init_uarts(struct s3c2410_uartcfg *cfg, int no);
#ifdef CONFIG_PM_SLEEP
u32 exynos_get_eint_wake_mask(void);
void s5pv210_cpu_resume(void);
void s5pv210_pm_init(void);
#else
static inline void s5pv210_pm_init(void) {}
#endif
#endif /* __ARCH_ARM_MACH_S5PV210_COMMON_H */

246
arch/arm/mach-s5pv210/dev-audio.c
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@ -1,246 +0,0 @@
/* linux/arch/arm/mach-s5pv210/dev-audio.c
*
* Copyright (c) 2010 Samsung Electronics Co. Ltd
* Jaswinder Singh <jassi.brar@samsung.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/platform_device.h>
#include <linux/dma-mapping.h>
#include <linux/gpio.h>
#include <plat/gpio-cfg.h>
#include <linux/platform_data/asoc-s3c.h>
#include <mach/map.h>
#include <mach/dma.h>
#include <mach/irqs.h>
#define S5PV210_AUDSS_INT_MEM (0xC0000000)
static int s5pv210_cfg_i2s(struct platform_device *pdev)
{
/* configure GPIO for i2s port */
switch (pdev->id) {
case 0:
s3c_gpio_cfgpin_range(S5PV210_GPI(0), 7, S3C_GPIO_SFN(2));
break;
case 1:
s3c_gpio_cfgpin_range(S5PV210_GPC0(0), 5, S3C_GPIO_SFN(2));
break;
case 2:
s3c_gpio_cfgpin_range(S5PV210_GPC1(0), 5, S3C_GPIO_SFN(4));
break;
default:
printk(KERN_ERR "Invalid Device %d\n", pdev->id);
return -EINVAL;
}
return 0;
}
static struct s3c_audio_pdata i2sv5_pdata = {
.cfg_gpio = s5pv210_cfg_i2s,
.type = {
.i2s = {
.quirks = QUIRK_PRI_6CHAN | QUIRK_SEC_DAI
| QUIRK_NEED_RSTCLR,
.idma_addr = S5PV210_AUDSS_INT_MEM,
},
},
};
static struct resource s5pv210_iis0_resource[] = {
[0] = DEFINE_RES_MEM(S5PV210_PA_IIS0, SZ_256),
[1] = DEFINE_RES_DMA(DMACH_I2S0_TX),
[2] = DEFINE_RES_DMA(DMACH_I2S0_RX),
[3] = DEFINE_RES_DMA(DMACH_I2S0S_TX),
};
struct platform_device s5pv210_device_iis0 = {
.name = "samsung-i2s",
.id = 0,
.num_resources = ARRAY_SIZE(s5pv210_iis0_resource),
.resource = s5pv210_iis0_resource,
.dev = {
.platform_data = &i2sv5_pdata,
},
};
static struct s3c_audio_pdata i2sv3_pdata = {
.cfg_gpio = s5pv210_cfg_i2s,
};
static struct resource s5pv210_iis1_resource[] = {
[0] = DEFINE_RES_MEM(S5PV210_PA_IIS1, SZ_256),
[1] = DEFINE_RES_DMA(DMACH_I2S1_TX),
[2] = DEFINE_RES_DMA(DMACH_I2S1_RX),
};
struct platform_device s5pv210_device_iis1 = {
.name = "samsung-i2s",
.id = 1,
.num_resources = ARRAY_SIZE(s5pv210_iis1_resource),
.resource = s5pv210_iis1_resource,
.dev = {
.platform_data = &i2sv3_pdata,
},
};
static struct resource s5pv210_iis2_resource[] = {
[0] = DEFINE_RES_MEM(S5PV210_PA_IIS2, SZ_256),
[1] = DEFINE_RES_DMA(DMACH_I2S2_TX),
[2] = DEFINE_RES_DMA(DMACH_I2S2_RX),
};
struct platform_device s5pv210_device_iis2 = {
.name = "samsung-i2s",
.id = 2,
.num_resources = ARRAY_SIZE(s5pv210_iis2_resource),
.resource = s5pv210_iis2_resource,
.dev = {
.platform_data = &i2sv3_pdata,
},
};
/* PCM Controller platform_devices */
static int s5pv210_pcm_cfg_gpio(struct platform_device *pdev)
{
switch (pdev->id) {
case 0:
s3c_gpio_cfgpin_range(S5PV210_GPI(0), 5, S3C_GPIO_SFN(3));
break;
case 1:
s3c_gpio_cfgpin_range(S5PV210_GPC0(0), 5, S3C_GPIO_SFN(3));
break;
case 2:
s3c_gpio_cfgpin_range(S5PV210_GPC1(0), 5, S3C_GPIO_SFN(2));
break;
default:
printk(KERN_DEBUG "Invalid PCM Controller number!");
return -EINVAL;
}
return 0;
}
static struct s3c_audio_pdata s3c_pcm_pdata = {
.cfg_gpio = s5pv210_pcm_cfg_gpio,
};
static struct resource s5pv210_pcm0_resource[] = {
[0] = DEFINE_RES_MEM(S5PV210_PA_PCM0, SZ_256),
[1] = DEFINE_RES_DMA(DMACH_PCM0_TX),
[2] = DEFINE_RES_DMA(DMACH_PCM0_RX),
};
struct platform_device s5pv210_device_pcm0 = {
.name = "samsung-pcm",
.id = 0,
.num_resources = ARRAY_SIZE(s5pv210_pcm0_resource),
.resource = s5pv210_pcm0_resource,
.dev = {
.platform_data = &s3c_pcm_pdata,
},
};
static struct resource s5pv210_pcm1_resource[] = {
[0] = DEFINE_RES_MEM(S5PV210_PA_PCM1, SZ_256),
[1] = DEFINE_RES_DMA(DMACH_PCM1_TX),
[2] = DEFINE_RES_DMA(DMACH_PCM1_RX),
};
struct platform_device s5pv210_device_pcm1 = {
.name = "samsung-pcm",
.id = 1,
.num_resources = ARRAY_SIZE(s5pv210_pcm1_resource),
.resource = s5pv210_pcm1_resource,
.dev = {
.platform_data = &s3c_pcm_pdata,
},
};
static struct resource s5pv210_pcm2_resource[] = {
[0] = DEFINE_RES_MEM(S5PV210_PA_PCM2, SZ_256),
[1] = DEFINE_RES_DMA(DMACH_PCM2_TX),
[2] = DEFINE_RES_DMA(DMACH_PCM2_RX),
};
struct platform_device s5pv210_device_pcm2 = {
.name = "samsung-pcm",
.id = 2,
.num_resources = ARRAY_SIZE(s5pv210_pcm2_resource),
.resource = s5pv210_pcm2_resource,
.dev = {
.platform_data = &s3c_pcm_pdata,
},
};
/* AC97 Controller platform devices */
static int s5pv210_ac97_cfg_gpio(struct platform_device *pdev)
{
return s3c_gpio_cfgpin_range(S5PV210_GPC0(0), 5, S3C_GPIO_SFN(4));
}
static struct resource s5pv210_ac97_resource[] = {
[0] = DEFINE_RES_MEM(S5PV210_PA_AC97, SZ_256),
[1] = DEFINE_RES_DMA(DMACH_AC97_PCMOUT),
[2] = DEFINE_RES_DMA(DMACH_AC97_PCMIN),
[3] = DEFINE_RES_DMA(DMACH_AC97_MICIN),
[4] = DEFINE_RES_IRQ(IRQ_AC97),
};
static struct s3c_audio_pdata s3c_ac97_pdata = {
.cfg_gpio = s5pv210_ac97_cfg_gpio,
};
static u64 s5pv210_ac97_dmamask = DMA_BIT_MASK(32);
struct platform_device s5pv210_device_ac97 = {
.name = "samsung-ac97",
.id = -1,
.num_resources = ARRAY_SIZE(s5pv210_ac97_resource),
.resource = s5pv210_ac97_resource,
.dev = {
.platform_data = &s3c_ac97_pdata,
.dma_mask = &s5pv210_ac97_dmamask,
.coherent_dma_mask = DMA_BIT_MASK(32),
},
};
/* S/PDIF Controller platform_device */
static int s5pv210_spdif_cfg_gpio(struct platform_device *pdev)
{
s3c_gpio_cfgpin_range(S5PV210_GPC1(0), 2, S3C_GPIO_SFN(3));
return 0;
}
static struct resource s5pv210_spdif_resource[] = {
[0] = DEFINE_RES_MEM(S5PV210_PA_SPDIF, SZ_256),
[1] = DEFINE_RES_DMA(DMACH_SPDIF),
};
static struct s3c_audio_pdata samsung_spdif_pdata = {
.cfg_gpio = s5pv210_spdif_cfg_gpio,
};
static u64 s5pv210_spdif_dmamask = DMA_BIT_MASK(32);
struct platform_device s5pv210_device_spdif = {
.name = "samsung-spdif",
.id = -1,
.num_resources = ARRAY_SIZE(s5pv210_spdif_resource),
.resource = s5pv210_spdif_resource,
.dev = {
.platform_data = &samsung_spdif_pdata,
.dma_mask = &s5pv210_spdif_dmamask,
.coherent_dma_mask = DMA_BIT_MASK(32),
},
};

130
arch/arm/mach-s5pv210/dma.c
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@ -1,130 +0,0 @@
/* linux/arch/arm/mach-s5pv210/dma.c
*
* Copyright (c) 2011 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* Copyright (C) 2010 Samsung Electronics Co. Ltd.
* Jaswinder Singh <jassi.brar@samsung.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#include <linux/dma-mapping.h>
#include <linux/amba/bus.h>
#include <linux/amba/pl330.h>
#include <asm/irq.h>
#include <plat/devs.h>
#include <plat/irqs.h>
#include <mach/map.h>
#include <mach/irqs.h>
#include <mach/dma.h>
static u8 pdma0_peri[] = {
DMACH_UART0_RX,
DMACH_UART0_TX,
DMACH_UART1_RX,
DMACH_UART1_TX,
DMACH_UART2_RX,
DMACH_UART2_TX,
DMACH_UART3_RX,
DMACH_UART3_TX,
DMACH_MAX,
DMACH_I2S0_RX,
DMACH_I2S0_TX,
DMACH_I2S0S_TX,
DMACH_I2S1_RX,
DMACH_I2S1_TX,
DMACH_MAX,
DMACH_MAX,
DMACH_SPI0_RX,
DMACH_SPI0_TX,
DMACH_SPI1_RX,
DMACH_SPI1_TX,
DMACH_MAX,
DMACH_MAX,
DMACH_AC97_MICIN,
DMACH_AC97_PCMIN,
DMACH_AC97_PCMOUT,
DMACH_MAX,
DMACH_PWM,
DMACH_SPDIF,
};
static struct dma_pl330_platdata s5pv210_pdma0_pdata = {
.nr_valid_peri = ARRAY_SIZE(pdma0_peri),
.peri_id = pdma0_peri,
};
static AMBA_AHB_DEVICE(s5pv210_pdma0, "dma-pl330.0", 0x00041330,
S5PV210_PA_PDMA0, {IRQ_PDMA0}, &s5pv210_pdma0_pdata);
static u8 pdma1_peri[] = {
DMACH_UART0_RX,
DMACH_UART0_TX,
DMACH_UART1_RX,
DMACH_UART1_TX,
DMACH_UART2_RX,
DMACH_UART2_TX,
DMACH_UART3_RX,
DMACH_UART3_TX,
DMACH_MAX,
DMACH_I2S0_RX,
DMACH_I2S0_TX,
DMACH_I2S0S_TX,
DMACH_I2S1_RX,
DMACH_I2S1_TX,
DMACH_I2S2_RX,
DMACH_I2S2_TX,
DMACH_SPI0_RX,
DMACH_SPI0_TX,
DMACH_SPI1_RX,
DMACH_SPI1_TX,
DMACH_MAX,
DMACH_MAX,
DMACH_PCM0_RX,
DMACH_PCM0_TX,
DMACH_PCM1_RX,
DMACH_PCM1_TX,
DMACH_MSM_REQ0,
DMACH_MSM_REQ1,
DMACH_MSM_REQ2,
DMACH_MSM_REQ3,
DMACH_PCM2_RX,
DMACH_PCM2_TX,
};
static struct dma_pl330_platdata s5pv210_pdma1_pdata = {
.nr_valid_peri = ARRAY_SIZE(pdma1_peri),
.peri_id = pdma1_peri,
};
static AMBA_AHB_DEVICE(s5pv210_pdma1, "dma-pl330.1", 0x00041330,
S5PV210_PA_PDMA1, {IRQ_PDMA1}, &s5pv210_pdma1_pdata);
static int __init s5pv210_dma_init(void)
{
dma_cap_set(DMA_SLAVE, s5pv210_pdma0_pdata.cap_mask);
dma_cap_set(DMA_CYCLIC, s5pv210_pdma0_pdata.cap_mask);
amba_device_register(&s5pv210_pdma0_device, &iomem_resource);
dma_cap_set(DMA_SLAVE, s5pv210_pdma1_pdata.cap_mask);
dma_cap_set(DMA_CYCLIC, s5pv210_pdma1_pdata.cap_mask);
amba_device_register(&s5pv210_pdma1_device, &iomem_resource);
return 0;
}
arch_initcall(s5pv210_dma_init);

26
arch/arm/mach-s5pv210/include/mach/dma.h
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@ -1,26 +0,0 @@
/*
* Copyright (C) 2010 Samsung Electronics Co. Ltd.
* Jaswinder Singh <jassi.brar@samsung.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#ifndef __MACH_DMA_H
#define __MACH_DMA_H
/* This platform uses the common DMA API driver for PL330 */
#include <plat/dma-pl330.h>
#endif /* __MACH_DMA_H */

140
arch/arm/mach-s5pv210/include/mach/gpio.h
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@ -1,140 +0,0 @@
/* linux/arch/arm/mach-s5pv210/include/mach/gpio.h
*
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
* http://www.samsung.com/
*
* S5PV210 - GPIO lib support
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_GPIO_H
#define __ASM_ARCH_GPIO_H __FILE__
/* Practically, GPIO banks up to MP03 are the configurable gpio banks */
/* GPIO bank sizes */
#define S5PV210_GPIO_A0_NR (8)
#define S5PV210_GPIO_A1_NR (4)
#define S5PV210_GPIO_B_NR (8)
#define S5PV210_GPIO_C0_NR (5)
#define S5PV210_GPIO_C1_NR (5)
#define S5PV210_GPIO_D0_NR (4)
#define S5PV210_GPIO_D1_NR (6)
#define S5PV210_GPIO_E0_NR (8)
#define S5PV210_GPIO_E1_NR (5)
#define S5PV210_GPIO_F0_NR (8)
#define S5PV210_GPIO_F1_NR (8)
#define S5PV210_GPIO_F2_NR (8)
#define S5PV210_GPIO_F3_NR (6)
#define S5PV210_GPIO_G0_NR (7)
#define S5PV210_GPIO_G1_NR (7)
#define S5PV210_GPIO_G2_NR (7)
#define S5PV210_GPIO_G3_NR (7)
#define S5PV210_GPIO_H0_NR (8)
#define S5PV210_GPIO_H1_NR (8)
#define S5PV210_GPIO_H2_NR (8)
#define S5PV210_GPIO_H3_NR (8)
#define S5PV210_GPIO_I_NR (7)
#define S5PV210_GPIO_J0_NR (8)
#define S5PV210_GPIO_J1_NR (6)
#define S5PV210_GPIO_J2_NR (8)
#define S5PV210_GPIO_J3_NR (8)
#define S5PV210_GPIO_J4_NR (5)
#define S5PV210_GPIO_MP01_NR (8)
#define S5PV210_GPIO_MP02_NR (4)
#define S5PV210_GPIO_MP03_NR (8)
#define S5PV210_GPIO_MP04_NR (8)
#define S5PV210_GPIO_MP05_NR (8)
/* GPIO bank numbers */
/* CONFIG_S3C_GPIO_SPACE allows the user to select extra
* space for debugging purposes so that any accidental
* change from one gpio bank to another can be caught.
*/
#define S5PV210_GPIO_NEXT(__gpio) \
((__gpio##_START) + (__gpio##_NR) + CONFIG_S3C_GPIO_SPACE + 1)
enum s5p_gpio_number {
S5PV210_GPIO_A0_START = 0,
S5PV210_GPIO_A1_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_A0),
S5PV210_GPIO_B_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_A1),
S5PV210_GPIO_C0_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_B),
S5PV210_GPIO_C1_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_C0),
S5PV210_GPIO_D0_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_C1),
S5PV210_GPIO_D1_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_D0),
S5PV210_GPIO_E0_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_D1),
S5PV210_GPIO_E1_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_E0),
S5PV210_GPIO_F0_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_E1),
S5PV210_GPIO_F1_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_F0),
S5PV210_GPIO_F2_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_F1),
S5PV210_GPIO_F3_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_F2),
S5PV210_GPIO_G0_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_F3),
S5PV210_GPIO_G1_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_G0),
S5PV210_GPIO_G2_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_G1),
S5PV210_GPIO_G3_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_G2),
S5PV210_GPIO_H0_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_G3),
S5PV210_GPIO_H1_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_H0),
S5PV210_GPIO_H2_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_H1),
S5PV210_GPIO_H3_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_H2),
S5PV210_GPIO_I_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_H3),
S5PV210_GPIO_J0_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_I),
S5PV210_GPIO_J1_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_J0),
S5PV210_GPIO_J2_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_J1),
S5PV210_GPIO_J3_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_J2),
S5PV210_GPIO_J4_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_J3),
S5PV210_GPIO_MP01_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_J4),
S5PV210_GPIO_MP02_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_MP01),
S5PV210_GPIO_MP03_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_MP02),
S5PV210_GPIO_MP04_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_MP03),
S5PV210_GPIO_MP05_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_MP04),
};
/* S5PV210 GPIO number definitions */
#define S5PV210_GPA0(_nr) (S5PV210_GPIO_A0_START + (_nr))
#define S5PV210_GPA1(_nr) (S5PV210_GPIO_A1_START + (_nr))
#define S5PV210_GPB(_nr) (S5PV210_GPIO_B_START + (_nr))
#define S5PV210_GPC0(_nr) (S5PV210_GPIO_C0_START + (_nr))
#define S5PV210_GPC1(_nr) (S5PV210_GPIO_C1_START + (_nr))
#define S5PV210_GPD0(_nr) (S5PV210_GPIO_D0_START + (_nr))
#define S5PV210_GPD1(_nr) (S5PV210_GPIO_D1_START + (_nr))
#define S5PV210_GPE0(_nr) (S5PV210_GPIO_E0_START + (_nr))
#define S5PV210_GPE1(_nr) (S5PV210_GPIO_E1_START + (_nr))
#define S5PV210_GPF0(_nr) (S5PV210_GPIO_F0_START + (_nr))
#define S5PV210_GPF1(_nr) (S5PV210_GPIO_F1_START + (_nr))
#define S5PV210_GPF2(_nr) (S5PV210_GPIO_F2_START + (_nr))
#define S5PV210_GPF3(_nr) (S5PV210_GPIO_F3_START + (_nr))
#define S5PV210_GPG0(_nr) (S5PV210_GPIO_G0_START + (_nr))
#define S5PV210_GPG1(_nr) (S5PV210_GPIO_G1_START + (_nr))
#define S5PV210_GPG2(_nr) (S5PV210_GPIO_G2_START + (_nr))
#define S5PV210_GPG3(_nr) (S5PV210_GPIO_G3_START + (_nr))
#define S5PV210_GPH0(_nr) (S5PV210_GPIO_H0_START + (_nr))
#define S5PV210_GPH1(_nr) (S5PV210_GPIO_H1_START + (_nr))
#define S5PV210_GPH2(_nr) (S5PV210_GPIO_H2_START + (_nr))
#define S5PV210_GPH3(_nr) (S5PV210_GPIO_H3_START + (_nr))
#define S5PV210_GPI(_nr) (S5PV210_GPIO_I_START + (_nr))
#define S5PV210_GPJ0(_nr) (S5PV210_GPIO_J0_START + (_nr))
#define S5PV210_GPJ1(_nr) (S5PV210_GPIO_J1_START + (_nr))
#define S5PV210_GPJ2(_nr) (S5PV210_GPIO_J2_START + (_nr))
#define S5PV210_GPJ3(_nr) (S5PV210_GPIO_J3_START + (_nr))
#define S5PV210_GPJ4(_nr) (S5PV210_GPIO_J4_START + (_nr))
#define S5PV210_MP01(_nr) (S5PV210_GPIO_MP01_START + (_nr))
#define S5PV210_MP02(_nr) (S5PV210_GPIO_MP02_START + (_nr))
#define S5PV210_MP03(_nr) (S5PV210_GPIO_MP03_START + (_nr))
#define S5PV210_MP04(_nr) (S5PV210_GPIO_MP04_START + (_nr))
#define S5PV210_MP05(_nr) (S5PV210_GPIO_MP05_START + (_nr))
/* the end of the S5PV210 specific gpios */
#define S5PV210_GPIO_END (S5PV210_MP05(S5PV210_GPIO_MP05_NR) + 1)
#define S3C_GPIO_END S5PV210_GPIO_END
/* define the number of gpios we need to the one after the MP05() range */
#define ARCH_NR_GPIOS (S5PV210_MP05(S5PV210_GPIO_MP05_NR) + \
CONFIG_SAMSUNG_GPIO_EXTRA + 1)
#endif /* __ASM_ARCH_GPIO_H */

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arch/arm/mach-s5pv210/include/mach/hardware.h
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/* linux/arch/arm/mach-s5pv210/include/mach/hardware.h
*
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
* http://www.samsung.com/
*
* S5PV210 - Hardware support
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_HARDWARE_H
#define __ASM_ARCH_HARDWARE_H __FILE__
/* currently nothing here, placeholder */
#endif /* __ASM_ARCH_HARDWARE_H */

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arch/arm/mach-s5pv210/include/mach/irqs.h
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/* linux/arch/arm/mach-s5pv210/include/mach/irqs.h
*
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
* http://www.samsung.com/
*
* S5PV210 - IRQ definitions
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_IRQS_H
#define __ASM_ARCH_IRQS_H __FILE__
#include <plat/irqs.h>
/* VIC0: System, DMA, Timer */
#define IRQ_EINT16_31 S5P_IRQ_VIC0(16)
#define IRQ_BATF S5P_IRQ_VIC0(17)
#define IRQ_MDMA S5P_IRQ_VIC0(18)
#define IRQ_PDMA0 S5P_IRQ_VIC0(19)
#define IRQ_PDMA1 S5P_IRQ_VIC0(20)
#define IRQ_TIMER0_VIC S5P_IRQ_VIC0(21)
#define IRQ_TIMER1_VIC S5P_IRQ_VIC0(22)
#define IRQ_TIMER2_VIC S5P_IRQ_VIC0(23)
#define IRQ_TIMER3_VIC S5P_IRQ_VIC0(24)
#define IRQ_TIMER4_VIC S5P_IRQ_VIC0(25)
#define IRQ_SYSTIMER S5P_IRQ_VIC0(26)
#define IRQ_WDT S5P_IRQ_VIC0(27)
#define IRQ_RTC_ALARM S5P_IRQ_VIC0(28)
#define IRQ_RTC_TIC S5P_IRQ_VIC0(29)
#define IRQ_GPIOINT S5P_IRQ_VIC0(30)
#define IRQ_FIMC3 S5P_IRQ_VIC0(31)
/* VIC1: ARM, Power, Memory, Connectivity, Storage */
#define IRQ_PMU S5P_IRQ_VIC1(0)
#define IRQ_CORTEX1 S5P_IRQ_VIC1(1)
#define IRQ_CORTEX2 S5P_IRQ_VIC1(2)
#define IRQ_CORTEX3 S5P_IRQ_VIC1(3)
#define IRQ_CORTEX4 S5P_IRQ_VIC1(4)
#define IRQ_IEMAPC S5P_IRQ_VIC1(5)
#define IRQ_IEMIEC S5P_IRQ_VIC1(6)
#define IRQ_ONENAND S5P_IRQ_VIC1(7)
#define IRQ_NFC S5P_IRQ_VIC1(8)
#define IRQ_CFCON S5P_IRQ_VIC1(9)
#define IRQ_UART0 S5P_IRQ_VIC1(10)
#define IRQ_UART1 S5P_IRQ_VIC1(11)
#define IRQ_UART2 S5P_IRQ_VIC1(12)
#define IRQ_UART3 S5P_IRQ_VIC1(13)
#define IRQ_IIC S5P_IRQ_VIC1(14)
#define IRQ_SPI0 S5P_IRQ_VIC1(15)
#define IRQ_SPI1 S5P_IRQ_VIC1(16)
#define IRQ_SPI2 S5P_IRQ_VIC1(17)
#define IRQ_IRDA S5P_IRQ_VIC1(18)
#define IRQ_IIC2 S5P_IRQ_VIC1(19)
#define IRQ_IIC_HDMIPHY S5P_IRQ_VIC1(20)
#define IRQ_HSIRX S5P_IRQ_VIC1(21)
#define IRQ_HSITX S5P_IRQ_VIC1(22)
#define IRQ_UHOST S5P_IRQ_VIC1(23)
#define IRQ_OTG S5P_IRQ_VIC1(24)
#define IRQ_MSM S5P_IRQ_VIC1(25)
#define IRQ_HSMMC0 S5P_IRQ_VIC1(26)
#define IRQ_HSMMC1 S5P_IRQ_VIC1(27)
#define IRQ_HSMMC2 S5P_IRQ_VIC1(28)
#define IRQ_MIPI_CSIS S5P_IRQ_VIC1(29)
#define IRQ_MIPIDSI S5P_IRQ_VIC1(30)
#define IRQ_ONENAND_AUDI S5P_IRQ_VIC1(31)
/* VIC2: Multimedia, Audio, Security */
#define IRQ_LCD0 S5P_IRQ_VIC2(0)
#define IRQ_LCD1 S5P_IRQ_VIC2(1)
#define IRQ_LCD2 S5P_IRQ_VIC2(2)
#define IRQ_LCD3 S5P_IRQ_VIC2(3)
#define IRQ_ROTATOR S5P_IRQ_VIC2(4)
#define IRQ_FIMC0 S5P_IRQ_VIC2(5)
#define IRQ_FIMC1 S5P_IRQ_VIC2(6)
#define IRQ_FIMC2 S5P_IRQ_VIC2(7)
#define IRQ_JPEG S5P_IRQ_VIC2(8)
#define IRQ_2D S5P_IRQ_VIC2(9)
#define IRQ_3D S5P_IRQ_VIC2(10)
#define IRQ_MIXER S5P_IRQ_VIC2(11)
#define IRQ_HDMI S5P_IRQ_VIC2(12)
#define IRQ_IIC1 S5P_IRQ_VIC2(13)
#define IRQ_MFC S5P_IRQ_VIC2(14)
#define IRQ_SDO S5P_IRQ_VIC2(15)
#define IRQ_I2S0 S5P_IRQ_VIC2(16)
#define IRQ_I2S1 S5P_IRQ_VIC2(17)
#define IRQ_I2S2 S5P_IRQ_VIC2(18)
#define IRQ_AC97 S5P_IRQ_VIC2(19)
#define IRQ_PCM0 S5P_IRQ_VIC2(20)
#define IRQ_PCM1 S5P_IRQ_VIC2(21)
#define IRQ_SPDIF S5P_IRQ_VIC2(22)
#define IRQ_ADC S5P_IRQ_VIC2(23)
#define IRQ_PENDN S5P_IRQ_VIC2(24)
#define IRQ_TC IRQ_PENDN
#define IRQ_KEYPAD S5P_IRQ_VIC2(25)
#define IRQ_CG S5P_IRQ_VIC2(26)
#define IRQ_SSS_INT S5P_IRQ_VIC2(27)
#define IRQ_SSS_HASH S5P_IRQ_VIC2(28)
#define IRQ_PCM2 S5P_IRQ_VIC2(29)
#define IRQ_SDMIRQ S5P_IRQ_VIC2(30)
#define IRQ_SDMFIQ S5P_IRQ_VIC2(31)
/* VIC3: Etc */
#define IRQ_IPC S5P_IRQ_VIC3(0)
#define IRQ_HOSTIF S5P_IRQ_VIC3(1)
#define IRQ_HSMMC3 S5P_IRQ_VIC3(2)
#define IRQ_CEC S5P_IRQ_VIC3(3)
#define IRQ_TSI S5P_IRQ_VIC3(4)
#define IRQ_MDNIE0 S5P_IRQ_VIC3(5)
#define IRQ_MDNIE1 S5P_IRQ_VIC3(6)
#define IRQ_MDNIE2 S5P_IRQ_VIC3(7)
#define IRQ_MDNIE3 S5P_IRQ_VIC3(8)
#define IRQ_VIC_END S5P_IRQ_VIC3(31)
#define S5P_EINT_BASE1 (S5P_IRQ_VIC0(0))
#define S5P_EINT_BASE2 (IRQ_VIC_END + 1)
/* GPIO interrupt */
#define S5P_GPIOINT_BASE (IRQ_EINT(31) + 1)
#define S5P_GPIOINT_GROUP_MAXNR 22
/* Set the default NR_IRQS */
#define NR_IRQS (IRQ_EINT(31) + S5P_GPIOINT_COUNT + 1)
/* Compatibility */
#define IRQ_LCD_FIFO IRQ_LCD0
#define IRQ_LCD_VSYNC IRQ_LCD1
#define IRQ_LCD_SYSTEM IRQ_LCD2
#define IRQ_MIPI_CSIS0 IRQ_MIPI_CSIS
#endif /* ASM_ARCH_IRQS_H */

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arch/arm/mach-s5pv210/include/mach/map.h
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/* linux/arch/arm/mach-s5pv210/include/mach/map.h
*
* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
* http://www.samsung.com/
*
* S5PV210 - Memory map definitions
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_MAP_H
#define __ASM_ARCH_MAP_H __FILE__
#include <plat/map-base.h>
#include <plat/map-s5p.h>
#define S5PV210_PA_SDRAM 0x20000000
#define S5PV210_PA_SROM_BANK5 0xA8000000
#define S5PC110_PA_ONENAND 0xB0000000
#define S5PC110_PA_ONENAND_DMA 0xB0600000
#define S5PV210_PA_CHIPID 0xE0000000
#define S5PV210_PA_SYSCON 0xE0100000
#define S5PV210_PA_GPIO 0xE0200000
#define S5PV210_PA_SPDIF 0xE1100000
#define S5PV210_PA_SPI0 0xE1300000
#define S5PV210_PA_SPI1 0xE1400000
#define S5PV210_PA_KEYPAD 0xE1600000
#define S5PV210_PA_ADC 0xE1700000
#define S5PV210_PA_IIC0 0xE1800000
#define S5PV210_PA_IIC1 0xFAB00000
#define S5PV210_PA_IIC2 0xE1A00000
#define S5PV210_PA_AC97 0xE2200000
#define S5PV210_PA_PCM0 0xE2300000
#define S5PV210_PA_PCM1 0xE1200000
#define S5PV210_PA_PCM2 0xE2B00000
#define S5PV210_PA_TIMER 0xE2500000
#define S5PV210_PA_SYSTIMER 0xE2600000
#define S5PV210_PA_WATCHDOG 0xE2700000
#define S5PV210_PA_RTC 0xE2800000
#define S5PV210_PA_UART 0xE2900000
#define S5PV210_PA_SROMC 0xE8000000
#define S5PV210_PA_CFCON 0xE8200000
#define S5PV210_PA_MFC 0xF1700000
#define S5PV210_PA_HSMMC(x) (0xEB000000 + ((x) * 0x100000))
#define S5PV210_PA_HSOTG 0xEC000000
#define S5PV210_PA_HSPHY 0xEC100000
#define S5PV210_PA_IIS0 0xEEE30000
#define S5PV210_PA_IIS1 0xE2100000
#define S5PV210_PA_IIS2 0xE2A00000
#define S5PV210_PA_DMC0 0xF0000000
#define S5PV210_PA_DMC1 0xF1400000
#define S5PV210_PA_VIC0 0xF2000000
#define S5PV210_PA_VIC1 0xF2100000
#define S5PV210_PA_VIC2 0xF2200000
#define S5PV210_PA_VIC3 0xF2300000
#define S5PV210_PA_FB 0xF8000000
#define S5PV210_PA_MDMA 0xFA200000
#define S5PV210_PA_PDMA0 0xE0900000
#define S5PV210_PA_PDMA1 0xE0A00000
#define S5PV210_PA_MIPI_CSIS 0xFA600000
#define S5PV210_PA_FIMC0 0xFB200000
#define S5PV210_PA_FIMC1 0xFB300000
#define S5PV210_PA_FIMC2 0xFB400000
#define S5PV210_PA_JPEG 0xFB600000
#define S5PV210_PA_SDO 0xF9000000
#define S5PV210_PA_VP 0xF9100000
#define S5PV210_PA_MIXER 0xF9200000
#define S5PV210_PA_HDMI 0xFA100000
#define S5PV210_PA_IIC_HDMIPHY 0xFA900000
/* Compatibiltiy Defines */
#define S3C_PA_FB S5PV210_PA_FB
#define S3C_PA_HSMMC0 S5PV210_PA_HSMMC(0)
#define S3C_PA_HSMMC1 S5PV210_PA_HSMMC(1)
#define S3C_PA_HSMMC2 S5PV210_PA_HSMMC(2)
#define S3C_PA_HSMMC3 S5PV210_PA_HSMMC(3)
#define S3C_PA_IIC S5PV210_PA_IIC0
#define S3C_PA_IIC1 S5PV210_PA_IIC1
#define S3C_PA_IIC2 S5PV210_PA_IIC2
#define S3C_PA_RTC S5PV210_PA_RTC
#define S3C_PA_USB_HSOTG S5PV210_PA_HSOTG
#define S3C_PA_WDT S5PV210_PA_WATCHDOG
#define S3C_PA_SPI0 S5PV210_PA_SPI0
#define S3C_PA_SPI1 S5PV210_PA_SPI1
#define S5P_PA_CHIPID S5PV210_PA_CHIPID
#define S5P_PA_FIMC0 S5PV210_PA_FIMC0
#define S5P_PA_FIMC1 S5PV210_PA_FIMC1
#define S5P_PA_FIMC2 S5PV210_PA_FIMC2
#define S5P_PA_MIPI_CSIS0 S5PV210_PA_MIPI_CSIS
#define S5P_PA_MFC S5PV210_PA_MFC
#define S5P_PA_IIC_HDMIPHY S5PV210_PA_IIC_HDMIPHY
#define S5P_PA_SDO S5PV210_PA_SDO
#define S5P_PA_VP S5PV210_PA_VP
#define S5P_PA_MIXER S5PV210_PA_MIXER
#define S5P_PA_HDMI S5PV210_PA_HDMI
#define S5P_PA_ONENAND S5PC110_PA_ONENAND
#define S5P_PA_ONENAND_DMA S5PC110_PA_ONENAND_DMA
#define S5P_PA_SDRAM S5PV210_PA_SDRAM
#define S5P_PA_SROMC S5PV210_PA_SROMC
#define S5P_PA_SYSCON S5PV210_PA_SYSCON
#define S5P_PA_TIMER S5PV210_PA_TIMER
#define S5P_PA_JPEG S5PV210_PA_JPEG
#define SAMSUNG_PA_ADC S5PV210_PA_ADC
#define SAMSUNG_PA_CFCON S5PV210_PA_CFCON
#define SAMSUNG_PA_KEYPAD S5PV210_PA_KEYPAD
#define SAMSUNG_PA_TIMER S5PV210_PA_TIMER
/* UART */
#define S3C_VA_UARTx(x) (S3C_VA_UART + ((x) * S3C_UART_OFFSET))
#define S3C_PA_UART S5PV210_PA_UART
#define S5P_PA_UART(x) (S3C_PA_UART + ((x) * S3C_UART_OFFSET))
#define S5P_PA_UART0 S5P_PA_UART(0)
#define S5P_PA_UART1 S5P_PA_UART(1)
#define S5P_PA_UART2 S5P_PA_UART(2)
#define S5P_PA_UART3 S5P_PA_UART(3)
#define S5P_SZ_UART SZ_256
#endif /* __ASM_ARCH_MAP_H */

27
arch/arm/mach-s5pv210/include/mach/memory.h
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@ -1,27 +0,0 @@
/* linux/arch/arm/mach-s5pv210/include/mach/memory.h
*
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
* http://www.samsung.com/
*
* S5PV210 - Memory definitions
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_MEMORY_H
#define __ASM_ARCH_MEMORY_H
#define PLAT_PHYS_OFFSET UL(0x20000000)
/*
* Sparsemem support
* Physical memory can be located from 0x20000000 to 0x7fffffff,
* so MAX_PHYSMEM_BITS is 31.
*/
#define MAX_PHYSMEM_BITS 31
#define SECTION_SIZE_BITS 28
#endif /* __ASM_ARCH_MEMORY_H */

46
arch/arm/mach-s5pv210/include/mach/pm-core.h
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/* linux/arch/arm/mach-s5pv210/include/mach/pm-core.h
*
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* Based on arch/arm/mach-s3c2410/include/mach/pm-core.h,
* Copyright 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
* S5PV210 - PM core support for arch/arm/plat-s5p/pm.c
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
static inline void s3c_pm_debug_init_uart(void)
{
/* nothing here yet */
}
static inline void s3c_pm_arch_prepare_irqs(void)
{
__raw_writel(s3c_irqwake_intmask, S5P_WAKEUP_MASK);
__raw_writel(s3c_irqwake_eintmask, S5P_EINT_WAKEUP_MASK);
}
static inline void s3c_pm_arch_stop_clocks(void)
{
/* nothing here yet */
}
static inline void s3c_pm_arch_show_resume_irqs(void)
{
/* nothing here yet */
}
static inline void s3c_pm_arch_update_uart(void __iomem *regs,
struct pm_uart_save *save)
{
/* nothing here yet */
}
static inline void s3c_pm_restored_gpios(void) { }
static inline void samsung_pm_saved_gpios(void) { }

2
arch/arm/mach-s5pv210/include/mach/regs-clock.h
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@ -13,7 +13,7 @@
#ifndef __ASM_ARCH_REGS_CLOCK_H
#define __ASM_ARCH_REGS_CLOCK_H __FILE__
#include <mach/map.h>
#include <plat/map-base.h>
#define S5P_CLKREG(x) (S3C_VA_SYS + (x))

41
arch/arm/mach-s5pv210/include/mach/regs-gpio.h
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/* linux/arch/arm/mach-s5pv210/include/mach/regs-gpio.h
*
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* S5PV210 - GPIO (including EINT) register definitions
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_REGS_GPIO_H
#define __ASM_ARCH_REGS_GPIO_H __FILE__
#include <mach/map.h>
#define S5PV210_EINT30CON (S5P_VA_GPIO + 0xE00)
#define S5P_EINT_CON(x) (S5PV210_EINT30CON + ((x) * 0x4))
#define S5PV210_EINT30FLTCON0 (S5P_VA_GPIO + 0xE80)
#define S5P_EINT_FLTCON(x) (S5PV210_EINT30FLTCON0 + ((x) * 0x4))
#define S5PV210_EINT30MASK (S5P_VA_GPIO + 0xF00)
#define S5P_EINT_MASK(x) (S5PV210_EINT30MASK + ((x) * 0x4))
#define S5PV210_EINT30PEND (S5P_VA_GPIO + 0xF40)
#define S5P_EINT_PEND(x) (S5PV210_EINT30PEND + ((x) * 0x4))
#define EINT_REG_NR(x) (EINT_OFFSET(x) >> 3)
#define eint_irq_to_bit(irq) (1 << (EINT_OFFSET(irq) & 0x7))
#define EINT_MODE S3C_GPIO_SFN(0xf)
#define EINT_GPIO_0(x) S5PV210_GPH0(x)
#define EINT_GPIO_1(x) S5PV210_GPH1(x)
#define EINT_GPIO_2(x) S5PV210_GPH2(x)
#define EINT_GPIO_3(x) S5PV210_GPH3(x)
#endif /* __ASM_ARCH_REGS_GPIO_H */

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arch/arm/mach-s5pv210/include/mach/regs-irq.h
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/* linux/arch/arm/mach-s5pv210/include/mach/regs-irq.h
*
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
* http://www.samsung.com/
*
* S5PV210 - IRQ register definitions
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_REGS_IRQ_H
#define __ASM_ARCH_REGS_IRQ_H __FILE__
#include <mach/map.h>
#endif /* __ASM_ARCH_REGS_IRQ_H */

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arch/arm/mach-s5pv210/mach-aquila.c
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/* linux/arch/arm/mach-s5pv210/mach-aquila.c
*
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
* http://www.samsung.com/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/init.h>
#include <linux/serial_core.h>
#include <linux/serial_s3c.h>
#include <linux/fb.h>
#include <linux/i2c.h>
#include <linux/i2c-gpio.h>
#include <linux/mfd/max8998.h>
#include <linux/mfd/wm8994/pdata.h>
#include <linux/regulator/fixed.h>
#include <linux/gpio_keys.h>
#include <linux/input.h>
#include <linux/gpio.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/setup.h>
#include <asm/mach-types.h>
#include <video/samsung_fimd.h>
#include <mach/map.h>
#include <mach/regs-clock.h>
#include <plat/gpio-cfg.h>
#include <plat/devs.h>
#include <plat/cpu.h>
#include <plat/fb.h>
#include <plat/fimc-core.h>
#include <plat/sdhci.h>
#include <plat/samsung-time.h>
#include "common.h"
/* Following are default values for UCON, ULCON and UFCON UART registers */
#define AQUILA_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
S3C2410_UCON_RXILEVEL | \
S3C2410_UCON_TXIRQMODE | \
S3C2410_UCON_RXIRQMODE | \
S3C2410_UCON_RXFIFO_TOI | \
S3C2443_UCON_RXERR_IRQEN)
#define AQUILA_ULCON_DEFAULT S3C2410_LCON_CS8
#define AQUILA_UFCON_DEFAULT S3C2410_UFCON_FIFOMODE
static struct s3c2410_uartcfg aquila_uartcfgs[] __initdata = {
[0] = {
.hwport = 0,
.flags = 0,
.ucon = AQUILA_UCON_DEFAULT,
.ulcon = AQUILA_ULCON_DEFAULT,
/*
* Actually UART0 can support 256 bytes fifo, but aquila board
* supports 128 bytes fifo because of initial chip bug
*/
.ufcon = AQUILA_UFCON_DEFAULT |
S5PV210_UFCON_TXTRIG128 | S5PV210_UFCON_RXTRIG128,
},
[1] = {
.hwport = 1,
.flags = 0,
.ucon = AQUILA_UCON_DEFAULT,
.ulcon = AQUILA_ULCON_DEFAULT,
.ufcon = AQUILA_UFCON_DEFAULT |
S5PV210_UFCON_TXTRIG64 | S5PV210_UFCON_RXTRIG64,
},
[2] = {
.hwport = 2,
.flags = 0,
.ucon = AQUILA_UCON_DEFAULT,
.ulcon = AQUILA_ULCON_DEFAULT,
.ufcon = AQUILA_UFCON_DEFAULT |
S5PV210_UFCON_TXTRIG16 | S5PV210_UFCON_RXTRIG16,
},
[3] = {
.hwport = 3,
.flags = 0,
.ucon = AQUILA_UCON_DEFAULT,
.ulcon = AQUILA_ULCON_DEFAULT,
.ufcon = AQUILA_UFCON_DEFAULT |
S5PV210_UFCON_TXTRIG16 | S5PV210_UFCON_RXTRIG16,
},
};
/* Frame Buffer */
static struct s3c_fb_pd_win aquila_fb_win0 = {
.max_bpp = 32,
.default_bpp = 16,
.xres = 480,
.yres = 800,
};
static struct s3c_fb_pd_win aquila_fb_win1 = {
.max_bpp = 32,
.default_bpp = 16,
.xres = 480,
.yres = 800,
};
static struct fb_videomode aquila_lcd_timing = {
.left_margin = 16,
.right_margin = 16,
.upper_margin = 3,
.lower_margin = 28,
.hsync_len = 2,
.vsync_len = 2,
.xres = 480,
.yres = 800,
};
static struct s3c_fb_platdata aquila_lcd_pdata __initdata = {
.win[0] = &aquila_fb_win0,
.win[1] = &aquila_fb_win1,
.vtiming = &aquila_lcd_timing,
.vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
.vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC |
VIDCON1_INV_VCLK | VIDCON1_INV_VDEN,
.setup_gpio = s5pv210_fb_gpio_setup_24bpp,
};
/* MAX8998 regulators */
#if defined(CONFIG_REGULATOR_MAX8998) || defined(CONFIG_REGULATOR_MAX8998_MODULE)
static struct regulator_init_data aquila_ldo2_data = {
.constraints = {
.name = "VALIVE_1.1V",
.min_uV = 1100000,
.max_uV = 1100000,
.apply_uV = 1,
.always_on = 1,
.state_mem = {
.enabled = 1,
},
},
};
static struct regulator_init_data aquila_ldo3_data = {
.constraints = {
.name = "VUSB+MIPI_1.1V",
.min_uV = 1100000,
.max_uV = 1100000,
.apply_uV = 1,
.always_on = 1,
},
};
static struct regulator_init_data aquila_ldo4_data = {
.constraints = {
.name = "VDAC_3.3V",
.min_uV = 3300000,
.max_uV = 3300000,
.apply_uV = 1,
},
};
static struct regulator_init_data aquila_ldo5_data = {
.constraints = {
.name = "VTF_2.8V",
.min_uV = 2800000,
.max_uV = 2800000,
.apply_uV = 1,
},
};
static struct regulator_init_data aquila_ldo6_data = {
.constraints = {
.name = "VCC_3.3V",
.min_uV = 3300000,
.max_uV = 3300000,
.apply_uV = 1,
},
};
static struct regulator_init_data aquila_ldo7_data = {
.constraints = {
.name = "VCC_3.0V",
.min_uV = 3000000,
.max_uV = 3000000,
.apply_uV = 1,
.boot_on = 1,
.always_on = 1,
},
};
static struct regulator_init_data aquila_ldo8_data = {
.constraints = {
.name = "VUSB+VADC_3.3V",
.min_uV = 3300000,
.max_uV = 3300000,
.apply_uV = 1,
.always_on = 1,
},
};
static struct regulator_init_data aquila_ldo9_data = {
.constraints = {
.name = "VCC+VCAM_2.8V",
.min_uV = 2800000,
.max_uV = 2800000,
.apply_uV = 1,
.always_on = 1,
},
};
static struct regulator_init_data aquila_ldo10_data = {
.constraints = {
.name = "VPLL_1.1V",
.min_uV = 1100000,
.max_uV = 1100000,
.apply_uV = 1,
.boot_on = 1,
},
};
static struct regulator_init_data aquila_ldo11_data = {
.constraints = {
.name = "CAM_IO_2.8V",
.min_uV = 2800000,
.max_uV = 2800000,
.apply_uV = 1,
.always_on = 1,
},
};
static struct regulator_init_data aquila_ldo12_data = {
.constraints = {
.name = "CAM_ISP_1.2V",
.min_uV = 1200000,
.max_uV = 1200000,
.apply_uV = 1,
.always_on = 1,
},
};
static struct regulator_init_data aquila_ldo13_data = {
.constraints = {
.name = "CAM_A_2.8V",
.min_uV = 2800000,
.max_uV = 2800000,
.apply_uV = 1,
.always_on = 1,
},
};
static struct regulator_init_data aquila_ldo14_data = {
.constraints = {
.name = "CAM_CIF_1.8V",
.min_uV = 1800000,
.max_uV = 1800000,
.apply_uV = 1,
.always_on = 1,
},
};
static struct regulator_init_data aquila_ldo15_data = {
.constraints = {
.name = "CAM_AF_3.3V",
.min_uV = 3300000,
.max_uV = 3300000,
.apply_uV = 1,
.always_on = 1,
},
};
static struct regulator_init_data aquila_ldo16_data = {
.constraints = {
.name = "VMIPI_1.8V",
.min_uV = 1800000,
.max_uV = 1800000,
.apply_uV = 1,
.always_on = 1,
},
};
static struct regulator_init_data aquila_ldo17_data = {
.constraints = {
.name = "CAM_8M_1.8V",
.min_uV = 1800000,
.max_uV = 1800000,
.apply_uV = 1,
.always_on = 1,
},
};
/* BUCK */
static struct regulator_consumer_supply buck1_consumer =
REGULATOR_SUPPLY("vddarm", NULL);
static struct regulator_consumer_supply buck2_consumer =
REGULATOR_SUPPLY("vddint", NULL);
static struct regulator_init_data aquila_buck1_data = {
.constraints = {
.name = "VARM_1.2V",
.min_uV = 1200000,
.max_uV = 1200000,
.apply_uV = 1,
.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
REGULATOR_CHANGE_STATUS,
},
.num_consumer_supplies = 1,
.consumer_supplies = &buck1_consumer,
};
static struct regulator_init_data aquila_buck2_data = {
.constraints = {
.name = "VINT_1.2V",
.min_uV = 1200000,
.max_uV = 1200000,
.apply_uV = 1,
.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
REGULATOR_CHANGE_STATUS,
},
.num_consumer_supplies = 1,
.consumer_supplies = &buck2_consumer,
};
static struct regulator_init_data aquila_buck3_data = {
.constraints = {
.name = "VCC_1.8V",
.min_uV = 1800000,
.max_uV = 1800000,
.apply_uV = 1,
.state_mem = {
.enabled = 1,
},
},
};
static struct regulator_init_data aquila_buck4_data = {
.constraints = {
.name = "CAM_CORE_1.2V",
.min_uV = 1200000,
.max_uV = 1200000,
.apply_uV = 1,
.always_on = 1,
},
};
static struct max8998_regulator_data aquila_regulators[] = {
{ MAX8998_LDO2, &aquila_ldo2_data },
{ MAX8998_LDO3, &aquila_ldo3_data },
{ MAX8998_LDO4, &aquila_ldo4_data },
{ MAX8998_LDO5, &aquila_ldo5_data },
{ MAX8998_LDO6, &aquila_ldo6_data },
{ MAX8998_LDO7, &aquila_ldo7_data },
{ MAX8998_LDO8, &aquila_ldo8_data },
{ MAX8998_LDO9, &aquila_ldo9_data },
{ MAX8998_LDO10, &aquila_ldo10_data },
{ MAX8998_LDO11, &aquila_ldo11_data },
{ MAX8998_LDO12, &aquila_ldo12_data },
{ MAX8998_LDO13, &aquila_ldo13_data },
{ MAX8998_LDO14, &aquila_ldo14_data },
{ MAX8998_LDO15, &aquila_ldo15_data },
{ MAX8998_LDO16, &aquila_ldo16_data },
{ MAX8998_LDO17, &aquila_ldo17_data },
{ MAX8998_BUCK1, &aquila_buck1_data },
{ MAX8998_BUCK2, &aquila_buck2_data },
{ MAX8998_BUCK3, &aquila_buck3_data },
{ MAX8998_BUCK4, &aquila_buck4_data },
};
static struct max8998_platform_data aquila_max8998_pdata = {
.num_regulators = ARRAY_SIZE(aquila_regulators),
.regulators = aquila_regulators,
.buck1_set1 = S5PV210_GPH0(3),
.buck1_set2 = S5PV210_GPH0(4),
.buck2_set3 = S5PV210_GPH0(5),
.buck1_voltage = { 1200000, 1200000, 1200000, 1200000 },
.buck2_voltage = { 1200000, 1200000 },
};
#endif
static struct regulator_consumer_supply wm8994_fixed_voltage0_supplies[] = {
REGULATOR_SUPPLY("DBVDD", "5-001a"),
REGULATOR_SUPPLY("AVDD2", "5-001a"),
REGULATOR_SUPPLY("CPVDD", "5-001a"),
};
static struct regulator_consumer_supply wm8994_fixed_voltage1_supplies[] = {
REGULATOR_SUPPLY("SPKVDD1", "5-001a"),
REGULATOR_SUPPLY("SPKVDD2", "5-001a"),
};
static struct regulator_init_data wm8994_fixed_voltage0_init_data = {
.constraints = {
.always_on = 1,
},
.num_consumer_supplies = ARRAY_SIZE(wm8994_fixed_voltage0_supplies),
.consumer_supplies = wm8994_fixed_voltage0_supplies,
};
static struct regulator_init_data wm8994_fixed_voltage1_init_data = {
.constraints = {
.always_on = 1,
},
.num_consumer_supplies = ARRAY_SIZE(wm8994_fixed_voltage1_supplies),
.consumer_supplies = wm8994_fixed_voltage1_supplies,
};
static struct fixed_voltage_config wm8994_fixed_voltage0_config = {
.supply_name = "VCC_1.8V_PDA",
.microvolts = 1800000,
.gpio = -EINVAL,
.init_data = &wm8994_fixed_voltage0_init_data,
};
static struct fixed_voltage_config wm8994_fixed_voltage1_config = {
.supply_name = "V_BAT",
.microvolts = 3700000,
.gpio = -EINVAL,
.init_data = &wm8994_fixed_voltage1_init_data,
};
static struct platform_device wm8994_fixed_voltage0 = {
.name = "reg-fixed-voltage",
.id = 0,
.dev = {
.platform_data = &wm8994_fixed_voltage0_config,
},
};
static struct platform_device wm8994_fixed_voltage1 = {
.name = "reg-fixed-voltage",
.id = 1,
.dev = {
.platform_data = &wm8994_fixed_voltage1_config,
},
};
static struct regulator_consumer_supply wm8994_avdd1_supply =
REGULATOR_SUPPLY("AVDD1", "5-001a");
static struct regulator_consumer_supply wm8994_dcvdd_supply =
REGULATOR_SUPPLY("DCVDD", "5-001a");
static struct regulator_init_data wm8994_ldo1_data = {
.constraints = {
.name = "AVDD1_3.0V",
.valid_ops_mask = REGULATOR_CHANGE_STATUS,
},
.num_consumer_supplies = 1,
.consumer_supplies = &wm8994_avdd1_supply,
};
static struct regulator_init_data wm8994_ldo2_data = {
.constraints = {
.name = "DCVDD_1.0V",
},
.num_consumer_supplies = 1,
.consumer_supplies = &wm8994_dcvdd_supply,
};
static struct wm8994_pdata wm8994_platform_data = {
/* configure gpio1 function: 0x0001(Logic level input/output) */
.gpio_defaults[0] = 0x0001,
/* configure gpio3/4/5/7 function for AIF2 voice */
.gpio_defaults[2] = 0x8100,
.gpio_defaults[3] = 0x8100,
.gpio_defaults[4] = 0x8100,
.gpio_defaults[6] = 0x0100,
/* configure gpio8/9/10/11 function for AIF3 BT */
.gpio_defaults[7] = 0x8100,
.gpio_defaults[8] = 0x0100,
.gpio_defaults[9] = 0x0100,
.gpio_defaults[10] = 0x0100,
.ldo[0] = { S5PV210_MP03(6), &wm8994_ldo1_data }, /* XM0FRNB_2 */
.ldo[1] = { 0, &wm8994_ldo2_data },
};
/* GPIO I2C PMIC */
#define AP_I2C_GPIO_PMIC_BUS_4 4
static struct i2c_gpio_platform_data aquila_i2c_gpio_pmic_data = {
.sda_pin = S5PV210_GPJ4(0), /* XMSMCSN */
.scl_pin = S5PV210_GPJ4(3), /* XMSMIRQN */
};
static struct platform_device aquila_i2c_gpio_pmic = {
.name = "i2c-gpio",
.id = AP_I2C_GPIO_PMIC_BUS_4,
.dev = {
.platform_data = &aquila_i2c_gpio_pmic_data,
},
};
static struct i2c_board_info i2c_gpio_pmic_devs[] __initdata = {
#if defined(CONFIG_REGULATOR_MAX8998) || defined(CONFIG_REGULATOR_MAX8998_MODULE)
{
/* 0xCC when SRAD = 0 */
I2C_BOARD_INFO("max8998", 0xCC >> 1),
.platform_data = &aquila_max8998_pdata,
},
#endif
};
/* GPIO I2C AP 1.8V */
#define AP_I2C_GPIO_BUS_5 5
static struct i2c_gpio_platform_data aquila_i2c_gpio5_data = {
.sda_pin = S5PV210_MP05(3), /* XM0ADDR_11 */
.scl_pin = S5PV210_MP05(2), /* XM0ADDR_10 */
};
static struct platform_device aquila_i2c_gpio5 = {
.name = "i2c-gpio",
.id = AP_I2C_GPIO_BUS_5,
.dev = {
.platform_data = &aquila_i2c_gpio5_data,
},
};
static struct i2c_board_info i2c_gpio5_devs[] __initdata = {
{
/* CS/ADDR = low 0x34 (FYI: high = 0x36) */
I2C_BOARD_INFO("wm8994", 0x1a),
.platform_data = &wm8994_platform_data,
},
};
/* PMIC Power button */
static struct gpio_keys_button aquila_gpio_keys_table[] = {
{
.code = KEY_POWER,
.gpio = S5PV210_GPH2(6),
.desc = "gpio-keys: KEY_POWER",
.type = EV_KEY,
.active_low = 1,
.wakeup = 1,
.debounce_interval = 1,
},
};
static struct gpio_keys_platform_data aquila_gpio_keys_data = {
.buttons = aquila_gpio_keys_table,
.nbuttons = ARRAY_SIZE(aquila_gpio_keys_table),
};
static struct platform_device aquila_device_gpiokeys = {
.name = "gpio-keys",
.dev = {
.platform_data = &aquila_gpio_keys_data,
},
};
static void __init aquila_pmic_init(void)
{
/* AP_PMIC_IRQ: EINT7 */
s3c_gpio_cfgpin(S5PV210_GPH0(7), S3C_GPIO_SFN(0xf));
s3c_gpio_setpull(S5PV210_GPH0(7), S3C_GPIO_PULL_UP);
/* nPower: EINT22 */
s3c_gpio_cfgpin(S5PV210_GPH2(6), S3C_GPIO_SFN(0xf));
s3c_gpio_setpull(S5PV210_GPH2(6), S3C_GPIO_PULL_UP);
}
/* MoviNAND */
static struct s3c_sdhci_platdata aquila_hsmmc0_data __initdata = {
.max_width = 4,
.cd_type = S3C_SDHCI_CD_PERMANENT,
};
/* Wireless LAN */
static struct s3c_sdhci_platdata aquila_hsmmc1_data __initdata = {
.max_width = 4,
.cd_type = S3C_SDHCI_CD_EXTERNAL,
/* ext_cd_{init,cleanup} callbacks will be added later */
};
/* External Flash */
#define AQUILA_EXT_FLASH_EN S5PV210_MP05(4)
#define AQUILA_EXT_FLASH_CD S5PV210_GPH3(4)
static struct s3c_sdhci_platdata aquila_hsmmc2_data __initdata = {
.max_width = 4,
.cd_type = S3C_SDHCI_CD_GPIO,
.ext_cd_gpio = AQUILA_EXT_FLASH_CD,
.ext_cd_gpio_invert = 1,
};
static void aquila_setup_sdhci(void)
{
gpio_request_one(AQUILA_EXT_FLASH_EN, GPIOF_OUT_INIT_HIGH, "FLASH_EN");
s3c_sdhci0_set_platdata(&aquila_hsmmc0_data);
s3c_sdhci1_set_platdata(&aquila_hsmmc1_data);
s3c_sdhci2_set_platdata(&aquila_hsmmc2_data);
};
/* Audio device */
static struct platform_device aquila_device_audio = {
.name = "smdk-audio",
.id = -1,
};
static struct platform_device *aquila_devices[] __initdata = {
&aquila_i2c_gpio_pmic,
&aquila_i2c_gpio5,
&aquila_device_gpiokeys,
&aquila_device_audio,
&s3c_device_fb,
&s5p_device_onenand,
&s3c_device_hsmmc0,
&s3c_device_hsmmc1,
&s3c_device_hsmmc2,
&s5p_device_fimc0,
&s5p_device_fimc1,
&s5p_device_fimc2,
&s5p_device_fimc_md,
&s5pv210_device_iis0,
&wm8994_fixed_voltage0,
&wm8994_fixed_voltage1,
};
static void __init aquila_sound_init(void)
{
unsigned int gpio;
/* CODEC_XTAL_EN
*
* The Aquila board have a oscillator which provide main clock
* to WM8994 codec. The oscillator provide 24MHz clock to WM8994
* clock. Set gpio setting of "CODEC_XTAL_EN" to enable a oscillator.
* */
gpio = S5PV210_GPH3(2); /* XEINT_26 */
gpio_request(gpio, "CODEC_XTAL_EN");
s3c_gpio_cfgpin(gpio, S3C_GPIO_OUTPUT);
s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
/* Ths main clock of WM8994 codec uses the output of CLKOUT pin.
* The CLKOUT[9:8] set to 0x3(XUSBXTI) of 0xE010E000(OTHERS)
* because it needs 24MHz clock to operate WM8994 codec.
*/
__raw_writel(__raw_readl(S5P_OTHERS) | (0x3 << 8), S5P_OTHERS);
}
static void __init aquila_map_io(void)
{
s5pv210_init_io(NULL, 0);
s3c24xx_init_clocks(24000000);
s3c24xx_init_uarts(aquila_uartcfgs, ARRAY_SIZE(aquila_uartcfgs));
samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
}
static void __init aquila_machine_init(void)
{
/* PMIC */
aquila_pmic_init();
i2c_register_board_info(AP_I2C_GPIO_PMIC_BUS_4, i2c_gpio_pmic_devs,
ARRAY_SIZE(i2c_gpio_pmic_devs));
/* SDHCI */
aquila_setup_sdhci();
s3c_fimc_setname(0, "s5p-fimc");
s3c_fimc_setname(1, "s5p-fimc");
s3c_fimc_setname(2, "s5p-fimc");
/* SOUND */
aquila_sound_init();
i2c_register_board_info(AP_I2C_GPIO_BUS_5, i2c_gpio5_devs,
ARRAY_SIZE(i2c_gpio5_devs));
/* FB */
s3c_fb_set_platdata(&aquila_lcd_pdata);
platform_add_devices(aquila_devices, ARRAY_SIZE(aquila_devices));
}
MACHINE_START(AQUILA, "Aquila")
/* Maintainers:
Marek Szyprowski <m.szyprowski@samsung.com>
Kyungmin Park <kyungmin.park@samsung.com> */
.atag_offset = 0x100,
.init_irq = s5pv210_init_irq,
.map_io = aquila_map_io,
.init_machine = aquila_machine_init,
.init_time = samsung_timer_init,
.restart = s5pv210_restart,
MACHINE_END

916
arch/arm/mach-s5pv210/mach-goni.c
View File

@ -1,916 +0,0 @@
/* linux/arch/arm/mach-s5pv210/mach-goni.c
*
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
* http://www.samsung.com/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/init.h>
#include <linux/serial_core.h>
#include <linux/serial_s3c.h>
#include <linux/fb.h>
#include <linux/i2c.h>
#include <linux/i2c-gpio.h>
#include <linux/i2c/atmel_mxt_ts.h>
#include <linux/mfd/max8998.h>
#include <linux/mfd/wm8994/pdata.h>
#include <linux/regulator/fixed.h>
#include <linux/spi/spi.h>
#include <linux/spi/spi_gpio.h>
#include <linux/lcd.h>
#include <linux/gpio_keys.h>
#include <linux/input.h>
#include <linux/gpio.h>
#include <linux/mmc/host.h>
#include <linux/interrupt.h>
#include <linux/platform_data/s3c-hsotg.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/setup.h>
#include <asm/mach-types.h>
#include <video/samsung_fimd.h>
#include <mach/map.h>
#include <mach/regs-clock.h>
#include <plat/gpio-cfg.h>
#include <plat/devs.h>
#include <plat/cpu.h>
#include <plat/fb.h>
#include <linux/platform_data/i2c-s3c2410.h>
#include <plat/keypad.h>
#include <plat/sdhci.h>
#include <plat/clock.h>
#include <plat/samsung-time.h>
#include <plat/mfc.h>
#include "common.h"
/* Following are default values for UCON, ULCON and UFCON UART registers */
#define GONI_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
S3C2410_UCON_RXILEVEL | \
S3C2410_UCON_TXIRQMODE | \
S3C2410_UCON_RXIRQMODE | \
S3C2410_UCON_RXFIFO_TOI | \
S3C2443_UCON_RXERR_IRQEN)
#define GONI_ULCON_DEFAULT S3C2410_LCON_CS8
#define GONI_UFCON_DEFAULT S3C2410_UFCON_FIFOMODE
static struct s3c2410_uartcfg goni_uartcfgs[] __initdata = {
[0] = {
.hwport = 0,
.flags = 0,
.ucon = GONI_UCON_DEFAULT,
.ulcon = GONI_ULCON_DEFAULT,
.ufcon = GONI_UFCON_DEFAULT |
S5PV210_UFCON_TXTRIG256 | S5PV210_UFCON_RXTRIG256,
},
[1] = {
.hwport = 1,
.flags = 0,
.ucon = GONI_UCON_DEFAULT,
.ulcon = GONI_ULCON_DEFAULT,
.ufcon = GONI_UFCON_DEFAULT |
S5PV210_UFCON_TXTRIG64 | S5PV210_UFCON_RXTRIG64,
},
[2] = {
.hwport = 2,
.flags = 0,
.ucon = GONI_UCON_DEFAULT,
.ulcon = GONI_ULCON_DEFAULT,
.ufcon = GONI_UFCON_DEFAULT |
S5PV210_UFCON_TXTRIG16 | S5PV210_UFCON_RXTRIG16,
},
[3] = {
.hwport = 3,
.flags = 0,
.ucon = GONI_UCON_DEFAULT,
.ulcon = GONI_ULCON_DEFAULT,
.ufcon = GONI_UFCON_DEFAULT |
S5PV210_UFCON_TXTRIG16 | S5PV210_UFCON_RXTRIG16,
},
};
/* Frame Buffer */
static struct s3c_fb_pd_win goni_fb_win0 = {
.max_bpp = 32,
.default_bpp = 16,
.xres = 480,
.yres = 800,
.virtual_x = 480,
.virtual_y = 2 * 800,
};
static struct fb_videomode goni_lcd_timing = {
.left_margin = 16,
.right_margin = 16,
.upper_margin = 2,
.lower_margin = 28,
.hsync_len = 2,
.vsync_len = 1,
.xres = 480,
.yres = 800,
.refresh = 55,
};
static struct s3c_fb_platdata goni_lcd_pdata __initdata = {
.win[0] = &goni_fb_win0,
.vtiming = &goni_lcd_timing,
.vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB |
VIDCON0_CLKSEL_LCD,
.vidcon1 = VIDCON1_INV_VCLK | VIDCON1_INV_VDEN
| VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
.setup_gpio = s5pv210_fb_gpio_setup_24bpp,
};
static int lcd_power_on(struct lcd_device *ld, int enable)
{
return 1;
}
static int reset_lcd(struct lcd_device *ld)
{
static unsigned int first = 1;
int reset_gpio = -1;
reset_gpio = S5PV210_MP05(5);
if (first) {
gpio_request(reset_gpio, "MLCD_RST");
first = 0;
}
gpio_direction_output(reset_gpio, 1);
return 1;
}
static struct lcd_platform_data goni_lcd_platform_data = {
.reset = reset_lcd,
.power_on = lcd_power_on,
.lcd_enabled = 0,
.reset_delay = 120, /* 120ms */
.power_on_delay = 25, /* 25ms */
.power_off_delay = 200, /* 200ms */
};
#define LCD_BUS_NUM 3
static struct spi_board_info spi_board_info[] __initdata = {
{
.modalias = "s6e63m0",
.platform_data = &goni_lcd_platform_data,
.max_speed_hz = 1200000,
.bus_num = LCD_BUS_NUM,
.chip_select = 0,
.mode = SPI_MODE_3,
.controller_data = (void *)S5PV210_MP01(1), /* DISPLAY_CS */
},
};
static struct spi_gpio_platform_data lcd_spi_gpio_data = {
.sck = S5PV210_MP04(1), /* DISPLAY_CLK */
.mosi = S5PV210_MP04(3), /* DISPLAY_SI */
.miso = SPI_GPIO_NO_MISO,
.num_chipselect = 1,
};
static struct platform_device goni_spi_gpio = {
.name = "spi_gpio",
.id = LCD_BUS_NUM,
.dev = {
.parent = &s3c_device_fb.dev,
.platform_data = &lcd_spi_gpio_data,
},
};
/* KEYPAD */
static uint32_t keymap[] __initdata = {
/* KEY(row, col, keycode) */
KEY(0, 1, KEY_MENU), /* Send */
KEY(0, 2, KEY_BACK), /* End */
KEY(1, 1, KEY_CONFIG), /* Half shot */
KEY(1, 2, KEY_VOLUMEUP),
KEY(2, 1, KEY_CAMERA), /* Full shot */
KEY(2, 2, KEY_VOLUMEDOWN),
};
static struct matrix_keymap_data keymap_data __initdata = {
.keymap = keymap,
.keymap_size = ARRAY_SIZE(keymap),
};
static struct samsung_keypad_platdata keypad_data __initdata = {
.keymap_data = &keymap_data,
.rows = 3,
.cols = 3,
};
/* Radio */
static struct i2c_board_info i2c1_devs[] __initdata = {
{
I2C_BOARD_INFO("si470x", 0x10),
},
};
static void __init goni_radio_init(void)
{
int gpio;
gpio = S5PV210_GPJ2(4); /* XMSMDATA_4 */
gpio_request(gpio, "FM_INT");
s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(0xf));
i2c1_devs[0].irq = gpio_to_irq(gpio);
gpio = S5PV210_GPJ2(5); /* XMSMDATA_5 */
gpio_request_one(gpio, GPIOF_OUT_INIT_HIGH, "FM_RST");
}
/* TSP */
static struct mxt_platform_data qt602240_platform_data = {
.irqflags = IRQF_TRIGGER_FALLING,
};
static struct s3c2410_platform_i2c i2c2_data __initdata = {
.flags = 0,
.bus_num = 2,
.slave_addr = 0x10,
.frequency = 400 * 1000,
.sda_delay = 100,
};
static struct i2c_board_info i2c2_devs[] __initdata = {
{
I2C_BOARD_INFO("qt602240_ts", 0x4a),
.platform_data = &qt602240_platform_data,
},
};
static void __init goni_tsp_init(void)
{
int gpio;
gpio = S5PV210_GPJ1(3); /* XMSMADDR_11 */
gpio_request_one(gpio, GPIOF_OUT_INIT_HIGH, "TSP_LDO_ON");
gpio_export(gpio, 0);
gpio = S5PV210_GPJ0(5); /* XMSMADDR_5 */
gpio_request(gpio, "TSP_INT");
s5p_register_gpio_interrupt(gpio);
s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(0xf));
s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
i2c2_devs[0].irq = gpio_to_irq(gpio);
}
/* USB OTG */
static struct s3c_hsotg_plat goni_hsotg_pdata;
/* MAX8998 regulators */
#if defined(CONFIG_REGULATOR_MAX8998) || defined(CONFIG_REGULATOR_MAX8998_MODULE)
static struct regulator_consumer_supply goni_ldo3_consumers[] = {
REGULATOR_SUPPLY("vusb_a", "s3c-hsotg"),
};
static struct regulator_consumer_supply goni_ldo5_consumers[] = {
REGULATOR_SUPPLY("vmmc", "s3c-sdhci.0"),
};
static struct regulator_consumer_supply goni_ldo8_consumers[] = {
REGULATOR_SUPPLY("vusb_d", "s3c-hsotg"),
REGULATOR_SUPPLY("vdd33a_dac", "s5p-sdo"),
};
static struct regulator_consumer_supply goni_ldo11_consumers[] = {
REGULATOR_SUPPLY("vddio", "0-0030"), /* "CAM_IO_2.8V" */
};
static struct regulator_consumer_supply goni_ldo13_consumers[] = {
REGULATOR_SUPPLY("vdda", "0-0030"), /* "CAM_A_2.8V" */
};
static struct regulator_consumer_supply goni_ldo14_consumers[] = {
REGULATOR_SUPPLY("vdd_core", "0-0030"), /* "CAM_CIF_1.8V" */
};
static struct regulator_init_data goni_ldo2_data = {
.constraints = {
.name = "VALIVE_1.1V",
.min_uV = 1100000,
.max_uV = 1100000,
.apply_uV = 1,
.always_on = 1,
.state_mem = {
.enabled = 1,
},
},
};
static struct regulator_init_data goni_ldo3_data = {
.constraints = {
.name = "VUSB+MIPI_1.1V",
.min_uV = 1100000,
.max_uV = 1100000,
.apply_uV = 1,
.valid_ops_mask = REGULATOR_CHANGE_STATUS,
},
.num_consumer_supplies = ARRAY_SIZE(goni_ldo3_consumers),
.consumer_supplies = goni_ldo3_consumers,
};
static struct regulator_init_data goni_ldo4_data = {
.constraints = {
.name = "VDAC_3.3V",
.min_uV = 3300000,
.max_uV = 3300000,
.apply_uV = 1,
},
};
static struct regulator_init_data goni_ldo5_data = {
.constraints = {
.name = "VTF_2.8V",
.min_uV = 2800000,
.max_uV = 2800000,
.apply_uV = 1,
.valid_ops_mask = REGULATOR_CHANGE_STATUS,
},
.num_consumer_supplies = ARRAY_SIZE(goni_ldo5_consumers),
.consumer_supplies = goni_ldo5_consumers,
};
static struct regulator_init_data goni_ldo6_data = {
.constraints = {
.name = "VCC_3.3V",
.min_uV = 3300000,
.max_uV = 3300000,
.apply_uV = 1,
},
};
static struct regulator_init_data goni_ldo7_data = {
.constraints = {
.name = "VLCD_1.8V",
.min_uV = 1800000,
.max_uV = 1800000,
.apply_uV = 1,
.always_on = 1,
},
};
static struct regulator_init_data goni_ldo8_data = {
.constraints = {
.name = "VUSB+VADC_3.3V",
.min_uV = 3300000,
.max_uV = 3300000,
.apply_uV = 1,
.valid_ops_mask = REGULATOR_CHANGE_STATUS,
},
.num_consumer_supplies = ARRAY_SIZE(goni_ldo8_consumers),
.consumer_supplies = goni_ldo8_consumers,
};
static struct regulator_init_data goni_ldo9_data = {
.constraints = {
.name = "VCC+VCAM_2.8V",
.min_uV = 2800000,
.max_uV = 2800000,
.apply_uV = 1,
},
};
static struct regulator_init_data goni_ldo10_data = {
.constraints = {
.name = "VPLL_1.1V",
.min_uV = 1100000,
.max_uV = 1100000,
.apply_uV = 1,
.boot_on = 1,
},
};
static struct regulator_init_data goni_ldo11_data = {
.constraints = {
.name = "CAM_IO_2.8V",
.min_uV = 2800000,
.max_uV = 2800000,
.apply_uV = 1,
.valid_ops_mask = REGULATOR_CHANGE_STATUS,
},
.num_consumer_supplies = ARRAY_SIZE(goni_ldo11_consumers),
.consumer_supplies = goni_ldo11_consumers,
};
static struct regulator_init_data goni_ldo12_data = {
.constraints = {
.name = "CAM_ISP_1.2V",
.min_uV = 1200000,
.max_uV = 1200000,
.apply_uV = 1,
},
};
static struct regulator_init_data goni_ldo13_data = {
.constraints = {
.name = "CAM_A_2.8V",
.min_uV = 2800000,
.max_uV = 2800000,
.apply_uV = 1,
.valid_ops_mask = REGULATOR_CHANGE_STATUS,
},
.num_consumer_supplies = ARRAY_SIZE(goni_ldo13_consumers),
.consumer_supplies = goni_ldo13_consumers,
};
static struct regulator_init_data goni_ldo14_data = {
.constraints = {
.name = "CAM_CIF_1.8V",
.min_uV = 1800000,
.max_uV = 1800000,
.apply_uV = 1,
.valid_ops_mask = REGULATOR_CHANGE_STATUS,
},
.num_consumer_supplies = ARRAY_SIZE(goni_ldo14_consumers),
.consumer_supplies = goni_ldo14_consumers,
};
static struct regulator_init_data goni_ldo15_data = {
.constraints = {
.name = "CAM_AF_3.3V",
.min_uV = 3300000,
.max_uV = 3300000,
.apply_uV = 1,
},
};
static struct regulator_init_data goni_ldo16_data = {
.constraints = {
.name = "VMIPI_1.8V",
.min_uV = 1800000,
.max_uV = 1800000,
.apply_uV = 1,
},
};
static struct regulator_init_data goni_ldo17_data = {
.constraints = {
.name = "VCC_3.0V_LCD",
.min_uV = 3000000,
.max_uV = 3000000,
.apply_uV = 1,
.always_on = 1,
},
};
/* BUCK */
static struct regulator_consumer_supply buck1_consumer =
REGULATOR_SUPPLY("vddarm", NULL);
static struct regulator_consumer_supply buck2_consumer =
REGULATOR_SUPPLY("vddint", NULL);
static struct regulator_consumer_supply buck3_consumer =
REGULATOR_SUPPLY("vdet", "s5p-sdo");
static struct regulator_init_data goni_buck1_data = {
.constraints = {
.name = "VARM_1.2V",
.min_uV = 1200000,
.max_uV = 1200000,
.apply_uV = 1,
.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
REGULATOR_CHANGE_STATUS,
},
.num_consumer_supplies = 1,
.consumer_supplies = &buck1_consumer,
};
static struct regulator_init_data goni_buck2_data = {
.constraints = {
.name = "VINT_1.2V",
.min_uV = 1200000,
.max_uV = 1200000,
.apply_uV = 1,
.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
REGULATOR_CHANGE_STATUS,
},
.num_consumer_supplies = 1,
.consumer_supplies = &buck2_consumer,
};
static struct regulator_init_data goni_buck3_data = {
.constraints = {
.name = "VCC_1.8V",
.min_uV = 1800000,
.max_uV = 1800000,
.apply_uV = 1,
.state_mem = {
.enabled = 1,
},
},
.num_consumer_supplies = 1,
.consumer_supplies = &buck3_consumer,
};
static struct regulator_init_data goni_buck4_data = {
.constraints = {
.name = "CAM_CORE_1.2V",
.min_uV = 1200000,
.max_uV = 1200000,
.apply_uV = 1,
.always_on = 1,
},
};
static struct max8998_regulator_data goni_regulators[] = {
{ MAX8998_LDO2, &goni_ldo2_data },
{ MAX8998_LDO3, &goni_ldo3_data },
{ MAX8998_LDO4, &goni_ldo4_data },
{ MAX8998_LDO5, &goni_ldo5_data },
{ MAX8998_LDO6, &goni_ldo6_data },
{ MAX8998_LDO7, &goni_ldo7_data },
{ MAX8998_LDO8, &goni_ldo8_data },
{ MAX8998_LDO9, &goni_ldo9_data },
{ MAX8998_LDO10, &goni_ldo10_data },
{ MAX8998_LDO11, &goni_ldo11_data },
{ MAX8998_LDO12, &goni_ldo12_data },
{ MAX8998_LDO13, &goni_ldo13_data },
{ MAX8998_LDO14, &goni_ldo14_data },
{ MAX8998_LDO15, &goni_ldo15_data },
{ MAX8998_LDO16, &goni_ldo16_data },
{ MAX8998_LDO17, &goni_ldo17_data },
{ MAX8998_BUCK1, &goni_buck1_data },
{ MAX8998_BUCK2, &goni_buck2_data },
{ MAX8998_BUCK3, &goni_buck3_data },
{ MAX8998_BUCK4, &goni_buck4_data },
};
static struct max8998_platform_data goni_max8998_pdata = {
.num_regulators = ARRAY_SIZE(goni_regulators),
.regulators = goni_regulators,
.buck1_set1 = S5PV210_GPH0(3),
.buck1_set2 = S5PV210_GPH0(4),
.buck2_set3 = S5PV210_GPH0(5),
.buck1_voltage = { 1200000, 1200000, 1200000, 1200000 },
.buck2_voltage = { 1200000, 1200000 },
};
#endif
static struct regulator_consumer_supply wm8994_fixed_voltage0_supplies[] = {
REGULATOR_SUPPLY("DBVDD", "5-001a"),
REGULATOR_SUPPLY("AVDD2", "5-001a"),
REGULATOR_SUPPLY("CPVDD", "5-001a"),
};
static struct regulator_consumer_supply wm8994_fixed_voltage1_supplies[] = {
REGULATOR_SUPPLY("SPKVDD1", "5-001a"),
REGULATOR_SUPPLY("SPKVDD2", "5-001a"),
};
static struct regulator_init_data wm8994_fixed_voltage0_init_data = {
.constraints = {
.always_on = 1,
},
.num_consumer_supplies = ARRAY_SIZE(wm8994_fixed_voltage0_supplies),
.consumer_supplies = wm8994_fixed_voltage0_supplies,
};
static struct regulator_init_data wm8994_fixed_voltage1_init_data = {
.constraints = {
.always_on = 1,
},
.num_consumer_supplies = ARRAY_SIZE(wm8994_fixed_voltage1_supplies),
.consumer_supplies = wm8994_fixed_voltage1_supplies,
};
static struct fixed_voltage_config wm8994_fixed_voltage0_config = {
.supply_name = "VCC_1.8V_PDA",
.microvolts = 1800000,
.gpio = -EINVAL,
.init_data = &wm8994_fixed_voltage0_init_data,
};
static struct fixed_voltage_config wm8994_fixed_voltage1_config = {
.supply_name = "V_BAT",
.microvolts = 3700000,
.gpio = -EINVAL,
.init_data = &wm8994_fixed_voltage1_init_data,
};
static struct platform_device wm8994_fixed_voltage0 = {
.name = "reg-fixed-voltage",
.id = 0,
.dev = {
.platform_data = &wm8994_fixed_voltage0_config,
},
};
static struct platform_device wm8994_fixed_voltage1 = {
.name = "reg-fixed-voltage",
.id = 1,
.dev = {
.platform_data = &wm8994_fixed_voltage1_config,
},
};
static struct regulator_consumer_supply wm8994_avdd1_supply =
REGULATOR_SUPPLY("AVDD1", "5-001a");
static struct regulator_consumer_supply wm8994_dcvdd_supply =
REGULATOR_SUPPLY("DCVDD", "5-001a");
static struct regulator_init_data wm8994_ldo1_data = {
.constraints = {
.name = "AVDD1_3.0V",
.valid_ops_mask = REGULATOR_CHANGE_STATUS,
},
.num_consumer_supplies = 1,
.consumer_supplies = &wm8994_avdd1_supply,
};
static struct regulator_init_data wm8994_ldo2_data = {
.constraints = {
.name = "DCVDD_1.0V",
},
.num_consumer_supplies = 1,
.consumer_supplies = &wm8994_dcvdd_supply,
};
static struct wm8994_pdata wm8994_platform_data = {
/* configure gpio1 function: 0x0001(Logic level input/output) */
.gpio_defaults[0] = 0x0001,
/* configure gpio3/4/5/7 function for AIF2 voice */
.gpio_defaults[2] = 0x8100,
.gpio_defaults[3] = 0x8100,
.gpio_defaults[4] = 0x8100,
.gpio_defaults[6] = 0x0100,
/* configure gpio8/9/10/11 function for AIF3 BT */
.gpio_defaults[7] = 0x8100,
.gpio_defaults[8] = 0x0100,
.gpio_defaults[9] = 0x0100,
.gpio_defaults[10] = 0x0100,
.ldo[0] = { S5PV210_MP03(6), &wm8994_ldo1_data }, /* XM0FRNB_2 */
.ldo[1] = { 0, &wm8994_ldo2_data },
};
/* GPIO I2C PMIC */
#define AP_I2C_GPIO_PMIC_BUS_4 4
static struct i2c_gpio_platform_data goni_i2c_gpio_pmic_data = {
.sda_pin = S5PV210_GPJ4(0), /* XMSMCSN */
.scl_pin = S5PV210_GPJ4(3), /* XMSMIRQN */
};
static struct platform_device goni_i2c_gpio_pmic = {
.name = "i2c-gpio",
.id = AP_I2C_GPIO_PMIC_BUS_4,
.dev = {
.platform_data = &goni_i2c_gpio_pmic_data,
},
};
static struct i2c_board_info i2c_gpio_pmic_devs[] __initdata = {
#if defined(CONFIG_REGULATOR_MAX8998) || defined(CONFIG_REGULATOR_MAX8998_MODULE)
{
/* 0xCC when SRAD = 0 */
I2C_BOARD_INFO("max8998", 0xCC >> 1),
.platform_data = &goni_max8998_pdata,
},
#endif
};
/* GPIO I2C AP 1.8V */
#define AP_I2C_GPIO_BUS_5 5
static struct i2c_gpio_platform_data goni_i2c_gpio5_data = {
.sda_pin = S5PV210_MP05(3), /* XM0ADDR_11 */
.scl_pin = S5PV210_MP05(2), /* XM0ADDR_10 */
};
static struct platform_device goni_i2c_gpio5 = {
.name = "i2c-gpio",
.id = AP_I2C_GPIO_BUS_5,
.dev = {
.platform_data = &goni_i2c_gpio5_data,
},
};
static struct i2c_board_info i2c_gpio5_devs[] __initdata = {
{
/* CS/ADDR = low 0x34 (FYI: high = 0x36) */
I2C_BOARD_INFO("wm8994", 0x1a),
.platform_data = &wm8994_platform_data,
},
};
/* PMIC Power button */
static struct gpio_keys_button goni_gpio_keys_table[] = {
{
.code = KEY_POWER,
.gpio = S5PV210_GPH2(6),
.desc = "gpio-keys: KEY_POWER",
.type = EV_KEY,
.active_low = 1,
.wakeup = 1,
.debounce_interval = 1,
},
};
static struct gpio_keys_platform_data goni_gpio_keys_data = {
.buttons = goni_gpio_keys_table,
.nbuttons = ARRAY_SIZE(goni_gpio_keys_table),
};
static struct platform_device goni_device_gpiokeys = {
.name = "gpio-keys",
.dev = {
.platform_data = &goni_gpio_keys_data,
},
};
static void __init goni_pmic_init(void)
{
/* AP_PMIC_IRQ: EINT7 */
s3c_gpio_cfgpin(S5PV210_GPH0(7), S3C_GPIO_SFN(0xf));
s3c_gpio_setpull(S5PV210_GPH0(7), S3C_GPIO_PULL_UP);
/* nPower: EINT22 */
s3c_gpio_cfgpin(S5PV210_GPH2(6), S3C_GPIO_SFN(0xf));
s3c_gpio_setpull(S5PV210_GPH2(6), S3C_GPIO_PULL_UP);
}
/* MoviNAND */
static struct s3c_sdhci_platdata goni_hsmmc0_data __initdata = {
.max_width = 4,
.cd_type = S3C_SDHCI_CD_PERMANENT,
};
/* Wireless LAN */
static struct s3c_sdhci_platdata goni_hsmmc1_data __initdata = {
.max_width = 4,
.cd_type = S3C_SDHCI_CD_EXTERNAL,
/* ext_cd_{init,cleanup} callbacks will be added later */
};
/* External Flash */
#define GONI_EXT_FLASH_EN S5PV210_MP05(4)
#define GONI_EXT_FLASH_CD S5PV210_GPH3(4)
static struct s3c_sdhci_platdata goni_hsmmc2_data __initdata = {
.max_width = 4,
.cd_type = S3C_SDHCI_CD_GPIO,
.ext_cd_gpio = GONI_EXT_FLASH_CD,
.ext_cd_gpio_invert = 1,
};
static struct regulator_consumer_supply mmc2_supplies[] = {
REGULATOR_SUPPLY("vmmc", "s3c-sdhci.2"),
};
static struct regulator_init_data mmc2_fixed_voltage_init_data = {
.constraints = {
.name = "V_TF_2.8V",
.valid_ops_mask = REGULATOR_CHANGE_STATUS,
},
.num_consumer_supplies = ARRAY_SIZE(mmc2_supplies),
.consumer_supplies = mmc2_supplies,
};
static struct fixed_voltage_config mmc2_fixed_voltage_config = {
.supply_name = "EXT_FLASH_EN",
.microvolts = 2800000,
.gpio = GONI_EXT_FLASH_EN,
.enable_high = true,
.init_data = &mmc2_fixed_voltage_init_data,
};
static struct platform_device mmc2_fixed_voltage = {
.name = "reg-fixed-voltage",
.id = 2,
.dev = {
.platform_data = &mmc2_fixed_voltage_config,
},
};
static void goni_setup_sdhci(void)
{
s3c_sdhci0_set_platdata(&goni_hsmmc0_data);
s3c_sdhci1_set_platdata(&goni_hsmmc1_data);
s3c_sdhci2_set_platdata(&goni_hsmmc2_data);
};
/* Audio device */
static struct platform_device goni_device_audio = {
.name = "smdk-audio",
.id = -1,
};
static struct platform_device *goni_devices[] __initdata = {
&s3c_device_fb,
&s5p_device_onenand,
&goni_spi_gpio,
&goni_i2c_gpio_pmic,
&goni_i2c_gpio5,
&goni_device_audio,
&mmc2_fixed_voltage,
&goni_device_gpiokeys,
&s5p_device_mfc,
&s5p_device_mfc_l,
&s5p_device_mfc_r,
&s5p_device_mixer,
&s5p_device_sdo,
&s3c_device_i2c0,
&s3c_device_hsmmc0,
&s3c_device_hsmmc1,
&s3c_device_hsmmc2,
&s5pv210_device_iis0,
&s3c_device_usb_hsotg,
&samsung_device_keypad,
&s3c_device_i2c1,
&s3c_device_i2c2,
&wm8994_fixed_voltage0,
&wm8994_fixed_voltage1,
};
static void __init goni_sound_init(void)
{
/* Ths main clock of WM8994 codec uses the output of CLKOUT pin.
* The CLKOUT[9:8] set to 0x3(XUSBXTI) of 0xE010E000(OTHERS)
* because it needs 24MHz clock to operate WM8994 codec.
*/
__raw_writel(__raw_readl(S5P_OTHERS) | (0x3 << 8), S5P_OTHERS);
}
static void __init goni_map_io(void)
{
s5pv210_init_io(NULL, 0);
s3c24xx_init_clocks(clk_xusbxti.rate);
s3c24xx_init_uarts(goni_uartcfgs, ARRAY_SIZE(goni_uartcfgs));
samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
}
static void __init goni_reserve(void)
{
s5p_mfc_reserve_mem(0x43000000, 8 << 20, 0x51000000, 8 << 20);
}
static void __init goni_machine_init(void)
{
/* Radio: call before I2C 1 registeration */
goni_radio_init();
/* I2C0 */
s3c_i2c0_set_platdata(NULL);
/* I2C1 */
s3c_i2c1_set_platdata(NULL);
i2c_register_board_info(1, i2c1_devs, ARRAY_SIZE(i2c1_devs));
/* TSP: call before I2C 2 registeration */
goni_tsp_init();
/* I2C2 */
s3c_i2c2_set_platdata(&i2c2_data);
i2c_register_board_info(2, i2c2_devs, ARRAY_SIZE(i2c2_devs));
/* PMIC */
goni_pmic_init();
i2c_register_board_info(AP_I2C_GPIO_PMIC_BUS_4, i2c_gpio_pmic_devs,
ARRAY_SIZE(i2c_gpio_pmic_devs));
/* SDHCI */
goni_setup_sdhci();
/* SOUND */
goni_sound_init();
i2c_register_board_info(AP_I2C_GPIO_BUS_5, i2c_gpio5_devs,
ARRAY_SIZE(i2c_gpio5_devs));
/* FB */
s3c_fb_set_platdata(&goni_lcd_pdata);
s3c_hsotg_set_platdata(&goni_hsotg_pdata);
/* SPI */
spi_register_board_info(spi_board_info, ARRAY_SIZE(spi_board_info));
/* KEYPAD */
samsung_keypad_set_platdata(&keypad_data);
platform_add_devices(goni_devices, ARRAY_SIZE(goni_devices));
}
MACHINE_START(GONI, "GONI")
/* Maintainers: Kyungmin Park <kyungmin.park@samsung.com> */
.atag_offset = 0x100,
.init_irq = s5pv210_init_irq,
.map_io = goni_map_io,
.init_machine = goni_machine_init,
.init_time = samsung_timer_init,
.reserve = &goni_reserve,
.restart = s5pv210_restart,
MACHINE_END

159
arch/arm/mach-s5pv210/mach-smdkc110.c
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@ -1,159 +0,0 @@
/* linux/arch/arm/mach-s5pv210/mach-smdkc110.c
*
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
* http://www.samsung.com/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/init.h>
#include <linux/serial_core.h>
#include <linux/serial_s3c.h>
#include <linux/i2c.h>
#include <linux/device.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/setup.h>
#include <asm/mach-types.h>
#include <mach/map.h>
#include <mach/regs-clock.h>
#include <plat/devs.h>
#include <plat/cpu.h>
#include <linux/platform_data/ata-samsung_cf.h>
#include <linux/platform_data/i2c-s3c2410.h>
#include <plat/pm.h>
#include <plat/samsung-time.h>
#include <plat/mfc.h>
#include "common.h"
/* Following are default values for UCON, ULCON and UFCON UART registers */
#define SMDKC110_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
S3C2410_UCON_RXILEVEL | \
S3C2410_UCON_TXIRQMODE | \
S3C2410_UCON_RXIRQMODE | \
S3C2410_UCON_RXFIFO_TOI | \
S3C2443_UCON_RXERR_IRQEN)
#define SMDKC110_ULCON_DEFAULT S3C2410_LCON_CS8
#define SMDKC110_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \
S5PV210_UFCON_TXTRIG4 | \
S5PV210_UFCON_RXTRIG4)
static struct s3c2410_uartcfg smdkv210_uartcfgs[] __initdata = {
[0] = {
.hwport = 0,
.flags = 0,
.ucon = SMDKC110_UCON_DEFAULT,
.ulcon = SMDKC110_ULCON_DEFAULT,
.ufcon = SMDKC110_UFCON_DEFAULT,
},
[1] = {
.hwport = 1,
.flags = 0,
.ucon = SMDKC110_UCON_DEFAULT,
.ulcon = SMDKC110_ULCON_DEFAULT,
.ufcon = SMDKC110_UFCON_DEFAULT,
},
[2] = {
.hwport = 2,
.flags = 0,
.ucon = SMDKC110_UCON_DEFAULT,
.ulcon = SMDKC110_ULCON_DEFAULT,
.ufcon = SMDKC110_UFCON_DEFAULT,
},
[3] = {
.hwport = 3,
.flags = 0,
.ucon = SMDKC110_UCON_DEFAULT,
.ulcon = SMDKC110_ULCON_DEFAULT,
.ufcon = SMDKC110_UFCON_DEFAULT,
},
};
static struct s3c_ide_platdata smdkc110_ide_pdata __initdata = {
.setup_gpio = s5pv210_ide_setup_gpio,
};
static struct platform_device *smdkc110_devices[] __initdata = {
&s5pv210_device_iis0,
&s5pv210_device_ac97,
&s5pv210_device_spdif,
&s3c_device_cfcon,
&s3c_device_i2c0,
&s3c_device_i2c1,
&s3c_device_i2c2,
&s3c_device_rtc,
&s3c_device_wdt,
&s5p_device_fimc0,
&s5p_device_fimc1,
&s5p_device_fimc2,
&s5p_device_fimc_md,
&s5p_device_mfc,
&s5p_device_mfc_l,
&s5p_device_mfc_r,
};
static struct i2c_board_info smdkc110_i2c_devs0[] __initdata = {
{ I2C_BOARD_INFO("24c08", 0x50), }, /* Samsung S524AD0XD1 */
{ I2C_BOARD_INFO("wm8580", 0x1b), },
};
static struct i2c_board_info smdkc110_i2c_devs1[] __initdata = {
/* To Be Updated */
};
static struct i2c_board_info smdkc110_i2c_devs2[] __initdata = {
/* To Be Updated */
};
static void __init smdkc110_map_io(void)
{
s5pv210_init_io(NULL, 0);
s3c24xx_init_clocks(24000000);
s3c24xx_init_uarts(smdkv210_uartcfgs, ARRAY_SIZE(smdkv210_uartcfgs));
samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
}
static void __init smdkc110_reserve(void)
{
s5p_mfc_reserve_mem(0x43000000, 8 << 20, 0x51000000, 8 << 20);
}
static void __init smdkc110_machine_init(void)
{
s3c_pm_init();
s3c_i2c0_set_platdata(NULL);
s3c_i2c1_set_platdata(NULL);
s3c_i2c2_set_platdata(NULL);
i2c_register_board_info(0, smdkc110_i2c_devs0,
ARRAY_SIZE(smdkc110_i2c_devs0));
i2c_register_board_info(1, smdkc110_i2c_devs1,
ARRAY_SIZE(smdkc110_i2c_devs1));
i2c_register_board_info(2, smdkc110_i2c_devs2,
ARRAY_SIZE(smdkc110_i2c_devs2));
s3c_ide_set_platdata(&smdkc110_ide_pdata);
platform_add_devices(smdkc110_devices, ARRAY_SIZE(smdkc110_devices));
}
MACHINE_START(SMDKC110, "SMDKC110")
/* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
.atag_offset = 0x100,
.init_irq = s5pv210_init_irq,
.map_io = smdkc110_map_io,
.init_machine = smdkc110_machine_init,
.init_time = samsung_timer_init,
.restart = s5pv210_restart,
.reserve = &smdkc110_reserve,
MACHINE_END

337
arch/arm/mach-s5pv210/mach-smdkv210.c
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/* linux/arch/arm/mach-s5pv210/mach-smdkv210.c
*
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
* http://www.samsung.com/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/i2c.h>
#include <linux/init.h>
#include <linux/serial_core.h>
#include <linux/serial_s3c.h>
#include <linux/device.h>
#include <linux/dm9000.h>
#include <linux/fb.h>
#include <linux/gpio.h>
#include <linux/delay.h>
#include <linux/pwm_backlight.h>
#include <linux/platform_data/s3c-hsotg.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/setup.h>
#include <asm/mach-types.h>
#include <video/platform_lcd.h>
#include <video/samsung_fimd.h>
#include <mach/map.h>
#include <mach/regs-clock.h>
#include <plat/regs-srom.h>
#include <plat/gpio-cfg.h>
#include <plat/devs.h>
#include <plat/cpu.h>
#include <plat/adc.h>
#include <linux/platform_data/touchscreen-s3c2410.h>
#include <linux/platform_data/ata-samsung_cf.h>
#include <linux/platform_data/i2c-s3c2410.h>
#include <plat/keypad.h>
#include <plat/pm.h>
#include <plat/fb.h>
#include <plat/samsung-time.h>
#include <plat/backlight.h>
#include <plat/mfc.h>
#include <plat/clock.h>
#include "common.h"
/* Following are default values for UCON, ULCON and UFCON UART registers */
#define SMDKV210_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
S3C2410_UCON_RXILEVEL | \
S3C2410_UCON_TXIRQMODE | \
S3C2410_UCON_RXIRQMODE | \
S3C2410_UCON_RXFIFO_TOI | \
S3C2443_UCON_RXERR_IRQEN)
#define SMDKV210_ULCON_DEFAULT S3C2410_LCON_CS8
#define SMDKV210_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \
S5PV210_UFCON_TXTRIG4 | \
S5PV210_UFCON_RXTRIG4)
static struct s3c2410_uartcfg smdkv210_uartcfgs[] __initdata = {
[0] = {
.hwport = 0,
.flags = 0,
.ucon = SMDKV210_UCON_DEFAULT,
.ulcon = SMDKV210_ULCON_DEFAULT,
.ufcon = SMDKV210_UFCON_DEFAULT,
},
[1] = {
.hwport = 1,
.flags = 0,
.ucon = SMDKV210_UCON_DEFAULT,
.ulcon = SMDKV210_ULCON_DEFAULT,
.ufcon = SMDKV210_UFCON_DEFAULT,
},
[2] = {
.hwport = 2,
.flags = 0,
.ucon = SMDKV210_UCON_DEFAULT,
.ulcon = SMDKV210_ULCON_DEFAULT,
.ufcon = SMDKV210_UFCON_DEFAULT,
},
[3] = {
.hwport = 3,
.flags = 0,
.ucon = SMDKV210_UCON_DEFAULT,
.ulcon = SMDKV210_ULCON_DEFAULT,
.ufcon = SMDKV210_UFCON_DEFAULT,
},
};
static struct s3c_ide_platdata smdkv210_ide_pdata __initdata = {
.setup_gpio = s5pv210_ide_setup_gpio,
};
static uint32_t smdkv210_keymap[] __initdata = {
/* KEY(row, col, keycode) */
KEY(0, 3, KEY_1), KEY(0, 4, KEY_2), KEY(0, 5, KEY_3),
KEY(0, 6, KEY_4), KEY(0, 7, KEY_5),
KEY(1, 3, KEY_A), KEY(1, 4, KEY_B), KEY(1, 5, KEY_C),
KEY(1, 6, KEY_D), KEY(1, 7, KEY_E)
};
static struct matrix_keymap_data smdkv210_keymap_data __initdata = {
.keymap = smdkv210_keymap,
.keymap_size = ARRAY_SIZE(smdkv210_keymap),
};
static struct samsung_keypad_platdata smdkv210_keypad_data __initdata = {
.keymap_data = &smdkv210_keymap_data,
.rows = 8,
.cols = 8,
};
static struct resource smdkv210_dm9000_resources[] = {
[0] = DEFINE_RES_MEM(S5PV210_PA_SROM_BANK5, 1),
[1] = DEFINE_RES_MEM(S5PV210_PA_SROM_BANK5 + 2, 1),
[2] = DEFINE_RES_NAMED(IRQ_EINT(9), 1, NULL, IORESOURCE_IRQ \
| IORESOURCE_IRQ_HIGHLEVEL),
};
static struct dm9000_plat_data smdkv210_dm9000_platdata = {
.flags = DM9000_PLATF_16BITONLY | DM9000_PLATF_NO_EEPROM,
.dev_addr = { 0x00, 0x09, 0xc0, 0xff, 0xec, 0x48 },
};
static struct platform_device smdkv210_dm9000 = {
.name = "dm9000",
.id = -1,
.num_resources = ARRAY_SIZE(smdkv210_dm9000_resources),
.resource = smdkv210_dm9000_resources,
.dev = {
.platform_data = &smdkv210_dm9000_platdata,
},
};
static void smdkv210_lte480wv_set_power(struct plat_lcd_data *pd,
unsigned int power)
{
if (power) {
#if !defined(CONFIG_BACKLIGHT_PWM)
gpio_request_one(S5PV210_GPD0(3), GPIOF_OUT_INIT_HIGH, "GPD0");
gpio_free(S5PV210_GPD0(3));
#endif
/* fire nRESET on power up */
gpio_request_one(S5PV210_GPH0(6), GPIOF_OUT_INIT_HIGH, "GPH0");
gpio_set_value(S5PV210_GPH0(6), 0);
mdelay(10);
gpio_set_value(S5PV210_GPH0(6), 1);
mdelay(10);
gpio_free(S5PV210_GPH0(6));
} else {
#if !defined(CONFIG_BACKLIGHT_PWM)
gpio_request_one(S5PV210_GPD0(3), GPIOF_OUT_INIT_LOW, "GPD0");
gpio_free(S5PV210_GPD0(3));
#endif
}
}
static struct plat_lcd_data smdkv210_lcd_lte480wv_data = {
.set_power = smdkv210_lte480wv_set_power,
};
static struct platform_device smdkv210_lcd_lte480wv = {
.name = "platform-lcd",
.dev.parent = &s3c_device_fb.dev,
.dev.platform_data = &smdkv210_lcd_lte480wv_data,
};
static struct s3c_fb_pd_win smdkv210_fb_win0 = {
.max_bpp = 32,
.default_bpp = 24,
.xres = 800,
.yres = 480,
};
static struct fb_videomode smdkv210_lcd_timing = {
.left_margin = 13,
.right_margin = 8,
.upper_margin = 7,
.lower_margin = 5,
.hsync_len = 3,
.vsync_len = 1,
.xres = 800,
.yres = 480,
};
static struct s3c_fb_platdata smdkv210_lcd0_pdata __initdata = {
.win[0] = &smdkv210_fb_win0,
.vtiming = &smdkv210_lcd_timing,
.vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
.vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
.setup_gpio = s5pv210_fb_gpio_setup_24bpp,
};
/* USB OTG */
static struct s3c_hsotg_plat smdkv210_hsotg_pdata;
static struct platform_device *smdkv210_devices[] __initdata = {
&s3c_device_adc,
&s3c_device_cfcon,
&s3c_device_fb,
&s3c_device_hsmmc0,
&s3c_device_hsmmc1,
&s3c_device_hsmmc2,
&s3c_device_hsmmc3,
&s3c_device_i2c0,
&s3c_device_i2c1,
&s3c_device_i2c2,
&samsung_device_pwm,
&s3c_device_rtc,
&s3c_device_ts,
&s3c_device_usb_hsotg,
&s3c_device_wdt,
&s5p_device_fimc0,
&s5p_device_fimc1,
&s5p_device_fimc2,
&s5p_device_fimc_md,
&s5p_device_jpeg,
&s5p_device_mfc,
&s5p_device_mfc_l,
&s5p_device_mfc_r,
&s5pv210_device_ac97,
&s5pv210_device_iis0,
&s5pv210_device_spdif,
&samsung_asoc_idma,
&samsung_device_keypad,
&smdkv210_dm9000,
&smdkv210_lcd_lte480wv,
};
static void __init smdkv210_dm9000_init(void)
{
unsigned int tmp;
gpio_request(S5PV210_MP01(5), "nCS5");
s3c_gpio_cfgpin(S5PV210_MP01(5), S3C_GPIO_SFN(2));
gpio_free(S5PV210_MP01(5));
tmp = (5 << S5P_SROM_BCX__TACC__SHIFT);
__raw_writel(tmp, S5P_SROM_BC5);
tmp = __raw_readl(S5P_SROM_BW);
tmp &= (S5P_SROM_BW__CS_MASK << S5P_SROM_BW__NCS5__SHIFT);
tmp |= (1 << S5P_SROM_BW__NCS5__SHIFT);
__raw_writel(tmp, S5P_SROM_BW);
}
static struct i2c_board_info smdkv210_i2c_devs0[] __initdata = {
{ I2C_BOARD_INFO("24c08", 0x50), }, /* Samsung S524AD0XD1 */
{ I2C_BOARD_INFO("wm8580", 0x1b), },
};
static struct i2c_board_info smdkv210_i2c_devs1[] __initdata = {
/* To Be Updated */
};
static struct i2c_board_info smdkv210_i2c_devs2[] __initdata = {
/* To Be Updated */
};
/* LCD Backlight data */
static struct samsung_bl_gpio_info smdkv210_bl_gpio_info = {
.no = S5PV210_GPD0(3),
.func = S3C_GPIO_SFN(2),
};
static struct platform_pwm_backlight_data smdkv210_bl_data = {
.pwm_id = 3,
.pwm_period_ns = 1000,
.enable_gpio = -1,
};
static void __init smdkv210_map_io(void)
{
s5pv210_init_io(NULL, 0);
s3c24xx_init_clocks(clk_xusbxti.rate);
s3c24xx_init_uarts(smdkv210_uartcfgs, ARRAY_SIZE(smdkv210_uartcfgs));
samsung_set_timer_source(SAMSUNG_PWM2, SAMSUNG_PWM4);
}
static void __init smdkv210_reserve(void)
{
s5p_mfc_reserve_mem(0x43000000, 8 << 20, 0x51000000, 8 << 20);
}
static void __init smdkv210_machine_init(void)
{
s3c_pm_init();
smdkv210_dm9000_init();
samsung_keypad_set_platdata(&smdkv210_keypad_data);
s3c24xx_ts_set_platdata(NULL);
s3c_i2c0_set_platdata(NULL);
s3c_i2c1_set_platdata(NULL);
s3c_i2c2_set_platdata(NULL);
i2c_register_board_info(0, smdkv210_i2c_devs0,
ARRAY_SIZE(smdkv210_i2c_devs0));
i2c_register_board_info(1, smdkv210_i2c_devs1,
ARRAY_SIZE(smdkv210_i2c_devs1));
i2c_register_board_info(2, smdkv210_i2c_devs2,
ARRAY_SIZE(smdkv210_i2c_devs2));
s3c_ide_set_platdata(&smdkv210_ide_pdata);
s3c_fb_set_platdata(&smdkv210_lcd0_pdata);
s3c_hsotg_set_platdata(&smdkv210_hsotg_pdata);
platform_add_devices(smdkv210_devices, ARRAY_SIZE(smdkv210_devices));
samsung_bl_set(&smdkv210_bl_gpio_info, &smdkv210_bl_data);
}
MACHINE_START(SMDKV210, "SMDKV210")
/* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
.atag_offset = 0x100,
.init_irq = s5pv210_init_irq,
.map_io = smdkv210_map_io,
.init_machine = smdkv210_machine_init,
.init_time = samsung_timer_init,
.restart = s5pv210_restart,
.reserve = &smdkv210_reserve,
MACHINE_END

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arch/arm/mach-s5pv210/mach-torbreck.c
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/* linux/arch/arm/mach-s5pv210/mach-torbreck.c
*
* Copyright (c) 2010 aESOP Community
* http://www.aesop.or.kr/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/i2c.h>
#include <linux/init.h>
#include <linux/serial_core.h>
#include <linux/serial_s3c.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/setup.h>
#include <asm/mach-types.h>
#include <mach/map.h>
#include <mach/regs-clock.h>
#include <plat/devs.h>
#include <plat/cpu.h>
#include <linux/platform_data/i2c-s3c2410.h>
#include <plat/samsung-time.h>
#include "common.h"
/* Following are default values for UCON, ULCON and UFCON UART registers */
#define TORBRECK_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
S3C2410_UCON_RXILEVEL | \
S3C2410_UCON_TXIRQMODE | \
S3C2410_UCON_RXIRQMODE | \
S3C2410_UCON_RXFIFO_TOI | \
S3C2443_UCON_RXERR_IRQEN)
#define TORBRECK_ULCON_DEFAULT S3C2410_LCON_CS8
#define TORBRECK_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \
S5PV210_UFCON_TXTRIG4 | \
S5PV210_UFCON_RXTRIG4)
static struct s3c2410_uartcfg torbreck_uartcfgs[] __initdata = {
[0] = {
.hwport = 0,
.flags = 0,
.ucon = TORBRECK_UCON_DEFAULT,
.ulcon = TORBRECK_ULCON_DEFAULT,
.ufcon = TORBRECK_UFCON_DEFAULT,
},
[1] = {
.hwport = 1,
.flags = 0,
.ucon = TORBRECK_UCON_DEFAULT,
.ulcon = TORBRECK_ULCON_DEFAULT,
.ufcon = TORBRECK_UFCON_DEFAULT,
},
[2] = {
.hwport = 2,
.flags = 0,
.ucon = TORBRECK_UCON_DEFAULT,
.ulcon = TORBRECK_ULCON_DEFAULT,
.ufcon = TORBRECK_UFCON_DEFAULT,
},
[3] = {
.hwport = 3,
.flags = 0,
.ucon = TORBRECK_UCON_DEFAULT,
.ulcon = TORBRECK_ULCON_DEFAULT,
.ufcon = TORBRECK_UFCON_DEFAULT,
},
};
static struct platform_device *torbreck_devices[] __initdata = {
&s5pv210_device_iis0,
&s3c_device_cfcon,
&s3c_device_hsmmc0,
&s3c_device_hsmmc1,
&s3c_device_hsmmc2,
&s3c_device_hsmmc3,
&s3c_device_i2c0,
&s3c_device_i2c1,
&s3c_device_i2c2,
&s3c_device_rtc,
&s3c_device_wdt,
};
static struct i2c_board_info torbreck_i2c_devs0[] __initdata = {
/* To Be Updated */
};
static struct i2c_board_info torbreck_i2c_devs1[] __initdata = {
/* To Be Updated */
};
static struct i2c_board_info torbreck_i2c_devs2[] __initdata = {
/* To Be Updated */
};
static void __init torbreck_map_io(void)
{
s5pv210_init_io(NULL, 0);
s3c24xx_init_clocks(24000000);
s3c24xx_init_uarts(torbreck_uartcfgs, ARRAY_SIZE(torbreck_uartcfgs));
samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
}
static void __init torbreck_machine_init(void)
{
s3c_i2c0_set_platdata(NULL);
s3c_i2c1_set_platdata(NULL);
s3c_i2c2_set_platdata(NULL);
i2c_register_board_info(0, torbreck_i2c_devs0,
ARRAY_SIZE(torbreck_i2c_devs0));
i2c_register_board_info(1, torbreck_i2c_devs1,
ARRAY_SIZE(torbreck_i2c_devs1));
i2c_register_board_info(2, torbreck_i2c_devs2,
ARRAY_SIZE(torbreck_i2c_devs2));
platform_add_devices(torbreck_devices, ARRAY_SIZE(torbreck_devices));
}
MACHINE_START(TORBRECK, "TORBRECK")
/* Maintainer: Hyunchul Ko <ghcstop@gmail.com> */
.atag_offset = 0x100,
.init_irq = s5pv210_init_irq,
.map_io = torbreck_map_io,
.init_machine = torbreck_machine_init,
.init_time = samsung_timer_init,
.restart = s5pv210_restart,
MACHINE_END

151
arch/arm/mach-s5pv210/pm.c
View File

@ -1,6 +1,6 @@
/* linux/arch/arm/mach-s5pv210/pm.c
*
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
* Copyright (c) 2010-2014 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* S5PV210 - Power Management support
@ -19,65 +19,28 @@
#include <linux/syscore_ops.h>
#include <linux/io.h>
#include <plat/cpu.h>
#include <plat/pm.h>
#include <asm/cacheflush.h>
#include <asm/suspend.h>
#include <plat/pm-common.h>
#include <mach/regs-irq.h>
#include <mach/regs-clock.h>
#include "common.h"
static struct sleep_save s5pv210_core_save[] = {
/* Clock source */
SAVE_ITEM(S5P_CLK_SRC0),
SAVE_ITEM(S5P_CLK_SRC1),
SAVE_ITEM(S5P_CLK_SRC2),
SAVE_ITEM(S5P_CLK_SRC3),
SAVE_ITEM(S5P_CLK_SRC4),
SAVE_ITEM(S5P_CLK_SRC5),
SAVE_ITEM(S5P_CLK_SRC6),
/* Clock source Mask */
SAVE_ITEM(S5P_CLK_SRC_MASK0),
SAVE_ITEM(S5P_CLK_SRC_MASK1),
/* Clock Divider */
SAVE_ITEM(S5P_CLK_DIV0),
SAVE_ITEM(S5P_CLK_DIV1),
SAVE_ITEM(S5P_CLK_DIV2),
SAVE_ITEM(S5P_CLK_DIV3),
SAVE_ITEM(S5P_CLK_DIV4),
SAVE_ITEM(S5P_CLK_DIV5),
SAVE_ITEM(S5P_CLK_DIV6),
SAVE_ITEM(S5P_CLK_DIV7),
/* Clock Main Gate */
SAVE_ITEM(S5P_CLKGATE_MAIN0),
SAVE_ITEM(S5P_CLKGATE_MAIN1),
SAVE_ITEM(S5P_CLKGATE_MAIN2),
/* Clock source Peri Gate */
SAVE_ITEM(S5P_CLKGATE_PERI0),
SAVE_ITEM(S5P_CLKGATE_PERI1),
/* Clock source SCLK Gate */
SAVE_ITEM(S5P_CLKGATE_SCLK0),
SAVE_ITEM(S5P_CLKGATE_SCLK1),
/* Clock IP Clock gate */
SAVE_ITEM(S5P_CLKGATE_IP0),
SAVE_ITEM(S5P_CLKGATE_IP1),
SAVE_ITEM(S5P_CLKGATE_IP2),
SAVE_ITEM(S5P_CLKGATE_IP3),
SAVE_ITEM(S5P_CLKGATE_IP4),
/* Clock Blcok and Bus gate */
SAVE_ITEM(S5P_CLKGATE_BLOCK),
SAVE_ITEM(S5P_CLKGATE_BUS0),
/* Clock ETC */
SAVE_ITEM(S5P_CLK_OUT),
SAVE_ITEM(S5P_MDNIE_SEL),
};
/*
* VIC wake-up support (TODO)
*/
static u32 s5pv210_irqwake_intmask = 0xffffffff;
/*
* Suspend helpers.
*/
static int s5pv210_cpu_suspend(unsigned long arg)
{
unsigned long tmp;
@ -102,8 +65,12 @@ static void s5pv210_pm_prepare(void)
{
unsigned int tmp;
/* Set wake-up mask registers */
__raw_writel(exynos_get_eint_wake_mask(), S5P_EINT_WAKEUP_MASK);
__raw_writel(s5pv210_irqwake_intmask, S5P_WAKEUP_MASK);
/* ensure at least INFORM0 has the resume address */
__raw_writel(virt_to_phys(s3c_cpu_resume), S5P_INFORM0);
__raw_writel(virt_to_phys(s5pv210_cpu_resume), S5P_INFORM0);
tmp = __raw_readl(S5P_SLEEP_CFG);
tmp &= ~(S5P_SLEEP_CFG_OSC_EN | S5P_SLEEP_CFG_USBOSC_EN);
@ -123,26 +90,70 @@ static void s5pv210_pm_prepare(void)
s3c_pm_do_save(s5pv210_core_save, ARRAY_SIZE(s5pv210_core_save));
}
static int s5pv210_pm_add(struct device *dev, struct subsys_interface *sif)
/*
* Suspend operations.
*/
static int s5pv210_suspend_enter(suspend_state_t state)
{
pm_cpu_prep = s5pv210_pm_prepare;
pm_cpu_sleep = s5pv210_cpu_suspend;
int ret;
s3c_pm_debug_init();
S3C_PMDBG("%s: suspending the system...\n", __func__);
S3C_PMDBG("%s: wakeup masks: %08x,%08x\n", __func__,
s5pv210_irqwake_intmask, exynos_get_eint_wake_mask());
if (s5pv210_irqwake_intmask == -1U
&& exynos_get_eint_wake_mask() == -1U) {
pr_err("%s: No wake-up sources!\n", __func__);
pr_err("%s: Aborting sleep\n", __func__);
return -EINVAL;
}
s3c_pm_save_uarts();
s5pv210_pm_prepare();
flush_cache_all();
s3c_pm_check_store();
ret = cpu_suspend(0, s5pv210_cpu_suspend);
if (ret)
return ret;
s3c_pm_restore_uarts();
S3C_PMDBG("%s: wakeup stat: %08x\n", __func__,
__raw_readl(S5P_WAKEUP_STAT));
s3c_pm_check_restore();
S3C_PMDBG("%s: resuming the system...\n", __func__);
return 0;
}
static struct subsys_interface s5pv210_pm_interface = {
.name = "s5pv210_pm",
.subsys = &s5pv210_subsys,
.add_dev = s5pv210_pm_add,
static int s5pv210_suspend_prepare(void)
{
s3c_pm_check_prepare();
return 0;
}
static void s5pv210_suspend_finish(void)
{
s3c_pm_check_cleanup();
}
static const struct platform_suspend_ops s5pv210_suspend_ops = {
.enter = s5pv210_suspend_enter,
.prepare = s5pv210_suspend_prepare,
.finish = s5pv210_suspend_finish,
.valid = suspend_valid_only_mem,
};
static __init int s5pv210_pm_drvinit(void)
{
return subsys_interface_register(&s5pv210_pm_interface);
}
arch_initcall(s5pv210_pm_drvinit);
/*
* Syscore operations used to delay restore of certain registers.
*/
static void s5pv210_pm_resume(void)
{
u32 tmp;
@ -159,9 +170,11 @@ static struct syscore_ops s5pv210_pm_syscore_ops = {
.resume = s5pv210_pm_resume,
};
static __init int s5pv210_pm_syscore_init(void)
/*
* Initialization entry point.
*/
void __init s5pv210_pm_init(void)
{
register_syscore_ops(&s5pv210_pm_syscore_ops);
return 0;
suspend_set_ops(&s5pv210_suspend_ops);
}
arch_initcall(s5pv210_pm_syscore_init);

77
arch/arm/mach-s5pv210/s5pv210.c Normal file
View File

@ -0,0 +1,77 @@
/*
* Samsung's S5PC110/S5PV210 flattened device tree enabled machine.
*
* Copyright (c) 2013-2014 Samsung Electronics Co., Ltd.
* Mateusz Krawczuk <m.krawczuk@partner.samsung.com>
* Tomasz Figa <t.figa@samsung.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/of_fdt.h>
#include <linux/of_platform.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/system_misc.h>
#include <plat/map-base.h>
#include <mach/regs-clock.h>
#include "common.h"
static int __init s5pv210_fdt_map_sys(unsigned long node, const char *uname,
int depth, void *data)
{
struct map_desc iodesc;
const __be32 *reg;
int len;
if (!of_flat_dt_is_compatible(node, "samsung,s5pv210-clock"))
return 0;
reg = of_get_flat_dt_prop(node, "reg", &len);
if (reg == NULL || len != (sizeof(unsigned long) * 2))
return 0;
iodesc.pfn = __phys_to_pfn(be32_to_cpu(reg[0]));
iodesc.length = be32_to_cpu(reg[1]) - 1;
iodesc.virtual = (unsigned long)S3C_VA_SYS;
iodesc.type = MT_DEVICE;
iotable_init(&iodesc, 1);
return 1;
}
static void __init s5pv210_dt_map_io(void)
{
debug_ll_io_init();
of_scan_flat_dt(s5pv210_fdt_map_sys, NULL);
}
static void s5pv210_dt_restart(enum reboot_mode mode, const char *cmd)
{
__raw_writel(0x1, S5P_SWRESET);
}
static void __init s5pv210_dt_init_late(void)
{
platform_device_register_simple("s5pv210-cpufreq", -1, NULL, 0);
s5pv210_pm_init();
}
static char const *s5pv210_dt_compat[] __initconst = {
"samsung,s5pc110",
"samsung,s5pv210",
NULL
};
DT_MACHINE_START(S5PV210_DT, "Samsung S5PC110/S5PV210-based board")
.dt_compat = s5pv210_dt_compat,
.map_io = s5pv210_dt_map_io,
.restart = s5pv210_dt_restart,
.init_late = s5pv210_dt_init_late,
MACHINE_END

49
arch/arm/mach-s5pv210/setup-fb-24bpp.c
View File

@ -1,49 +0,0 @@
/* linux/arch/arm/plat-s5pv210/setup-fb-24bpp.c
*
* Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
* http://www.samsung.com/
*
* Base s5pv210 setup information for 24bpp LCD framebuffer
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/fb.h>
#include <linux/gpio.h>
#include <mach/map.h>
#include <plat/fb.h>
#include <mach/regs-clock.h>
#include <plat/gpio-cfg.h>
static void s5pv210_fb_cfg_gpios(unsigned int base, unsigned int nr)
{
s3c_gpio_cfgrange_nopull(base, nr, S3C_GPIO_SFN(2));
for (; nr > 0; nr--, base++)
s5p_gpio_set_drvstr(base, S5P_GPIO_DRVSTR_LV4);
}
void s5pv210_fb_gpio_setup_24bpp(void)
{
s5pv210_fb_cfg_gpios(S5PV210_GPF0(0), 8);
s5pv210_fb_cfg_gpios(S5PV210_GPF1(0), 8);
s5pv210_fb_cfg_gpios(S5PV210_GPF2(0), 8);
s5pv210_fb_cfg_gpios(S5PV210_GPF3(0), 4);
/* Set DISPLAY_CONTROL register for Display path selection.
*
* ouput | RGB | I80 | ITU
* -----------------------------------
* 00 | MIE | FIMD | FIMD
* 01 | MDNIE | MDNIE | FIMD
* 10 | FIMD | FIMD | FIMD
* 11 | FIMD | FIMD | FIMD
*/
writel(0x2, S5P_MDNIE_SEL);
}

43
arch/arm/mach-s5pv210/setup-fimc.c
View File

@ -1,43 +0,0 @@
/*
* Copyright (C) 2011 Samsung Electronics Co., Ltd.
*
* S5PV210 camera interface GPIO configuration.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/gpio.h>
#include <plat/gpio-cfg.h>
#include <plat/camport.h>
int s5pv210_fimc_setup_gpio(enum s5p_camport_id id)
{
u32 gpio8, gpio5;
int ret;
switch (id) {
case S5P_CAMPORT_A:
gpio8 = S5PV210_GPE0(0);
gpio5 = S5PV210_GPE1(0);
break;
case S5P_CAMPORT_B:
gpio8 = S5PV210_GPJ0(0);
gpio5 = S5PV210_GPJ1(0);
break;
default:
WARN(1, "Wrong camport id: %d\n", id);
return -EINVAL;
}
ret = s3c_gpio_cfgall_range(gpio8, 8, S3C_GPIO_SFN(2),
S3C_GPIO_PULL_UP);
if (ret)
return ret;
return s3c_gpio_cfgall_range(gpio5, 5, S3C_GPIO_SFN(2),
S3C_GPIO_PULL_UP);
}

28
arch/arm/mach-s5pv210/setup-i2c0.c
View File

@ -1,28 +0,0 @@
/* linux/arch/arm/mach-s5pv210/setup-i2c0.c
*
* Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
* http://www.samsung.com/
*
* I2C0 GPIO configuration.
*
* Based on plat-s3c64xx/setup-i2c0.c
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/gpio.h>
struct platform_device; /* don't need the contents */
#include <linux/platform_data/i2c-s3c2410.h>
#include <plat/gpio-cfg.h>
void s3c_i2c0_cfg_gpio(struct platform_device *dev)
{
s3c_gpio_cfgall_range(S5PV210_GPD1(0), 2,
S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
}

28
arch/arm/mach-s5pv210/setup-i2c1.c
View File

@ -1,28 +0,0 @@
/* linux/arch/arm/mach-s5pv210/setup-i2c1.c
*
* Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
* http://www.samsung.com/
*
* I2C1 GPIO configuration.
*
* Based on plat-s3c64xx/setup-i2c1.c
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/gpio.h>
struct platform_device; /* don't need the contents */
#include <linux/platform_data/i2c-s3c2410.h>
#include <plat/gpio-cfg.h>
void s3c_i2c1_cfg_gpio(struct platform_device *dev)
{
s3c_gpio_cfgall_range(S5PV210_GPD1(2), 2,
S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
}

28
arch/arm/mach-s5pv210/setup-i2c2.c
View File

@ -1,28 +0,0 @@
/* linux/arch/arm/mach-s5pv210/setup-i2c2.c
*
* Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
* http://www.samsung.com/
*
* I2C2 GPIO configuration.
*
* Based on plat-s3c64xx/setup-i2c0.c
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/gpio.h>
struct platform_device; /* don't need the contents */
#include <linux/platform_data/i2c-s3c2410.h>
#include <plat/gpio-cfg.h>
void s3c_i2c2_cfg_gpio(struct platform_device *dev)
{
s3c_gpio_cfgall_range(S5PV210_GPD1(4), 2,
S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
}

39
arch/arm/mach-s5pv210/setup-ide.c
View File

@ -1,39 +0,0 @@
/* linux/arch/arm/mach-s5pv210/setup-ide.c
*
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* S5PV210 setup information for IDE
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/gpio.h>
#include <plat/gpio-cfg.h>
static void s5pv210_ide_cfg_gpios(unsigned int base, unsigned int nr)
{
s3c_gpio_cfgrange_nopull(base, nr, S3C_GPIO_SFN(4));
for (; nr > 0; nr--, base++)
s5p_gpio_set_drvstr(base, S5P_GPIO_DRVSTR_LV4);
}
void s5pv210_ide_setup_gpio(void)
{
/* CF_Add[0 - 2], CF_IORDY, CF_INTRQ, CF_DMARQ, CF_DMARST, CF_DMACK */
s5pv210_ide_cfg_gpios(S5PV210_GPJ0(0), 8);
/* CF_Data[0 - 7] */
s5pv210_ide_cfg_gpios(S5PV210_GPJ2(0), 8);
/* CF_Data[8 - 15] */
s5pv210_ide_cfg_gpios(S5PV210_GPJ3(0), 8);
/* CF_CS0, CF_CS1, CF_IORD, CF_IOWR */
s5pv210_ide_cfg_gpios(S5PV210_GPJ4(0), 4);
}

24
arch/arm/mach-s5pv210/setup-keypad.c
View File

@ -1,24 +0,0 @@
/*
* linux/arch/arm/mach-s5pv210/setup-keypad.c
*
* Copyright (C) 2010 Samsung Electronics Co.Ltd
* Author: Joonyoung Shim <jy0922.shim@samsung.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
*/
#include <linux/gpio.h>
#include <plat/gpio-cfg.h>
void samsung_keypad_cfg_gpio(unsigned int rows, unsigned int cols)
{
/* Set all the necessary GPH3 pins to special-function 3: KP_ROW[x] */
s3c_gpio_cfgrange_nopull(S5PV210_GPH3(0), rows, S3C_GPIO_SFN(3));
/* Set all the necessary GPH2 pins to special-function 3: KP_COL[x] */
s3c_gpio_cfgrange_nopull(S5PV210_GPH2(0), cols, S3C_GPIO_SFN(3));
}

103
arch/arm/mach-s5pv210/setup-sdhci-gpio.c
View File

@ -1,103 +0,0 @@
/* linux/arch/arm/plat-s5pc1xx/setup-sdhci-gpio.c
*
* Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
* http://www.samsung.com/
*
* S5PV210 - Helper functions for setting up SDHCI device(s) GPIO (HSMMC)
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/interrupt.h>
#include <linux/platform_device.h>
#include <linux/io.h>
#include <linux/gpio.h>
#include <linux/mmc/host.h>
#include <linux/mmc/card.h>
#include <plat/gpio-cfg.h>
#include <plat/sdhci.h>
void s5pv210_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width)
{
struct s3c_sdhci_platdata *pdata = dev->dev.platform_data;
/* Set all the necessary GPG0/GPG1 pins to special-function 2 */
s3c_gpio_cfgrange_nopull(S5PV210_GPG0(0), 2, S3C_GPIO_SFN(2));
switch (width) {
case 8:
/* GPG1[3:6] special-function 3 */
s3c_gpio_cfgrange_nopull(S5PV210_GPG1(3), 4, S3C_GPIO_SFN(3));
case 4:
/* GPG0[3:6] special-function 2 */
s3c_gpio_cfgrange_nopull(S5PV210_GPG0(3), 4, S3C_GPIO_SFN(2));
default:
break;
}
if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) {
s3c_gpio_setpull(S5PV210_GPG0(2), S3C_GPIO_PULL_UP);
s3c_gpio_cfgpin(S5PV210_GPG0(2), S3C_GPIO_SFN(2));
}
}
void s5pv210_setup_sdhci1_cfg_gpio(struct platform_device *dev, int width)
{
struct s3c_sdhci_platdata *pdata = dev->dev.platform_data;
/* Set all the necessary GPG1[0:1] pins to special-function 2 */
s3c_gpio_cfgrange_nopull(S5PV210_GPG1(0), 2, S3C_GPIO_SFN(2));
/* Data pin GPG1[3:6] to special-function 2 */
s3c_gpio_cfgrange_nopull(S5PV210_GPG1(3), 4, S3C_GPIO_SFN(2));
if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) {
s3c_gpio_setpull(S5PV210_GPG1(2), S3C_GPIO_PULL_UP);
s3c_gpio_cfgpin(S5PV210_GPG1(2), S3C_GPIO_SFN(2));
}
}
void s5pv210_setup_sdhci2_cfg_gpio(struct platform_device *dev, int width)
{
struct s3c_sdhci_platdata *pdata = dev->dev.platform_data;
/* Set all the necessary GPG2[0:1] pins to special-function 2 */
s3c_gpio_cfgrange_nopull(S5PV210_GPG2(0), 2, S3C_GPIO_SFN(2));
switch (width) {
case 8:
/* Data pin GPG3[3:6] to special-function 3 */
s3c_gpio_cfgrange_nopull(S5PV210_GPG3(3), 4, S3C_GPIO_SFN(3));
case 4:
/* Data pin GPG2[3:6] to special-function 2 */
s3c_gpio_cfgrange_nopull(S5PV210_GPG2(3), 4, S3C_GPIO_SFN(2));
default:
break;
}
if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) {
s3c_gpio_setpull(S5PV210_GPG2(2), S3C_GPIO_PULL_UP);
s3c_gpio_cfgpin(S5PV210_GPG2(2), S3C_GPIO_SFN(2));
}
}
void s5pv210_setup_sdhci3_cfg_gpio(struct platform_device *dev, int width)
{
struct s3c_sdhci_platdata *pdata = dev->dev.platform_data;
/* Set all the necessary GPG3[0:1] pins to special-function 2 */
s3c_gpio_cfgrange_nopull(S5PV210_GPG3(0), 2, S3C_GPIO_SFN(2));
/* Data pin GPG3[3:6] to special-function 2 */
s3c_gpio_cfgrange_nopull(S5PV210_GPG3(3), 4, S3C_GPIO_SFN(2));
if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) {
s3c_gpio_setpull(S5PV210_GPG3(2), S3C_GPIO_PULL_UP);
s3c_gpio_cfgpin(S5PV210_GPG3(2), S3C_GPIO_SFN(2));
}
}

34
arch/arm/mach-s5pv210/setup-spi.c
View File

@ -1,34 +0,0 @@
/* linux/arch/arm/mach-s5pv210/setup-spi.c
*
* Copyright (C) 2011 Samsung Electronics Ltd.
* http://www.samsung.com/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/gpio.h>
#include <plat/gpio-cfg.h>
#ifdef CONFIG_S3C64XX_DEV_SPI0
int s3c64xx_spi0_cfg_gpio(void)
{
s3c_gpio_cfgpin(S5PV210_GPB(0), S3C_GPIO_SFN(2));
s3c_gpio_setpull(S5PV210_GPB(0), S3C_GPIO_PULL_UP);
s3c_gpio_cfgall_range(S5PV210_GPB(2), 2,
S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
return 0;
}
#endif
#ifdef CONFIG_S3C64XX_DEV_SPI1
int s3c64xx_spi1_cfg_gpio(void)
{
s3c_gpio_cfgpin(S5PV210_GPB(4), S3C_GPIO_SFN(2));
s3c_gpio_setpull(S5PV210_GPB(4), S3C_GPIO_PULL_UP);
s3c_gpio_cfgall_range(S5PV210_GPB(6), 2,
S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
return 0;
}
#endif

95
arch/arm/mach-s5pv210/setup-usb-phy.c
View File

@ -1,95 +0,0 @@
/*
* Copyright (C) 2012 Samsung Electronics Co.Ltd
* Author: Joonyoung Shim <jy0922.shim@samsung.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundationr
*/
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/platform_device.h>
#include <mach/map.h>
#include <plat/cpu.h>
#include <plat/regs-usb-hsotg-phy.h>
#include <plat/usb-phy.h>
#define S5PV210_USB_PHY_CON (S3C_VA_SYS + 0xE80C)
#define S5PV210_USB_PHY0_EN (1 << 0)
#define S5PV210_USB_PHY1_EN (1 << 1)
static int s5pv210_usb_otgphy_init(struct platform_device *pdev)
{
struct clk *xusbxti;
u32 phyclk;
writel(readl(S5PV210_USB_PHY_CON) | S5PV210_USB_PHY0_EN,
S5PV210_USB_PHY_CON);
/* set clock frequency for PLL */
phyclk = readl(S3C_PHYCLK) & ~S3C_PHYCLK_CLKSEL_MASK;
xusbxti = clk_get(&pdev->dev, "xusbxti");
if (xusbxti && !IS_ERR(xusbxti)) {
switch (clk_get_rate(xusbxti)) {
case 12 * MHZ:
phyclk |= S3C_PHYCLK_CLKSEL_12M;
break;
case 24 * MHZ:
phyclk |= S3C_PHYCLK_CLKSEL_24M;
break;
default:
case 48 * MHZ:
/* default reference clock */
break;
}
clk_put(xusbxti);
}
/* TODO: select external clock/oscillator */
writel(phyclk | S3C_PHYCLK_CLK_FORCE, S3C_PHYCLK);
/* set to normal OTG PHY */
writel((readl(S3C_PHYPWR) & ~S3C_PHYPWR_NORMAL_MASK), S3C_PHYPWR);
mdelay(1);
/* reset OTG PHY and Link */
writel(S3C_RSTCON_PHY | S3C_RSTCON_HCLK | S3C_RSTCON_PHYCLK,
S3C_RSTCON);
udelay(20); /* at-least 10uS */
writel(0, S3C_RSTCON);
return 0;
}
static int s5pv210_usb_otgphy_exit(struct platform_device *pdev)
{
writel((readl(S3C_PHYPWR) | S3C_PHYPWR_ANALOG_POWERDOWN |
S3C_PHYPWR_OTG_DISABLE), S3C_PHYPWR);
writel(readl(S5PV210_USB_PHY_CON) & ~S5PV210_USB_PHY0_EN,
S5PV210_USB_PHY_CON);
return 0;
}
int s5p_usb_phy_init(struct platform_device *pdev, int type)
{
if (type == USB_PHY_TYPE_DEVICE)
return s5pv210_usb_otgphy_init(pdev);
return -EINVAL;
}
int s5p_usb_phy_exit(struct platform_device *pdev, int type)
{
if (type == USB_PHY_TYPE_DEVICE)
return s5pv210_usb_otgphy_exit(pdev);
return -EINVAL;
}

19
arch/arm/plat-samsung/s5p-sleep.S → arch/arm/mach-s5pv210/sleep.S
View File

@ -1,8 +1,8 @@
/*
* Copyright (c) 2011 Samsung Electronics Co., Ltd.
* Copyright (c) 2011-2014 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* Common S5P Sleep Code
* S5PV210 Sleep Code
* Based on S3C64XX sleep code by:
* Ben Dooks, (c) 2008 Simtec Electronics
*
@ -10,16 +10,7 @@
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
*/
#include <linux/linkage.h>
@ -40,6 +31,6 @@
* resume code entry for bootloader to call
*/
ENTRY(s3c_cpu_resume)
ENTRY(s5pv210_cpu_resume)
b cpu_resume
ENDPROC(s3c_cpu_resume)
ENDPROC(s5pv210_cpu_resume)

143
arch/arm/plat-samsung/Kconfig
View File

@ -6,30 +6,16 @@
config PLAT_SAMSUNG
bool
depends on PLAT_S3C24XX || ARCH_S3C64XX || PLAT_S5P || ARCH_EXYNOS
depends on PLAT_S3C24XX || ARCH_S3C64XX || ARCH_EXYNOS || ARCH_S5PV210
default y
select GENERIC_IRQ_CHIP
select NO_IOPORT_MAP
help
Base platform code for all Samsung SoC based systems
config PLAT_S5P
bool
depends on ARCH_S5PV210
default y
select ARCH_REQUIRE_GPIOLIB
select ARM_VIC
select NO_IOPORT_MAP
select PLAT_SAMSUNG
select S3C_GPIO_TRACK
select S5P_GPIO_DRVSTR
select SAMSUNG_CLKSRC if !COMMON_CLK
help
Base platform code for Samsung's S5P series SoC.
config SAMSUNG_PM
bool
depends on PM && (PLAT_S3C24XX || ARCH_S3C64XX || S5P_PM)
depends on PM && (PLAT_S3C24XX || ARCH_S3C64XX)
default y
help
Base platform power management code for samsung code
@ -65,48 +51,6 @@ config SAMSUNG_ATAGS
if SAMSUNG_ATAGS
# clock options
config SAMSUNG_CLOCK
bool
default y if !COMMON_CLK
config SAMSUNG_CLKSRC
bool
help
Select the clock code for the clksrc implementation
used by newer systems such as the S3C64XX.
config S5P_CLOCK
def_bool ARCH_S5PV210
help
Support common clock part for ARCH_S5P and ARCH_EXYNOS SoCs
# options for IRQ support
config S5P_IRQ
def_bool ARCH_S5PV210
help
Support common interrupt part for ARCH_S5P SoCs
config S5P_EXT_INT
bool
help
Use the external interrupts (other than GPIO interrupts.)
config S5P_GPIO_INT
bool
help
Common code for the GPIO interrupts (other than external interrupts.)
# options for gpio configuration support
config S5P_GPIO_DRVSTR
bool
help
Internal configuration to get and set correct GPIO driver strength
helper
config SAMSUNG_GPIO_EXTRA
int "Number of additional GPIO pins"
default 128 if SAMSUNG_GPIO_EXTRA128
@ -138,12 +82,6 @@ config S3C_GPIO_TRACK
Internal configuration option to enable the s3c specific gpio
chip tracking if the platform requires it.
# uart options
config S5P_DEV_UART
def_bool y
depends on ARCH_S5PV210
# ADC driver
config S3C_ADC
@ -301,66 +239,6 @@ config SAMSUNG_DEV_BACKLIGHT
help
Compile in platform device definition LCD backlight with PWM Timer
config S5P_DEV_CSIS0
bool
help
Compile in platform device definitions for MIPI-CSIS channel 0
config S5P_DEV_CSIS1
bool
help
Compile in platform device definitions for MIPI-CSIS channel 1
config S5P_DEV_FIMC0
bool
help
Compile in platform device definitions for FIMC controller 0
config S5P_DEV_FIMC1
bool
help
Compile in platform device definitions for FIMC controller 1
config S5P_DEV_FIMC2
bool
help
Compile in platform device definitions for FIMC controller 2
config S5P_DEV_FIMC3
bool
help
Compile in platform device definitions for FIMC controller 3
config S5P_DEV_FIMD0
bool
help
Compile in platform device definitions for FIMD controller 0
config S5P_DEV_G2D
bool
help
Compile in platform device definitions for G2D device
config S5P_DEV_I2C_HDMIPHY
bool
help
Compile in platform device definitions for I2C HDMIPHY controller
config S5P_DEV_JPEG
bool
help
Compile in platform device definitions for JPEG codec
config S5P_DEV_ONENAND
bool
help
Compile in platform device definition for OneNAND controller
config S5P_DEV_TV
bool
help
Compile in platform device definition for TV interface
config S3C24XX_PWM
bool "PWM device support"
select PWM
@ -381,12 +259,6 @@ config S3C_DMA
help
Internal configuration for S3C DMA core
config S5P_IRQ_PM
bool
default y if S5P_PM
help
Legacy IRQ power management for S5P platforms
config SAMSUNG_PM_GPIO
bool
default y if GPIO_SAMSUNG && PM
@ -469,17 +341,6 @@ config SAMSUNG_WDT_RESET
Compile support for system restart by triggering watchdog reset.
Used on SoCs that do not provide dedicated reset control.
config S5P_PM
bool
help
Common code for power management support on S5P and newer SoCs
config S5P_SLEEP
bool
help
Internal config node to apply common S5P sleep management code.
Can be selected by S5P and newer SoCs with similar sleep procedure.
config DEBUG_S3C_UART
depends on PLAT_SAMSUNG
int

15
arch/arm/plat-samsung/Makefile
View File

@ -5,7 +5,6 @@
# Licensed under GPLv2
ccflags-$(CONFIG_ARCH_MULTI_V7) += -I$(srctree)/$(src)/include
ccflags-$(CONFIG_ARCH_EXYNOS) += -I$(srctree)/arch/arm/mach-exynos/include
obj-y :=
obj-m :=
@ -16,15 +15,6 @@ obj- :=
obj-y += init.o cpu.o
obj-$(CONFIG_SAMSUNG_CLOCK) += clock.o
obj-$(CONFIG_SAMSUNG_CLKSRC) += clock-clksrc.o
obj-$(CONFIG_S5P_CLOCK) += s5p-clock.o
obj-$(CONFIG_S5P_IRQ) += s5p-irq.o
obj-$(CONFIG_S5P_EXT_INT) += s5p-irq-eint.o
obj-$(CONFIG_S5P_GPIO_INT) += s5p-irq-gpioint.o
# ADC
obj-$(CONFIG_S3C_ADC) += adc.o
@ -36,7 +26,6 @@ obj-$(CONFIG_SAMSUNG_ATAGS) += platformdata.o
obj-$(CONFIG_SAMSUNG_ATAGS) += devs.o
obj-$(CONFIG_SAMSUNG_ATAGS) += dev-uart.o
obj-$(CONFIG_S5P_DEV_MFC) += s5p-dev-mfc.o
obj-$(CONFIG_S5P_DEV_UART) += s5p-dev-uart.o
obj-$(CONFIG_SAMSUNG_DEV_BACKLIGHT) += dev-backlight.o
@ -58,7 +47,3 @@ obj-$(CONFIG_SAMSUNG_PM_DEBUG) += pm-debug.o
obj-$(CONFIG_SAMSUNG_WAKEMASK) += wakeup-mask.o
obj-$(CONFIG_SAMSUNG_WDT_RESET) += watchdog-reset.o
obj-$(CONFIG_S5P_PM) += s5p-pm.o
obj-$(CONFIG_S5P_IRQ_PM) += s5p-irq-pm.o
obj-$(CONFIG_S5P_SLEEP) += s5p-sleep.o

212
arch/arm/plat-samsung/clock-clksrc.c
View File

@ -1,212 +0,0 @@
/* linux/arch/arm/plat-samsung/clock-clksrc.c
*
* Copyright 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/init.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/list.h>
#include <linux/errno.h>
#include <linux/err.h>
#include <linux/clk.h>
#include <linux/device.h>
#include <linux/io.h>
#include <plat/clock.h>
#include <plat/clock-clksrc.h>
#include <plat/cpu-freq.h>
static inline struct clksrc_clk *to_clksrc(struct clk *clk)
{
return container_of(clk, struct clksrc_clk, clk);
}
static inline u32 bit_mask(u32 shift, u32 nr_bits)
{
u32 mask = 0xffffffff >> (32 - nr_bits);
return mask << shift;
}
static unsigned long s3c_getrate_clksrc(struct clk *clk)
{
struct clksrc_clk *sclk = to_clksrc(clk);
unsigned long rate = clk_get_rate(clk->parent);
u32 clkdiv = __raw_readl(sclk->reg_div.reg);
u32 mask = bit_mask(sclk->reg_div.shift, sclk->reg_div.size);
clkdiv &= mask;
clkdiv >>= sclk->reg_div.shift;
clkdiv++;
rate /= clkdiv;
return rate;
}
static int s3c_setrate_clksrc(struct clk *clk, unsigned long rate)
{
struct clksrc_clk *sclk = to_clksrc(clk);
void __iomem *reg = sclk->reg_div.reg;
unsigned int div;
u32 mask = bit_mask(sclk->reg_div.shift, sclk->reg_div.size);
u32 val;
rate = clk_round_rate(clk, rate);
div = clk_get_rate(clk->parent) / rate;
if (div > (1 << sclk->reg_div.size))
return -EINVAL;
val = __raw_readl(reg);
val &= ~mask;
val |= (div - 1) << sclk->reg_div.shift;
__raw_writel(val, reg);
return 0;
}
static int s3c_setparent_clksrc(struct clk *clk, struct clk *parent)
{
struct clksrc_clk *sclk = to_clksrc(clk);
struct clksrc_sources *srcs = sclk->sources;
u32 clksrc = __raw_readl(sclk->reg_src.reg);
u32 mask = bit_mask(sclk->reg_src.shift, sclk->reg_src.size);
int src_nr = -1;
int ptr;
for (ptr = 0; ptr < srcs->nr_sources; ptr++)
if (srcs->sources[ptr] == parent) {
src_nr = ptr;
break;
}
if (src_nr >= 0) {
clk->parent = parent;
clksrc &= ~mask;
clksrc |= src_nr << sclk->reg_src.shift;
__raw_writel(clksrc, sclk->reg_src.reg);
return 0;
}
return -EINVAL;
}
static unsigned long s3c_roundrate_clksrc(struct clk *clk,
unsigned long rate)
{
struct clksrc_clk *sclk = to_clksrc(clk);
unsigned long parent_rate = clk_get_rate(clk->parent);
int max_div = 1 << sclk->reg_div.size;
int div;
if (rate >= parent_rate)
rate = parent_rate;
else {
div = parent_rate / rate;
if (parent_rate % rate)
div++;
if (div == 0)
div = 1;
if (div > max_div)
div = max_div;
rate = parent_rate / div;
}
return rate;
}
/* Clock initialisation code */
void __init_or_cpufreq s3c_set_clksrc(struct clksrc_clk *clk, bool announce)
{
struct clksrc_sources *srcs = clk->sources;
u32 mask = bit_mask(clk->reg_src.shift, clk->reg_src.size);
u32 clksrc;
if (!clk->reg_src.reg) {
if (!clk->clk.parent)
printk(KERN_ERR "%s: no parent clock specified\n",
clk->clk.name);
return;
}
clksrc = __raw_readl(clk->reg_src.reg);
clksrc &= mask;
clksrc >>= clk->reg_src.shift;
if (clksrc > srcs->nr_sources || !srcs->sources[clksrc]) {
printk(KERN_ERR "%s: bad source %d\n",
clk->clk.name, clksrc);
return;
}
clk->clk.parent = srcs->sources[clksrc];
if (announce)
printk(KERN_INFO "%s: source is %s (%d), rate is %ld\n",
clk->clk.name, clk->clk.parent->name, clksrc,
clk_get_rate(&clk->clk));
}
static struct clk_ops clksrc_ops = {
.set_parent = s3c_setparent_clksrc,
.get_rate = s3c_getrate_clksrc,
.set_rate = s3c_setrate_clksrc,
.round_rate = s3c_roundrate_clksrc,
};
static struct clk_ops clksrc_ops_nodiv = {
.set_parent = s3c_setparent_clksrc,
};
static struct clk_ops clksrc_ops_nosrc = {
.get_rate = s3c_getrate_clksrc,
.set_rate = s3c_setrate_clksrc,
.round_rate = s3c_roundrate_clksrc,
};
void __init s3c_register_clksrc(struct clksrc_clk *clksrc, int size)
{
int ret;
for (; size > 0; size--, clksrc++) {
if (!clksrc->reg_div.reg && !clksrc->reg_src.reg)
printk(KERN_ERR "%s: clock %s has no registers set\n",
__func__, clksrc->clk.name);
/* fill in the default functions */
if (!clksrc->clk.ops) {
if (!clksrc->reg_div.reg)
clksrc->clk.ops = &clksrc_ops_nodiv;
else if (!clksrc->reg_src.reg)
clksrc->clk.ops = &clksrc_ops_nosrc;
else
clksrc->clk.ops = &clksrc_ops;
}
/* setup the clocksource, but do not announce it
* as it may be re-set by the setup routines
* called after the rest of the clocks have been
* registered
*/
s3c_set_clksrc(clksrc, false);
ret = s3c24xx_register_clock(&clksrc->clk);
if (ret < 0) {
printk(KERN_ERR "%s: failed to register %s (%d)\n",
__func__, clksrc->clk.name, ret);
}
}
}

539
arch/arm/plat-samsung/clock.c
View File

@ -1,539 +0,0 @@
/* linux/arch/arm/plat-s3c24xx/clock.c
*
* Copyright 2004-2005 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
*
* S3C24XX Core clock control support
*
* Based on, and code from linux/arch/arm/mach-versatile/clock.c
**
** Copyright (C) 2004 ARM Limited.
** Written by Deep Blue Solutions Limited.
*
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include <linux/init.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/list.h>
#include <linux/errno.h>
#include <linux/err.h>
#include <linux/platform_device.h>
#include <linux/device.h>
#include <linux/interrupt.h>
#include <linux/ioport.h>
#include <linux/clk.h>
#include <linux/spinlock.h>
#include <linux/io.h>
#if defined(CONFIG_DEBUG_FS)
#include <linux/debugfs.h>
#endif
#include <asm/irq.h>
#include <plat/cpu-freq.h>
#include <plat/clock.h>
#include <plat/cpu.h>
#include <linux/serial_core.h>
#include <linux/serial_s3c.h> /* for s3c24xx_uart_devs */
/* clock information */
static LIST_HEAD(clocks);
/* We originally used an mutex here, but some contexts (see resume)
* are calling functions such as clk_set_parent() with IRQs disabled
* causing an BUG to be triggered.
*/
DEFINE_SPINLOCK(clocks_lock);
/* Global watchdog clock used by arch_wtd_reset() callback */
struct clk *s3c2410_wdtclk;
static int __init s3c_wdt_reset_init(void)
{
s3c2410_wdtclk = clk_get(NULL, "watchdog");
if (IS_ERR(s3c2410_wdtclk))
printk(KERN_WARNING "%s: warning: cannot get watchdog clock\n", __func__);
return 0;
}
arch_initcall(s3c_wdt_reset_init);
/* enable and disable calls for use with the clk struct */
static int clk_null_enable(struct clk *clk, int enable)
{
return 0;
}
int clk_enable(struct clk *clk)
{
unsigned long flags;
if (IS_ERR(clk) || clk == NULL)
return -EINVAL;
clk_enable(clk->parent);
spin_lock_irqsave(&clocks_lock, flags);
if ((clk->usage++) == 0)
(clk->enable)(clk, 1);
spin_unlock_irqrestore(&clocks_lock, flags);
return 0;
}
void clk_disable(struct clk *clk)
{
unsigned long flags;
if (IS_ERR(clk) || clk == NULL)
return;
spin_lock_irqsave(&clocks_lock, flags);
if ((--clk->usage) == 0)
(clk->enable)(clk, 0);
spin_unlock_irqrestore(&clocks_lock, flags);
clk_disable(clk->parent);
}
unsigned long clk_get_rate(struct clk *clk)
{
if (IS_ERR_OR_NULL(clk))
return 0;
if (clk->rate != 0)
return clk->rate;
if (clk->ops != NULL && clk->ops->get_rate != NULL)
return (clk->ops->get_rate)(clk);
if (clk->parent != NULL)
return clk_get_rate(clk->parent);
return clk->rate;
}
long clk_round_rate(struct clk *clk, unsigned long rate)
{
if (!IS_ERR_OR_NULL(clk) && clk->ops && clk->ops->round_rate)
return (clk->ops->round_rate)(clk, rate);
return rate;
}
int clk_set_rate(struct clk *clk, unsigned long rate)
{
unsigned long flags;
int ret;
if (IS_ERR_OR_NULL(clk))
return -EINVAL;
/* We do not default just do a clk->rate = rate as
* the clock may have been made this way by choice.
*/
WARN_ON(clk->ops == NULL);
WARN_ON(clk->ops && clk->ops->set_rate == NULL);
if (clk->ops == NULL || clk->ops->set_rate == NULL)
return -EINVAL;
spin_lock_irqsave(&clocks_lock, flags);
ret = (clk->ops->set_rate)(clk, rate);
spin_unlock_irqrestore(&clocks_lock, flags);
return ret;
}
struct clk *clk_get_parent(struct clk *clk)
{
return clk->parent;
}
int clk_set_parent(struct clk *clk, struct clk *parent)
{
unsigned long flags;
int ret = 0;
if (IS_ERR_OR_NULL(clk) || IS_ERR_OR_NULL(parent))
return -EINVAL;
spin_lock_irqsave(&clocks_lock, flags);
if (clk->ops && clk->ops->set_parent)
ret = (clk->ops->set_parent)(clk, parent);
spin_unlock_irqrestore(&clocks_lock, flags);
return ret;
}
EXPORT_SYMBOL(clk_enable);
EXPORT_SYMBOL(clk_disable);
EXPORT_SYMBOL(clk_get_rate);
EXPORT_SYMBOL(clk_round_rate);
EXPORT_SYMBOL(clk_set_rate);
EXPORT_SYMBOL(clk_get_parent);
EXPORT_SYMBOL(clk_set_parent);
/* base clocks */
int clk_default_setrate(struct clk *clk, unsigned long rate)
{
clk->rate = rate;
return 0;
}
struct clk_ops clk_ops_def_setrate = {
.set_rate = clk_default_setrate,
};
struct clk clk_xtal = {
.name = "xtal",
.rate = 0,
.parent = NULL,
.ctrlbit = 0,
};
struct clk clk_ext = {
.name = "ext",
};
struct clk clk_epll = {
.name = "epll",
};
struct clk clk_mpll = {
.name = "mpll",
.ops = &clk_ops_def_setrate,
};
struct clk clk_upll = {
.name = "upll",
.parent = NULL,
.ctrlbit = 0,
};
struct clk clk_f = {
.name = "fclk",
.rate = 0,
.parent = &clk_mpll,
.ctrlbit = 0,
};
struct clk clk_h = {
.name = "hclk",
.rate = 0,
.parent = NULL,
.ctrlbit = 0,
.ops = &clk_ops_def_setrate,
};
struct clk clk_p = {
.name = "pclk",
.rate = 0,
.parent = NULL,
.ctrlbit = 0,
.ops = &clk_ops_def_setrate,
};
struct clk clk_usb_bus = {
.name = "usb-bus",
.rate = 0,
.parent = &clk_upll,
};
struct clk s3c24xx_uclk = {
.name = "uclk",
};
/* initialise the clock system */
/**
* s3c24xx_register_clock() - register a clock
* @clk: The clock to register
*
* Add the specified clock to the list of clocks known by the system.
*/
int s3c24xx_register_clock(struct clk *clk)
{
if (clk->enable == NULL)
clk->enable = clk_null_enable;
/* fill up the clk_lookup structure and register it*/
clk->lookup.dev_id = clk->devname;
clk->lookup.con_id = clk->name;
clk->lookup.clk = clk;
clkdev_add(&clk->lookup);
return 0;
}
/**
* s3c24xx_register_clocks() - register an array of clock pointers
* @clks: Pointer to an array of struct clk pointers
* @nr_clks: The number of clocks in the @clks array.
*
* Call s3c24xx_register_clock() for all the clock pointers contained
* in the @clks list. Returns the number of failures.
*/
int s3c24xx_register_clocks(struct clk **clks, int nr_clks)
{
int fails = 0;
for (; nr_clks > 0; nr_clks--, clks++) {
if (s3c24xx_register_clock(*clks) < 0) {
struct clk *clk = *clks;
printk(KERN_ERR "%s: failed to register %p: %s\n",
__func__, clk, clk->name);
fails++;
}
}
return fails;
}
/**
* s3c_register_clocks() - register an array of clocks
* @clkp: Pointer to the first clock in the array.
* @nr_clks: Number of clocks to register.
*
* Call s3c24xx_register_clock() on the @clkp array given, printing an
* error if it fails to register the clock (unlikely).
*/
void __init s3c_register_clocks(struct clk *clkp, int nr_clks)
{
int ret;
for (; nr_clks > 0; nr_clks--, clkp++) {
ret = s3c24xx_register_clock(clkp);
if (ret < 0) {
printk(KERN_ERR "Failed to register clock %s (%d)\n",
clkp->name, ret);
}
}
}
/**
* s3c_disable_clocks() - disable an array of clocks
* @clkp: Pointer to the first clock in the array.
* @nr_clks: Number of clocks to register.
*
* for internal use only at initialisation time. disable the clocks in the
* @clkp array.
*/
void __init s3c_disable_clocks(struct clk *clkp, int nr_clks)
{
for (; nr_clks > 0; nr_clks--, clkp++)
(clkp->enable)(clkp, 0);
}
/* initialise all the clocks */
int __init s3c24xx_register_baseclocks(unsigned long xtal)
{
printk(KERN_INFO "S3C24XX Clocks, Copyright 2004 Simtec Electronics\n");
clk_xtal.rate = xtal;
/* register our clocks */
if (s3c24xx_register_clock(&clk_xtal) < 0)
printk(KERN_ERR "failed to register master xtal\n");
if (s3c24xx_register_clock(&clk_mpll) < 0)
printk(KERN_ERR "failed to register mpll clock\n");
if (s3c24xx_register_clock(&clk_upll) < 0)
printk(KERN_ERR "failed to register upll clock\n");
if (s3c24xx_register_clock(&clk_f) < 0)
printk(KERN_ERR "failed to register cpu fclk\n");
if (s3c24xx_register_clock(&clk_h) < 0)
printk(KERN_ERR "failed to register cpu hclk\n");
if (s3c24xx_register_clock(&clk_p) < 0)
printk(KERN_ERR "failed to register cpu pclk\n");
return 0;
}
#if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS)
/* debugfs support to trace clock tree hierarchy and attributes */
static struct dentry *clk_debugfs_root;
static void clock_tree_show_one(struct seq_file *s, struct clk *c, int level)
{
struct clk *child;
const char *state;
char buf[255] = { 0 };
int n = 0;
if (c->name)
n = snprintf(buf, sizeof(buf) - 1, "%s", c->name);
if (c->devname)
n += snprintf(buf + n, sizeof(buf) - 1 - n, ":%s", c->devname);
state = (c->usage > 0) ? "on" : "off";
seq_printf(s, "%*s%-*s %-6s %-3d %-10lu\n",
level * 3 + 1, "",
50 - level * 3, buf,
state, c->usage, clk_get_rate(c));
list_for_each_entry(child, &clocks, list) {
if (child->parent != c)
continue;
clock_tree_show_one(s, child, level + 1);
}
}
static int clock_tree_show(struct seq_file *s, void *data)
{
struct clk *c;
unsigned long flags;
seq_printf(s, " clock state ref rate\n");
seq_printf(s, "----------------------------------------------------\n");
spin_lock_irqsave(&clocks_lock, flags);
list_for_each_entry(c, &clocks, list)
if (c->parent == NULL)
clock_tree_show_one(s, c, 0);
spin_unlock_irqrestore(&clocks_lock, flags);
return 0;
}
static int clock_tree_open(struct inode *inode, struct file *file)
{
return single_open(file, clock_tree_show, inode->i_private);
}
static const struct file_operations clock_tree_fops = {
.open = clock_tree_open,
.read = seq_read,
.llseek = seq_lseek,
.release = single_release,
};
static int clock_rate_show(void *data, u64 *val)
{
struct clk *c = data;
*val = clk_get_rate(c);
return 0;
}
DEFINE_SIMPLE_ATTRIBUTE(clock_rate_fops, clock_rate_show, NULL, "%llu\n");
static int clk_debugfs_register_one(struct clk *c)
{
int err;
struct dentry *d;
struct clk *pa = c->parent;
char s[255];
char *p = s;
p += sprintf(p, "%s", c->devname);
d = debugfs_create_dir(s, pa ? pa->dent : clk_debugfs_root);
if (!d)
return -ENOMEM;
c->dent = d;
d = debugfs_create_u8("usecount", S_IRUGO, c->dent, (u8 *)&c->usage);
if (!d) {
err = -ENOMEM;
goto err_out;
}
d = debugfs_create_file("rate", S_IRUGO, c->dent, c, &clock_rate_fops);
if (!d) {
err = -ENOMEM;
goto err_out;
}
return 0;
err_out:
debugfs_remove_recursive(c->dent);
return err;
}
static int clk_debugfs_register(struct clk *c)
{
int err;
struct clk *pa = c->parent;
if (pa && !pa->dent) {
err = clk_debugfs_register(pa);
if (err)
return err;
}
if (!c->dent) {
err = clk_debugfs_register_one(c);
if (err)
return err;
}
return 0;
}
static int __init clk_debugfs_init(void)
{
struct clk *c;
struct dentry *d;
int err = -ENOMEM;
d = debugfs_create_dir("clock", NULL);
if (!d)
return -ENOMEM;
clk_debugfs_root = d;
d = debugfs_create_file("clock_tree", S_IRUGO, clk_debugfs_root, NULL,
&clock_tree_fops);
if (!d)
goto err_out;
list_for_each_entry(c, &clocks, list) {
err = clk_debugfs_register(c);
if (err)
goto err_out;
}
return 0;
err_out:
debugfs_remove_recursive(clk_debugfs_root);
return err;
}
late_initcall(clk_debugfs_init);
#endif /* defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS) */

3
arch/arm/plat-samsung/cpu.c
View File

@ -15,8 +15,7 @@
#include <linux/init.h>
#include <linux/io.h>
#include <mach/map.h>
#include <plat/map-base.h>
#include <plat/cpu.h>
unsigned long samsung_cpu_id;

330
arch/arm/plat-samsung/devs.c
View File

@ -53,7 +53,6 @@
#include <linux/platform_data/ata-samsung_cf.h>
#include <plat/fb.h>
#include <plat/fb-s3c2410.h>
#include <plat/hdmi.h>
#include <linux/platform_data/hwmon-s3c.h>
#include <linux/platform_data/i2c-s3c2410.h>
#include <plat/keypad.h>
@ -145,23 +144,6 @@ struct platform_device s3c_device_camif = {
};
#endif /* CONFIG_CPU_S3C2440 */
/* ASOC DMA */
#ifdef CONFIG_PLAT_S5P
static struct resource samsung_asoc_idma_resource = DEFINE_RES_IRQ(IRQ_I2S0);
struct platform_device samsung_asoc_idma = {
.name = "samsung-idma",
.id = -1,
.num_resources = 1,
.resource = &samsung_asoc_idma_resource,
.dev = {
.dma_mask = &samsung_device_dma_mask,
.coherent_dma_mask = DMA_BIT_MASK(32),
}
};
#endif
/* FB */
#ifdef CONFIG_S3C_DEV_FB
@ -190,151 +172,6 @@ void __init s3c_fb_set_platdata(struct s3c_fb_platdata *pd)
}
#endif /* CONFIG_S3C_DEV_FB */
/* FIMC */
#ifdef CONFIG_S5P_DEV_FIMC0
static struct resource s5p_fimc0_resource[] = {
[0] = DEFINE_RES_MEM(S5P_PA_FIMC0, SZ_4K),
[1] = DEFINE_RES_IRQ(IRQ_FIMC0),
};
struct platform_device s5p_device_fimc0 = {
.name = "s5p-fimc",
.id = 0,
.num_resources = ARRAY_SIZE(s5p_fimc0_resource),
.resource = s5p_fimc0_resource,
.dev = {
.dma_mask = &samsung_device_dma_mask,
.coherent_dma_mask = DMA_BIT_MASK(32),
},
};
struct platform_device s5p_device_fimc_md = {
.name = "s5p-fimc-md",
.id = -1,
};
#endif /* CONFIG_S5P_DEV_FIMC0 */
#ifdef CONFIG_S5P_DEV_FIMC1
static struct resource s5p_fimc1_resource[] = {
[0] = DEFINE_RES_MEM(S5P_PA_FIMC1, SZ_4K),
[1] = DEFINE_RES_IRQ(IRQ_FIMC1),
};
struct platform_device s5p_device_fimc1 = {
.name = "s5p-fimc",
.id = 1,
.num_resources = ARRAY_SIZE(s5p_fimc1_resource),
.resource = s5p_fimc1_resource,
.dev = {
.dma_mask = &samsung_device_dma_mask,
.coherent_dma_mask = DMA_BIT_MASK(32),
},
};
#endif /* CONFIG_S5P_DEV_FIMC1 */
#ifdef CONFIG_S5P_DEV_FIMC2
static struct resource s5p_fimc2_resource[] = {
[0] = DEFINE_RES_MEM(S5P_PA_FIMC2, SZ_4K),
[1] = DEFINE_RES_IRQ(IRQ_FIMC2),
};
struct platform_device s5p_device_fimc2 = {
.name = "s5p-fimc",
.id = 2,
.num_resources = ARRAY_SIZE(s5p_fimc2_resource),
.resource = s5p_fimc2_resource,
.dev = {
.dma_mask = &samsung_device_dma_mask,
.coherent_dma_mask = DMA_BIT_MASK(32),
},
};
#endif /* CONFIG_S5P_DEV_FIMC2 */
#ifdef CONFIG_S5P_DEV_FIMC3
static struct resource s5p_fimc3_resource[] = {
[0] = DEFINE_RES_MEM(S5P_PA_FIMC3, SZ_4K),
[1] = DEFINE_RES_IRQ(IRQ_FIMC3),
};
struct platform_device s5p_device_fimc3 = {
.name = "s5p-fimc",
.id = 3,
.num_resources = ARRAY_SIZE(s5p_fimc3_resource),
.resource = s5p_fimc3_resource,
.dev = {
.dma_mask = &samsung_device_dma_mask,
.coherent_dma_mask = DMA_BIT_MASK(32),
},
};
#endif /* CONFIG_S5P_DEV_FIMC3 */
/* G2D */
#ifdef CONFIG_S5P_DEV_G2D
static struct resource s5p_g2d_resource[] = {
[0] = DEFINE_RES_MEM(S5P_PA_G2D, SZ_4K),
[1] = DEFINE_RES_IRQ(IRQ_2D),
};
struct platform_device s5p_device_g2d = {
.name = "s5p-g2d",
.id = 0,
.num_resources = ARRAY_SIZE(s5p_g2d_resource),
.resource = s5p_g2d_resource,
.dev = {
.dma_mask = &samsung_device_dma_mask,
.coherent_dma_mask = DMA_BIT_MASK(32),
},
};
#endif /* CONFIG_S5P_DEV_G2D */
#ifdef CONFIG_S5P_DEV_JPEG
static struct resource s5p_jpeg_resource[] = {
[0] = DEFINE_RES_MEM(S5P_PA_JPEG, SZ_4K),
[1] = DEFINE_RES_IRQ(IRQ_JPEG),
};
struct platform_device s5p_device_jpeg = {
.name = "s5p-jpeg",
.id = 0,
.num_resources = ARRAY_SIZE(s5p_jpeg_resource),
.resource = s5p_jpeg_resource,
.dev = {
.dma_mask = &samsung_device_dma_mask,
.coherent_dma_mask = DMA_BIT_MASK(32),
},
};
#endif /* CONFIG_S5P_DEV_JPEG */
/* FIMD0 */
#ifdef CONFIG_S5P_DEV_FIMD0
static struct resource s5p_fimd0_resource[] = {
[0] = DEFINE_RES_MEM(S5P_PA_FIMD0, SZ_32K),
[1] = DEFINE_RES_IRQ_NAMED(IRQ_FIMD0_VSYNC, "vsync"),
[2] = DEFINE_RES_IRQ_NAMED(IRQ_FIMD0_FIFO, "fifo"),
[3] = DEFINE_RES_IRQ_NAMED(IRQ_FIMD0_SYSTEM, "lcd_sys"),
};
struct platform_device s5p_device_fimd0 = {
.name = "s5p-fb",
.id = 0,
.num_resources = ARRAY_SIZE(s5p_fimd0_resource),
.resource = s5p_fimd0_resource,
.dev = {
.dma_mask = &samsung_device_dma_mask,
.coherent_dma_mask = DMA_BIT_MASK(32),
},
};
void __init s5p_fimd0_set_platdata(struct s3c_fb_platdata *pd)
{
s3c_set_platdata(pd, sizeof(struct s3c_fb_platdata),
&s5p_device_fimd0);
}
#endif /* CONFIG_S5P_DEV_FIMD0 */
/* HWMON */
#ifdef CONFIG_S3C_DEV_HWMON
@ -722,60 +559,6 @@ void __init s3c_i2c7_set_platdata(struct s3c2410_platform_i2c *pd)
}
#endif /* CONFIG_S3C_DEV_I2C7 */
/* I2C HDMIPHY */
#ifdef CONFIG_S5P_DEV_I2C_HDMIPHY
static struct resource s5p_i2c_resource[] = {
[0] = DEFINE_RES_MEM(S5P_PA_IIC_HDMIPHY, SZ_4K),
[1] = DEFINE_RES_IRQ(IRQ_IIC_HDMIPHY),
};
struct platform_device s5p_device_i2c_hdmiphy = {
.name = "s3c2440-hdmiphy-i2c",
.id = -1,
.num_resources = ARRAY_SIZE(s5p_i2c_resource),
.resource = s5p_i2c_resource,
};
void __init s5p_i2c_hdmiphy_set_platdata(struct s3c2410_platform_i2c *pd)
{
struct s3c2410_platform_i2c *npd;
if (!pd) {
pd = &default_i2c_data;
if (soc_is_s5pv210())
pd->bus_num = 3;
else
pd->bus_num = 0;
}
npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c),
&s5p_device_i2c_hdmiphy);
}
static struct s5p_hdmi_platform_data s5p_hdmi_def_platdata;
void __init s5p_hdmi_set_platdata(struct i2c_board_info *hdmiphy_info,
struct i2c_board_info *mhl_info, int mhl_bus)
{
struct s5p_hdmi_platform_data *pd = &s5p_hdmi_def_platdata;
if (soc_is_s5pv210())
pd->hdmiphy_bus = 3;
else
pd->hdmiphy_bus = 0;
pd->hdmiphy_info = hdmiphy_info;
pd->mhl_info = mhl_info;
pd->mhl_bus = mhl_bus;
s3c_set_platdata(pd, sizeof(struct s5p_hdmi_platform_data),
&s5p_device_hdmi);
}
#endif /* CONFIG_S5P_DEV_I2C_HDMIPHY */
/* I2S */
#ifdef CONFIG_PLAT_S3C24XX
@ -879,36 +662,6 @@ void __init s3c24xx_fb_set_platdata(struct s3c2410fb_mach_info *pd)
}
#endif /* CONFIG_PLAT_S3C24XX */
/* MIPI CSIS */
#ifdef CONFIG_S5P_DEV_CSIS0
static struct resource s5p_mipi_csis0_resource[] = {
[0] = DEFINE_RES_MEM(S5P_PA_MIPI_CSIS0, SZ_16K),
[1] = DEFINE_RES_IRQ(IRQ_MIPI_CSIS0),
};
struct platform_device s5p_device_mipi_csis0 = {
.name = "s5p-mipi-csis",
.id = 0,
.num_resources = ARRAY_SIZE(s5p_mipi_csis0_resource),
.resource = s5p_mipi_csis0_resource,
};
#endif /* CONFIG_S5P_DEV_CSIS0 */
#ifdef CONFIG_S5P_DEV_CSIS1
static struct resource s5p_mipi_csis1_resource[] = {
[0] = DEFINE_RES_MEM(S5P_PA_MIPI_CSIS1, SZ_16K),
[1] = DEFINE_RES_IRQ(IRQ_MIPI_CSIS1),
};
struct platform_device s5p_device_mipi_csis1 = {
.name = "s5p-mipi-csis",
.id = 1,
.num_resources = ARRAY_SIZE(s5p_mipi_csis1_resource),
.resource = s5p_mipi_csis1_resource,
};
#endif
/* NAND */
#ifdef CONFIG_S3C_DEV_NAND
@ -1052,43 +805,6 @@ void __init s3c64xx_onenand1_set_platdata(struct onenand_platform_data *pdata)
}
#endif /* CONFIG_S3C64XX_DEV_ONENAND1 */
#ifdef CONFIG_S5P_DEV_ONENAND
static struct resource s5p_onenand_resources[] = {
[0] = DEFINE_RES_MEM(S5P_PA_ONENAND, SZ_128K),
[1] = DEFINE_RES_MEM(S5P_PA_ONENAND_DMA, SZ_8K),
[2] = DEFINE_RES_IRQ(IRQ_ONENAND_AUDI),
};
struct platform_device s5p_device_onenand = {
.name = "s5pc110-onenand",
.id = -1,
.num_resources = ARRAY_SIZE(s5p_onenand_resources),
.resource = s5p_onenand_resources,
};
#endif /* CONFIG_S5P_DEV_ONENAND */
/* PMU */
#if defined(CONFIG_PLAT_S5P) && !defined(CONFIG_ARCH_EXYNOS)
static struct resource s5p_pmu_resource[] = {
DEFINE_RES_IRQ(IRQ_PMU)
};
static struct platform_device s5p_device_pmu = {
.name = "arm-pmu",
.id = -1,
.num_resources = ARRAY_SIZE(s5p_pmu_resource),
.resource = s5p_pmu_resource,
};
static int __init s5p_pmu_init(void)
{
platform_device_register(&s5p_device_pmu);
return 0;
}
arch_initcall(s5p_pmu_init);
#endif /* CONFIG_PLAT_S5P */
/* PWM Timer */
#ifdef CONFIG_SAMSUNG_DEV_PWM
@ -1251,52 +967,6 @@ void __init s3c24xx_ts_set_platdata(struct s3c2410_ts_mach_info *pd)
}
#endif /* CONFIG_SAMSUNG_DEV_TS */
/* TV */
#ifdef CONFIG_S5P_DEV_TV
static struct resource s5p_hdmi_resources[] = {
[0] = DEFINE_RES_MEM(S5P_PA_HDMI, SZ_1M),
[1] = DEFINE_RES_IRQ(IRQ_HDMI),
};
struct platform_device s5p_device_hdmi = {
.name = "s5p-hdmi",
.id = -1,
.num_resources = ARRAY_SIZE(s5p_hdmi_resources),
.resource = s5p_hdmi_resources,
};
static struct resource s5p_sdo_resources[] = {
[0] = DEFINE_RES_MEM(S5P_PA_SDO, SZ_64K),
[1] = DEFINE_RES_IRQ(IRQ_SDO),
};
struct platform_device s5p_device_sdo = {
.name = "s5p-sdo",
.id = -1,
.num_resources = ARRAY_SIZE(s5p_sdo_resources),
.resource = s5p_sdo_resources,
};
static struct resource s5p_mixer_resources[] = {
[0] = DEFINE_RES_MEM_NAMED(S5P_PA_MIXER, SZ_64K, "mxr"),
[1] = DEFINE_RES_MEM_NAMED(S5P_PA_VP, SZ_64K, "vp"),
[2] = DEFINE_RES_IRQ_NAMED(IRQ_MIXER, "irq"),
};
struct platform_device s5p_device_mixer = {
.name = "s5p-mixer",
.id = -1,
.num_resources = ARRAY_SIZE(s5p_mixer_resources),
.resource = s5p_mixer_resources,
.dev = {
.dma_mask = &samsung_device_dma_mask,
.coherent_dma_mask = DMA_BIT_MASK(32),
}
};
#endif /* CONFIG_S5P_DEV_TV */
/* USB */
#ifdef CONFIG_S3C_DEV_USB_HOST

28
arch/arm/plat-samsung/include/plat/camport.h
View File

@ -1,28 +0,0 @@
/*
* Copyright (C) 2011 Samsung Electronics Co., Ltd.
*
* S5P series camera interface helper functions
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __PLAT_SAMSUNG_CAMPORT_H_
#define __PLAT_SAMSUNG_CAMPORT_H_ __FILE__
enum s5p_camport_id {
S5P_CAMPORT_A,
S5P_CAMPORT_B,
};
/*
* The helper functions to configure GPIO for the camera parallel bus.
* The camera port can be multiplexed with any FIMC entity, even multiple
* FIMC entities are allowed to be attached to a single port simultaneously.
* These functions are to be used in the board setup code.
*/
int s5pv210_fimc_setup_gpio(enum s5p_camport_id id);
int exynos4_fimc_setup_gpio(enum s5p_camport_id id);
#endif /* __PLAT_SAMSUNG_CAMPORT_H */

83
arch/arm/plat-samsung/include/plat/clock-clksrc.h
View File

@ -1,83 +0,0 @@
/* linux/arch/arm/plat-samsung/include/plat/clock-clksrc.h
*
* Parts taken from arch/arm/plat-s3c64xx/clock.c
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
* Copyright 2009 Ben Dooks <ben-linux@fluff.org>
* Copyright 2009 Harald Welte
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/**
* struct clksrc_sources - list of sources for a given clock
* @sources: array of pointers to clocks
* @nr_sources: The size of @sources
*/
struct clksrc_sources {
unsigned int nr_sources;
struct clk **sources;
};
/**
* struct clksrc_reg - register definition for clock control bits
* @reg: pointer to the register in virtual memory.
* @shift: the shift in bits to where the bitfield is.
* @size: the size in bits of the bitfield.
*
* This specifies the size and position of the bits we are interested
* in within the register specified by @reg.
*/
struct clksrc_reg {
void __iomem *reg;
unsigned short shift;
unsigned short size;
};
/**
* struct clksrc_clk - class of clock for newer style samsung devices.
* @clk: the standard clock representation
* @sources: the sources for this clock
* @reg_src: the register definition for selecting the clock's source
* @reg_div: the register definition for the clock's output divisor
*
* This clock implements the features required by the newer SoCs where
* the standard clock block provides an input mux and a post-mux divisor
* to provide the periperhal's clock.
*
* The array of @sources provides the mapping of mux position to the
* clock, and @reg_src shows the code where to modify to change the mux
* position. The @reg_div defines how to change the divider settings on
* the output.
*/
struct clksrc_clk {
struct clk clk;
struct clksrc_sources *sources;
struct clksrc_reg reg_src;
struct clksrc_reg reg_div;
};
/**
* s3c_set_clksrc() - setup the clock from the register settings
* @clk: The clock to setup.
* @announce: true to announce the setting to printk().
*
* Setup the clock from the current register settings, for when the
* kernel boots or if it is resuming from a possibly unknown state.
*/
extern void s3c_set_clksrc(struct clksrc_clk *clk, bool announce);
/**
* s3c_register_clksrc() register clocks from an array of clksrc clocks
* @srcs: The array of clocks to register
* @size: The size of the @srcs array.
*
* Initialise and register the array of clocks described by @srcs.
*/
extern void s3c_register_clksrc(struct clksrc_clk *srcs, int size);

152
arch/arm/plat-samsung/include/plat/clock.h
View File

@ -1,152 +0,0 @@
/* linux/arch/arm/plat-s3c/include/plat/clock.h
*
* Copyright (c) 2004-2005 Simtec Electronics
* http://www.simtec.co.uk/products/SWLINUX/
* Written by Ben Dooks, <ben@simtec.co.uk>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_PLAT_CLOCK_H
#define __ASM_PLAT_CLOCK_H __FILE__
#include <linux/spinlock.h>
#include <linux/clkdev.h>
struct clk;
/**
* struct clk_ops - standard clock operations
* @set_rate: set the clock rate, see clk_set_rate().
* @get_rate: get the clock rate, see clk_get_rate().
* @round_rate: round a given clock rate, see clk_round_rate().
* @set_parent: set the clock's parent, see clk_set_parent().
*
* Group the common clock implementations together so that we
* don't have to keep setting the same fields again. We leave
* enable in struct clk.
*
* Adding an extra layer of indirection into the process should
* not be a problem as it is unlikely these operations are going
* to need to be called quickly.
*/
struct clk_ops {
int (*set_rate)(struct clk *c, unsigned long rate);
unsigned long (*get_rate)(struct clk *c);
unsigned long (*round_rate)(struct clk *c, unsigned long rate);
int (*set_parent)(struct clk *c, struct clk *parent);
};
struct clk {
struct list_head list;
struct module *owner;
struct clk *parent;
const char *name;
const char *devname;
int id;
int usage;
unsigned long rate;
unsigned long ctrlbit;
struct clk_ops *ops;
int (*enable)(struct clk *, int enable);
struct clk_lookup lookup;
#if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS)
struct dentry *dent; /* For visible tree hierarchy */
#endif
};
/* other clocks which may be registered by board support */
extern struct clk s3c24xx_dclk0;
extern struct clk s3c24xx_dclk1;
extern struct clk s3c24xx_clkout0;
extern struct clk s3c24xx_clkout1;
extern struct clk s3c24xx_uclk;
extern struct clk clk_usb_bus;
/* core clock support */
extern struct clk clk_f;
extern struct clk clk_h;
extern struct clk clk_p;
extern struct clk clk_mpll;
extern struct clk clk_upll;
extern struct clk clk_epll;
extern struct clk clk_xtal;
extern struct clk clk_ext;
/* S3C2443/S3C2416 specific clocks */
extern struct clksrc_clk clk_epllref;
extern struct clksrc_clk clk_esysclk;
/* S3C24XX UART clocks */
extern struct clk s3c24xx_clk_uart0;
extern struct clk s3c24xx_clk_uart1;
extern struct clk s3c24xx_clk_uart2;
/* S3C64XX specific clocks */
extern struct clk clk_h2;
extern struct clk clk_27m;
extern struct clk clk_48m;
extern struct clk clk_xusbxti;
extern int clk_default_setrate(struct clk *clk, unsigned long rate);
extern struct clk_ops clk_ops_def_setrate;
/* exports for arch/arm/mach-s3c2410
*
* Please DO NOT use these outside of arch/arm/mach-s3c2410
*/
extern spinlock_t clocks_lock;
extern int s3c2410_clkcon_enable(struct clk *clk, int enable);
extern int s3c24xx_register_clock(struct clk *clk);
extern int s3c24xx_register_clocks(struct clk **clk, int nr_clks);
extern void s3c_register_clocks(struct clk *clk, int nr_clks);
extern void s3c_disable_clocks(struct clk *clkp, int nr_clks);
extern int s3c24xx_register_baseclocks(unsigned long xtal);
extern void s5p_register_clocks(unsigned long xtal_freq);
extern void s3c24xx_setup_clocks(unsigned long fclk,
unsigned long hclk,
unsigned long pclk);
extern void s3c2410_setup_clocks(void);
extern void s3c2412_setup_clocks(void);
extern void s3c244x_setup_clocks(void);
/* S3C2410 specific clock functions */
extern int s3c2410_baseclk_add(void);
/* S3C2443/S3C2416 specific clock functions */
typedef unsigned int (*pll_fn)(unsigned int reg, unsigned int base);
extern void s3c2443_common_setup_clocks(pll_fn get_mpll);
extern void s3c2443_common_init_clocks(int xtal, pll_fn get_mpll,
unsigned int *divs, int nr_divs,
int divmask);
extern int s3c2443_clkcon_enable_h(struct clk *clk, int enable);
extern int s3c2443_clkcon_enable_p(struct clk *clk, int enable);
extern int s3c2443_clkcon_enable_s(struct clk *clk, int enable);
/* S3C64XX specific functions and clocks */
extern int s3c64xx_sclk_ctrl(struct clk *clk, int enable);
/* Global watchdog clock used by arch_wtd_reset() callback */
extern struct clk *s3c2410_wdtclk;
#endif /* __ASM_PLAT_CLOCK_H */

3
arch/arm/plat-samsung/include/plat/cpu-freq-core.h
View File

@ -140,7 +140,6 @@ struct s3c_cpufreq_config {
* any frequency changes. This is really only need by devices like the
* S3C2410 where there is no or limited divider between the PLL and the
* ARMCLK.
* @resume_clocks: Update the clocks on resume.
* @get_iotiming: Get the current IO timing data, mainly for use at start.
* @set_iotiming: Update the IO timings from the cached copies calculated
* from the @calc_iotiming entry when changing the frequency.
@ -169,8 +168,6 @@ struct s3c_cpufreq_info {
/* driver routines */
void (*resume_clocks)(void);
int (*get_iotiming)(struct s3c_cpufreq_config *cfg,
struct s3c_iotimings *timings);

13
arch/arm/plat-samsung/include/plat/cpu.h
View File

@ -47,7 +47,6 @@ IS_SAMSUNG_CPU(s3c24xx, S3C24XX_CPU_ID, S3C24XX_CPU_MASK)
IS_SAMSUNG_CPU(s3c2412, S3C2412_CPU_ID, S3C2412_CPU_MASK)
IS_SAMSUNG_CPU(s3c6400, S3C6400_CPU_ID, S3C64XX_CPU_MASK)
IS_SAMSUNG_CPU(s3c6410, S3C6410_CPU_ID, S3C64XX_CPU_MASK)
IS_SAMSUNG_CPU(s5pv210, S5PV210_CPU_ID, S5PV210_CPU_MASK)
#if defined(CONFIG_CPU_S3C2410) || defined(CONFIG_CPU_S3C2412) || \
defined(CONFIG_CPU_S3C2416) || defined(CONFIG_CPU_S3C2440) || \
@ -76,12 +75,6 @@ IS_SAMSUNG_CPU(s5pv210, S5PV210_CPU_ID, S5PV210_CPU_MASK)
# define soc_is_s3c64xx() 0
#endif
#if defined(CONFIG_CPU_S5PV210)
# define soc_is_s5pv210() is_samsung_s5pv210()
#else
# define soc_is_s5pv210() 0
#endif
#define IODESC_ENT(x) { (unsigned long)S3C24XX_VA_##x, __phys_to_pfn(S3C24XX_PA_##x), S3C24XX_SZ_##x, MT_DEVICE }
#ifndef KHZ
@ -117,12 +110,9 @@ extern void s3c_init_cpu(unsigned long idcode,
/* core initialisation functions */
extern void s5p_init_irq(u32 *vic, u32 num_vic);
extern void s3c24xx_init_io(struct map_desc *mach_desc, int size);
extern void s3c64xx_init_cpu(void);
extern void s5p_init_cpu(void __iomem *cpuid_addr);
extern unsigned int samsung_rev(void);
@ -149,8 +139,5 @@ extern struct bus_type s3c2440_subsys;
extern struct bus_type s3c2442_subsys;
extern struct bus_type s3c2443_subsys;
extern struct bus_type s3c6410_subsys;
extern struct bus_type s5pv210_subsys;
extern void (*s5pc1xx_idle)(void);
#endif

42
arch/arm/plat-samsung/include/plat/devs.h
View File

@ -25,9 +25,6 @@ struct s3c24xx_uart_resources {
extern struct s3c24xx_uart_resources s3c2410_uart_resources[];
extern struct s3c24xx_uart_resources s3c64xx_uart_resources[];
extern struct s3c24xx_uart_resources s5p_uart_resources[];
extern struct s3c24xx_uart_resources exynos4_uart_resources[];
extern struct s3c24xx_uart_resources exynos5_uart_resources[];
extern struct platform_device *s3c24xx_uart_devs[];
extern struct platform_device *s3c24xx_uart_src[];
@ -75,45 +72,6 @@ extern struct platform_device s3c_device_usb_hsotg;
extern struct platform_device s3c_device_usb_hsudc;
extern struct platform_device s3c_device_wdt;
extern struct platform_device s5p_device_fimc0;
extern struct platform_device s5p_device_fimc1;
extern struct platform_device s5p_device_fimc2;
extern struct platform_device s5p_device_fimc3;
extern struct platform_device s5p_device_fimc_md;
extern struct platform_device s5p_device_jpeg;
extern struct platform_device s5p_device_g2d;
extern struct platform_device s5p_device_fimd0;
extern struct platform_device s5p_device_hdmi;
extern struct platform_device s5p_device_i2c_hdmiphy;
extern struct platform_device s5p_device_mfc;
extern struct platform_device s5p_device_mfc_l;
extern struct platform_device s5p_device_mfc_r;
extern struct platform_device s5p_device_mipi_csis0;
extern struct platform_device s5p_device_mipi_csis1;
extern struct platform_device s5p_device_mixer;
extern struct platform_device s5p_device_onenand;
extern struct platform_device s5p_device_sdo;
extern struct platform_device s5pv210_device_ac97;
extern struct platform_device s5pv210_device_iis0;
extern struct platform_device s5pv210_device_iis1;
extern struct platform_device s5pv210_device_iis2;
extern struct platform_device s5pv210_device_pcm0;
extern struct platform_device s5pv210_device_pcm1;
extern struct platform_device s5pv210_device_pcm2;
extern struct platform_device s5pv210_device_spdif;
extern struct platform_device exynos4_device_ac97;
extern struct platform_device exynos4_device_ahci;
extern struct platform_device exynos4_device_i2s0;
extern struct platform_device exynos4_device_i2s1;
extern struct platform_device exynos4_device_i2s2;
extern struct platform_device exynos4_device_ohci;
extern struct platform_device exynos4_device_pcm0;
extern struct platform_device exynos4_device_pcm1;
extern struct platform_device exynos4_device_pcm2;
extern struct platform_device exynos4_device_spdif;
extern struct platform_device samsung_asoc_idma;
extern struct platform_device samsung_device_keypad;
extern struct platform_device samsung_device_pwm;

15
arch/arm/plat-samsung/include/plat/fb-core.h
View File

@ -26,19 +26,4 @@ static inline void s3c_fb_setname(char *name)
#endif
}
/* Re-define device name depending on support. */
static inline void s5p_fb_setname(int id, char *name)
{
switch (id) {
#ifdef CONFIG_S5P_DEV_FIMD0
case 0:
s5p_device_fimd0.name = name;
break;
#endif
default:
printk(KERN_ERR "%s: invalid device id(%d)\n", __func__, id);
break;
}
}
#endif /* __ASM_PLAT_FB_CORE_H */

22
arch/arm/plat-samsung/include/plat/fb.h
View File

@ -25,14 +25,6 @@
*/
extern void s3c_fb_set_platdata(struct s3c_fb_platdata *pd);
/**
* s5p_fimd0_set_platdata() - Setup the FB device with platform data.
* @pd: The platform data to set. The data is copied from the passed structure
* so the machine data can mark the data __initdata so that any unused
* machines will end up dumping their data at runtime.
*/
extern void s5p_fimd0_set_platdata(struct s3c_fb_platdata *pd);
/**
* s3c64xx_fb_gpio_setup_24bpp() - S3C64XX setup function for 24bpp LCD
*
@ -40,18 +32,4 @@ extern void s5p_fimd0_set_platdata(struct s3c_fb_platdata *pd);
*/
extern void s3c64xx_fb_gpio_setup_24bpp(void);
/**
* s5pv210_fb_gpio_setup_24bpp() - S5PV210/S5PC110 setup function for 24bpp LCD
*
* Initialise the GPIO for an 24bpp LCD display on the RGB interface.
*/
extern void s5pv210_fb_gpio_setup_24bpp(void);
/**
* exynos4_fimd0_gpio_setup_24bpp() - Exynos4 setup function for 24bpp LCD0
*
* Initialise the GPIO for an 24bpp LCD display on the RGB interface 0.
*/
extern void exynos4_fimd0_gpio_setup_24bpp(void);
#endif /* __PLAT_S3C_FB_H */

51
arch/arm/plat-samsung/include/plat/fimc-core.h
View File

@ -1,51 +0,0 @@
/*
* arch/arm/plat-samsung/include/plat/fimc-core.h
*
* Copyright 2010 Samsung Electronics Co., Ltd.
* Sylwester Nawrocki <s.nawrocki@samsung.com>
*
* Samsung camera interface driver core functions
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_PLAT_FIMC_CORE_H
#define __ASM_PLAT_FIMC_CORE_H __FILE__
/*
* These functions are only for use with the core support code, such as
* the CPU-specific initialization code.
*/
/* Re-define device name to differentiate the subsystem in various SoCs. */
static inline void s3c_fimc_setname(int id, char *name)
{
switch (id) {
#ifdef CONFIG_S5P_DEV_FIMC0
case 0:
s5p_device_fimc0.name = name;
break;
#endif
#ifdef CONFIG_S5P_DEV_FIMC1
case 1:
s5p_device_fimc1.name = name;
break;
#endif
#ifdef CONFIG_S5P_DEV_FIMC2
case 2:
s5p_device_fimc2.name = name;
break;
#endif
#ifdef CONFIG_S5P_DEV_FIMC3
case 3:
s5p_device_fimc3.name = name;
break;
#endif
default:
break;
}
}
#endif /* __ASM_PLAT_FIMC_CORE_H */

64
arch/arm/plat-samsung/include/plat/gpio-cfg.h
View File

@ -27,7 +27,6 @@
#include <linux/types.h>
typedef unsigned int __bitwise__ samsung_gpio_pull_t;
typedef unsigned int __bitwise__ s5p_gpio_drvstr_t;
/* forward declaration if gpio-core.h hasn't been included */
struct samsung_gpio_chip;
@ -180,67 +179,4 @@ static inline int s3c_gpio_cfgrange_nopull(unsigned int pin, unsigned int size,
return s3c_gpio_cfgall_range(pin, size, cfg, S3C_GPIO_PULL_NONE);
}
/* Define values for the drvstr available for each gpio pin.
*
* These values control the value of the output signal driver strength,
* configurable on most pins on the S5P series.
*/
#define S5P_GPIO_DRVSTR_LV1 ((__force s5p_gpio_drvstr_t)0x0)
#define S5P_GPIO_DRVSTR_LV2 ((__force s5p_gpio_drvstr_t)0x2)
#define S5P_GPIO_DRVSTR_LV3 ((__force s5p_gpio_drvstr_t)0x1)
#define S5P_GPIO_DRVSTR_LV4 ((__force s5p_gpio_drvstr_t)0x3)
/**
* s5c_gpio_get_drvstr() - get the driver streght value of a gpio pin
* @pin: The pin number to get the settings for
*
* Read the driver streght value for the specified pin.
*/
extern s5p_gpio_drvstr_t s5p_gpio_get_drvstr(unsigned int pin);
/**
* s3c_gpio_set_drvstr() - set the driver streght value of a gpio pin
* @pin: The pin number to configure the driver streght value
* @drvstr: The new value of the driver strength
*
* This function sets the driver strength value for the specified pin.
* It will return 0 if successful, or a negative error code if the pin
* cannot support the requested setting.
*/
extern int s5p_gpio_set_drvstr(unsigned int pin, s5p_gpio_drvstr_t drvstr);
/**
* s5p_register_gpio_interrupt() - register interrupt support for a gpio group
* @pin: The pin number from the group to be registered
*
* This function registers gpio interrupt support for the group that the
* specified pin belongs to.
*
* The total number of gpio pins is quite large ob s5p series. Registering
* irq support for all of them would be a resource waste. Because of that the
* interrupt support for standard gpio pins is registered dynamically.
*
* It will return the irq number of the interrupt that has been registered
* or -ENOMEM if no more gpio interrupts can be registered. It is allowed
* to call this function more than once for the same gpio group (the group
* will be registered only once).
*/
extern int s5p_register_gpio_interrupt(int pin);
/** s5p_register_gpioint_bank() - add gpio bank for further gpio interrupt
* registration (see s5p_register_gpio_interrupt function)
* @chain_irq: chained irq number for the gpio int handler for this bank
* @start: start gpio group number of this bank
* @nr_groups: number of gpio groups handled by this bank
*
* This functions registers initial information about gpio banks that
* can be later used by the s5p_register_gpio_interrupt() function to
* enable support for gpio interrupt for particular gpio group.
*/
#ifdef CONFIG_S5P_GPIO_INT
extern int s5p_register_gpioint_bank(int chain_irq, int start, int nr_groups);
#else
#define s5p_register_gpioint_bank(chain_irq, start, nr_groups) do { } while (0)
#endif
#endif /* __PLAT_GPIO_CFG_H */

16
arch/arm/plat-samsung/include/plat/hdmi.h
View File

@ -1,16 +0,0 @@
/*
* Copyright (C) 2012 Samsung Electronics Co.Ltd
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#ifndef __PLAT_SAMSUNG_HDMI_H
#define __PLAT_SAMSUNG_HDMI_H __FILE__
extern void s5p_hdmi_set_platdata(struct i2c_board_info *hdmiphy_info,
struct i2c_board_info *mhl_info, int mhl_bus);
#endif /* __PLAT_SAMSUNG_HDMI_H */

72
arch/arm/plat-samsung/include/plat/irqs.h
View File

@ -1,72 +0,0 @@
/* linux/arch/arm/plat-samsung/include/plat/irqs.h
*
* Copyright (c) 2009 Samsung Electronics Co., Ltd.
* http://www.samsung.com/
*
* S5P Common IRQ support
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __PLAT_SAMSUNG_IRQS_H
#define __PLAT_SAMSUNG_IRQS_H __FILE__
/* we keep the first set of CPU IRQs out of the range of
* the ISA space, so that the PC104 has them to itself
* and we don't end up having to do horrible things to the
* standard ISA drivers....
*
* note, since we're using the VICs, our start must be a
* mulitple of 32 to allow the common code to work
*/
#define S5P_IRQ_OFFSET (32)
#define S5P_IRQ(x) ((x) + S5P_IRQ_OFFSET)
#define S5P_VIC0_BASE S5P_IRQ(0)
#define S5P_VIC1_BASE S5P_IRQ(32)
#define S5P_VIC2_BASE S5P_IRQ(64)
#define S5P_VIC3_BASE S5P_IRQ(96)
#define VIC_BASE(x) (S5P_VIC0_BASE + ((x)*32))
#define IRQ_VIC0_BASE S5P_VIC0_BASE
#define IRQ_VIC1_BASE S5P_VIC1_BASE
#define IRQ_VIC2_BASE S5P_VIC2_BASE
/* VIC based IRQs */
#define S5P_IRQ_VIC0(x) (S5P_VIC0_BASE + (x))
#define S5P_IRQ_VIC1(x) (S5P_VIC1_BASE + (x))
#define S5P_IRQ_VIC2(x) (S5P_VIC2_BASE + (x))
#define S5P_IRQ_VIC3(x) (S5P_VIC3_BASE + (x))
#define IRQ_EINT(x) ((x) < 16 ? ((x) + S5P_EINT_BASE1) \
: ((x) - 16 + S5P_EINT_BASE2))
#define EINT_OFFSET(irq) ((irq) < S5P_EINT_BASE2 ? \
((irq) - S5P_EINT_BASE1) : \
((irq) + 16 - S5P_EINT_BASE2))
#define IRQ_EINT_BIT(x) EINT_OFFSET(x)
/* Typically only a few gpio chips require gpio interrupt support.
To avoid memory waste irq descriptors are allocated only for
S5P_GPIOINT_GROUP_COUNT chips, each with total number of
S5P_GPIOINT_GROUP_SIZE pins/irqs. Each GPIOINT group can be assiged
to any gpio chip with the s5p_register_gpio_interrupt() function */
#define S5P_GPIOINT_GROUP_COUNT 4
#define S5P_GPIOINT_GROUP_SIZE 8
#define S5P_GPIOINT_COUNT (S5P_GPIOINT_GROUP_COUNT * S5P_GPIOINT_GROUP_SIZE)
/* IRQ types common for all s5p platforms */
#define S5P_IRQ_TYPE_LEVEL_LOW (0x00)
#define S5P_IRQ_TYPE_LEVEL_HIGH (0x01)
#define S5P_IRQ_TYPE_EDGE_FALLING (0x02)
#define S5P_IRQ_TYPE_EDGE_RISING (0x03)
#define S5P_IRQ_TYPE_EDGE_BOTH (0x04)
#endif /* __PLAT_SAMSUNG_IRQS_H */

35
arch/arm/plat-samsung/include/plat/mfc.h
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@ -1,35 +0,0 @@
/*
* Copyright (C) 2011 Samsung Electronics Co.Ltd
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#ifndef __PLAT_SAMSUNG_MFC_H
#define __PLAT_SAMSUNG_MFC_H __FILE__
struct s5p_mfc_dt_meminfo {
unsigned long loff;
unsigned long lsize;
unsigned long roff;
unsigned long rsize;
char *compatible;
};
/**
* s5p_mfc_reserve_mem - function to early reserve memory for MFC driver
* @rbase: base address for MFC 'right' memory interface
* @rsize: size of the memory reserved for MFC 'right' interface
* @lbase: base address for MFC 'left' memory interface
* @lsize: size of the memory reserved for MFC 'left' interface
*
* This function reserves system memory for both MFC device memory
* interfaces and registers it to respective struct device entries as
* coherent memory.
*/
void __init s5p_mfc_reserve_mem(phys_addr_t rbase, unsigned int rsize,
phys_addr_t lbase, unsigned int lsize);
#endif /* __PLAT_SAMSUNG_MFC_H */

323
arch/arm/plat-samsung/include/plat/pll.h
View File

@ -1,323 +0,0 @@
/* linux/arch/arm/plat-samsung/include/plat/pll.h
*
* Copyright (c) 2009-2011 Samsung Electronics Co., Ltd.
* http://www.samsung.com/
*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
* Samsung PLL codes
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <asm/div64.h>
#define S3C24XX_PLL_MDIV_MASK (0xFF)
#define S3C24XX_PLL_PDIV_MASK (0x1F)
#define S3C24XX_PLL_SDIV_MASK (0x3)
#define S3C24XX_PLL_MDIV_SHIFT (12)
#define S3C24XX_PLL_PDIV_SHIFT (4)
#define S3C24XX_PLL_SDIV_SHIFT (0)
static inline unsigned int s3c24xx_get_pll(unsigned int pllval,
unsigned int baseclk)
{
unsigned int mdiv, pdiv, sdiv;
uint64_t fvco;
mdiv = (pllval >> S3C24XX_PLL_MDIV_SHIFT) & S3C24XX_PLL_MDIV_MASK;
pdiv = (pllval >> S3C24XX_PLL_PDIV_SHIFT) & S3C24XX_PLL_PDIV_MASK;
sdiv = (pllval >> S3C24XX_PLL_SDIV_SHIFT) & S3C24XX_PLL_SDIV_MASK;
fvco = (uint64_t)baseclk * (mdiv + 8);
do_div(fvco, (pdiv + 2) << sdiv);
return (unsigned int)fvco;
}
#define S3C2416_PLL_MDIV_MASK (0x3FF)
#define S3C2416_PLL_PDIV_MASK (0x3F)
#define S3C2416_PLL_SDIV_MASK (0x7)
#define S3C2416_PLL_MDIV_SHIFT (14)
#define S3C2416_PLL_PDIV_SHIFT (5)
#define S3C2416_PLL_SDIV_SHIFT (0)
static inline unsigned int s3c2416_get_pll(unsigned int pllval,
unsigned int baseclk)
{
unsigned int mdiv, pdiv, sdiv;
uint64_t fvco;
mdiv = (pllval >> S3C2416_PLL_MDIV_SHIFT) & S3C2416_PLL_MDIV_MASK;
pdiv = (pllval >> S3C2416_PLL_PDIV_SHIFT) & S3C2416_PLL_PDIV_MASK;
sdiv = (pllval >> S3C2416_PLL_SDIV_SHIFT) & S3C2416_PLL_SDIV_MASK;
fvco = (uint64_t)baseclk * mdiv;
do_div(fvco, (pdiv << sdiv));
return (unsigned int)fvco;
}
#define S3C6400_PLL_MDIV_MASK (0x3FF)
#define S3C6400_PLL_PDIV_MASK (0x3F)
#define S3C6400_PLL_SDIV_MASK (0x7)
#define S3C6400_PLL_MDIV_SHIFT (16)
#define S3C6400_PLL_PDIV_SHIFT (8)
#define S3C6400_PLL_SDIV_SHIFT (0)
static inline unsigned long s3c6400_get_pll(unsigned long baseclk,
u32 pllcon)
{
u32 mdiv, pdiv, sdiv;
u64 fvco = baseclk;
mdiv = (pllcon >> S3C6400_PLL_MDIV_SHIFT) & S3C6400_PLL_MDIV_MASK;
pdiv = (pllcon >> S3C6400_PLL_PDIV_SHIFT) & S3C6400_PLL_PDIV_MASK;
sdiv = (pllcon >> S3C6400_PLL_SDIV_SHIFT) & S3C6400_PLL_SDIV_MASK;
fvco *= mdiv;
do_div(fvco, (pdiv << sdiv));
return (unsigned long)fvco;
}
#define PLL6553X_MDIV_MASK (0x7F)
#define PLL6553X_PDIV_MASK (0x1F)
#define PLL6553X_SDIV_MASK (0x3)
#define PLL6553X_KDIV_MASK (0xFFFF)
#define PLL6553X_MDIV_SHIFT (16)
#define PLL6553X_PDIV_SHIFT (8)
#define PLL6553X_SDIV_SHIFT (0)
static inline unsigned long s3c_get_pll6553x(unsigned long baseclk,
u32 pll_con0, u32 pll_con1)
{
unsigned long result;
u32 mdiv, pdiv, sdiv, kdiv;
u64 tmp;
mdiv = (pll_con0 >> PLL6553X_MDIV_SHIFT) & PLL6553X_MDIV_MASK;
pdiv = (pll_con0 >> PLL6553X_PDIV_SHIFT) & PLL6553X_PDIV_MASK;
sdiv = (pll_con0 >> PLL6553X_SDIV_SHIFT) & PLL6553X_SDIV_MASK;
kdiv = pll_con1 & PLL6553X_KDIV_MASK;
/*
* We need to multiple baseclk by mdiv (the integer part) and kdiv
* which is in 2^16ths, so shift mdiv up (does not overflow) and
* add kdiv before multiplying. The use of tmp is to avoid any
* overflows before shifting bac down into result when multipling
* by the mdiv and kdiv pair.
*/
tmp = baseclk;
tmp *= (mdiv << 16) + kdiv;
do_div(tmp, (pdiv << sdiv));
result = tmp >> 16;
return result;
}
#define PLL35XX_MDIV_MASK (0x3FF)
#define PLL35XX_PDIV_MASK (0x3F)
#define PLL35XX_SDIV_MASK (0x7)
#define PLL35XX_MDIV_SHIFT (16)
#define PLL35XX_PDIV_SHIFT (8)
#define PLL35XX_SDIV_SHIFT (0)
static inline unsigned long s5p_get_pll35xx(unsigned long baseclk, u32 pll_con)
{
u32 mdiv, pdiv, sdiv;
u64 fvco = baseclk;
mdiv = (pll_con >> PLL35XX_MDIV_SHIFT) & PLL35XX_MDIV_MASK;
pdiv = (pll_con >> PLL35XX_PDIV_SHIFT) & PLL35XX_PDIV_MASK;
sdiv = (pll_con >> PLL35XX_SDIV_SHIFT) & PLL35XX_SDIV_MASK;
fvco *= mdiv;
do_div(fvco, (pdiv << sdiv));
return (unsigned long)fvco;
}
#define PLL36XX_KDIV_MASK (0xFFFF)
#define PLL36XX_MDIV_MASK (0x1FF)
#define PLL36XX_PDIV_MASK (0x3F)
#define PLL36XX_SDIV_MASK (0x7)
#define PLL36XX_MDIV_SHIFT (16)
#define PLL36XX_PDIV_SHIFT (8)
#define PLL36XX_SDIV_SHIFT (0)
static inline unsigned long s5p_get_pll36xx(unsigned long baseclk,
u32 pll_con0, u32 pll_con1)
{
unsigned long result;
u32 mdiv, pdiv, sdiv, kdiv;
u64 tmp;
mdiv = (pll_con0 >> PLL36XX_MDIV_SHIFT) & PLL36XX_MDIV_MASK;
pdiv = (pll_con0 >> PLL36XX_PDIV_SHIFT) & PLL36XX_PDIV_MASK;
sdiv = (pll_con0 >> PLL36XX_SDIV_SHIFT) & PLL36XX_SDIV_MASK;
kdiv = pll_con1 & PLL36XX_KDIV_MASK;
tmp = baseclk;
tmp *= (mdiv << 16) + kdiv;
do_div(tmp, (pdiv << sdiv));
result = tmp >> 16;
return result;
}
#define PLL45XX_MDIV_MASK (0x3FF)
#define PLL45XX_PDIV_MASK (0x3F)
#define PLL45XX_SDIV_MASK (0x7)
#define PLL45XX_MDIV_SHIFT (16)
#define PLL45XX_PDIV_SHIFT (8)
#define PLL45XX_SDIV_SHIFT (0)
enum pll45xx_type_t {
pll_4500,
pll_4502,
pll_4508
};
static inline unsigned long s5p_get_pll45xx(unsigned long baseclk, u32 pll_con,
enum pll45xx_type_t pll_type)
{
u32 mdiv, pdiv, sdiv;
u64 fvco = baseclk;
mdiv = (pll_con >> PLL45XX_MDIV_SHIFT) & PLL45XX_MDIV_MASK;
pdiv = (pll_con >> PLL45XX_PDIV_SHIFT) & PLL45XX_PDIV_MASK;
sdiv = (pll_con >> PLL45XX_SDIV_SHIFT) & PLL45XX_SDIV_MASK;
if (pll_type == pll_4508)
sdiv = sdiv - 1;
fvco *= mdiv;
do_div(fvco, (pdiv << sdiv));
return (unsigned long)fvco;
}
/* CON0 bit-fields */
#define PLL46XX_MDIV_MASK (0x1FF)
#define PLL46XX_PDIV_MASK (0x3F)
#define PLL46XX_SDIV_MASK (0x7)
#define PLL46XX_LOCKED_SHIFT (29)
#define PLL46XX_MDIV_SHIFT (16)
#define PLL46XX_PDIV_SHIFT (8)
#define PLL46XX_SDIV_SHIFT (0)
/* CON1 bit-fields */
#define PLL46XX_MRR_MASK (0x1F)
#define PLL46XX_MFR_MASK (0x3F)
#define PLL46XX_KDIV_MASK (0xFFFF)
#define PLL4650C_KDIV_MASK (0xFFF)
#define PLL46XX_MRR_SHIFT (24)
#define PLL46XX_MFR_SHIFT (16)
#define PLL46XX_KDIV_SHIFT (0)
enum pll46xx_type_t {
pll_4600,
pll_4650,
pll_4650c,
};
static inline unsigned long s5p_get_pll46xx(unsigned long baseclk,
u32 pll_con0, u32 pll_con1,
enum pll46xx_type_t pll_type)
{
unsigned long result;
u32 mdiv, pdiv, sdiv, kdiv;
u64 tmp;
mdiv = (pll_con0 >> PLL46XX_MDIV_SHIFT) & PLL46XX_MDIV_MASK;
pdiv = (pll_con0 >> PLL46XX_PDIV_SHIFT) & PLL46XX_PDIV_MASK;
sdiv = (pll_con0 >> PLL46XX_SDIV_SHIFT) & PLL46XX_SDIV_MASK;
kdiv = pll_con1 & PLL46XX_KDIV_MASK;
if (pll_type == pll_4650c)
kdiv = pll_con1 & PLL4650C_KDIV_MASK;
else
kdiv = pll_con1 & PLL46XX_KDIV_MASK;
tmp = baseclk;
if (pll_type == pll_4600) {
tmp *= (mdiv << 16) + kdiv;
do_div(tmp, (pdiv << sdiv));
result = tmp >> 16;
} else {
tmp *= (mdiv << 10) + kdiv;
do_div(tmp, (pdiv << sdiv));
result = tmp >> 10;
}
return result;
}
#define PLL90XX_MDIV_MASK (0xFF)
#define PLL90XX_PDIV_MASK (0x3F)
#define PLL90XX_SDIV_MASK (0x7)
#define PLL90XX_KDIV_MASK (0xffff)
#define PLL90XX_LOCKED_SHIFT (29)
#define PLL90XX_MDIV_SHIFT (16)
#define PLL90XX_PDIV_SHIFT (8)
#define PLL90XX_SDIV_SHIFT (0)
#define PLL90XX_KDIV_SHIFT (0)
static inline unsigned long s5p_get_pll90xx(unsigned long baseclk,
u32 pll_con, u32 pll_conk)
{
unsigned long result;
u32 mdiv, pdiv, sdiv, kdiv;
u64 tmp;
mdiv = (pll_con >> PLL90XX_MDIV_SHIFT) & PLL90XX_MDIV_MASK;
pdiv = (pll_con >> PLL90XX_PDIV_SHIFT) & PLL90XX_PDIV_MASK;
sdiv = (pll_con >> PLL90XX_SDIV_SHIFT) & PLL90XX_SDIV_MASK;
kdiv = pll_conk & PLL90XX_KDIV_MASK;
/*
* We need to multiple baseclk by mdiv (the integer part) and kdiv
* which is in 2^16ths, so shift mdiv up (does not overflow) and
* add kdiv before multiplying. The use of tmp is to avoid any
* overflows before shifting bac down into result when multipling
* by the mdiv and kdiv pair.
*/
tmp = baseclk;
tmp *= (mdiv << 16) + kdiv;
do_div(tmp, (pdiv << sdiv));
result = tmp >> 16;
return result;
}
#define PLL65XX_MDIV_MASK (0x3FF)
#define PLL65XX_PDIV_MASK (0x3F)
#define PLL65XX_SDIV_MASK (0x7)
#define PLL65XX_MDIV_SHIFT (16)
#define PLL65XX_PDIV_SHIFT (8)
#define PLL65XX_SDIV_SHIFT (0)
static inline unsigned long s5p_get_pll65xx(unsigned long baseclk, u32 pll_con)
{
u32 mdiv, pdiv, sdiv;
u64 fvco = baseclk;
mdiv = (pll_con >> PLL65XX_MDIV_SHIFT) & PLL65XX_MDIV_MASK;
pdiv = (pll_con >> PLL65XX_PDIV_SHIFT) & PLL65XX_PDIV_MASK;
sdiv = (pll_con >> PLL65XX_SDIV_SHIFT) & PLL65XX_SDIV_MASK;
fvco *= mdiv;
do_div(fvco, (pdiv << sdiv));
return (unsigned long)fvco;
}

65
arch/arm/plat-samsung/include/plat/s5p-clock.h
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@ -1,65 +0,0 @@
/* linux/arch/arm/plat-samsung/include/plat/s5p-clock.h
*
* Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* Header file for s5p clock support
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_PLAT_S5P_CLOCK_H
#define __ASM_PLAT_S5P_CLOCK_H __FILE__
#include <linux/clk.h>
#define GET_DIV(clk, field) ((((clk) & field##_MASK) >> field##_SHIFT) + 1)
#define clk_fin_apll clk_ext_xtal_mux
#define clk_fin_bpll clk_ext_xtal_mux
#define clk_fin_cpll clk_ext_xtal_mux
#define clk_fin_mpll clk_ext_xtal_mux
#define clk_fin_epll clk_ext_xtal_mux
#define clk_fin_dpll clk_ext_xtal_mux
#define clk_fin_vpll clk_ext_xtal_mux
#define clk_fin_hpll clk_ext_xtal_mux
extern struct clk clk_ext_xtal_mux;
extern struct clk clk_xusbxti;
extern struct clk clk_48m;
extern struct clk s5p_clk_27m;
extern struct clk clk_fout_apll;
extern struct clk clk_fout_bpll;
extern struct clk clk_fout_bpll_div2;
extern struct clk clk_fout_cpll;
extern struct clk clk_fout_mpll;
extern struct clk clk_fout_mpll_div2;
extern struct clk clk_fout_epll;
extern struct clk clk_fout_dpll;
extern struct clk clk_fout_vpll;
extern struct clk clk_arm;
extern struct clk clk_vpll;
extern struct clksrc_sources clk_src_apll;
extern struct clksrc_sources clk_src_bpll;
extern struct clksrc_sources clk_src_bpll_fout;
extern struct clksrc_sources clk_src_cpll;
extern struct clksrc_sources clk_src_mpll;
extern struct clksrc_sources clk_src_mpll_fout;
extern struct clksrc_sources clk_src_epll;
extern struct clksrc_sources clk_src_dpll;
extern int s5p_gatectrl(void __iomem *reg, struct clk *clk, int enable);
/* Common EPLL operations for S5P platform */
extern int s5p_epll_enable(struct clk *clk, int enable);
extern unsigned long s5p_epll_get_rate(struct clk *clk);
/* SPDIF clk operations common for S5PV210/C110 and Exynos4 */
extern int s5p_spdif_set_rate(struct clk *clk, unsigned long rate);
extern unsigned long s5p_spdif_get_rate(struct clk *clk);
extern struct clk_ops s5p_sclk_spdif_ops;
#endif /* __ASM_PLAT_S5P_CLOCK_H */

47
arch/arm/plat-samsung/include/plat/sdhci.h
View File

@ -57,14 +57,6 @@ extern void s3c2416_setup_sdhci1_cfg_gpio(struct platform_device *, int w);
extern void s3c64xx_setup_sdhci0_cfg_gpio(struct platform_device *, int w);
extern void s3c64xx_setup_sdhci1_cfg_gpio(struct platform_device *, int w);
extern void s3c64xx_setup_sdhci2_cfg_gpio(struct platform_device *, int w);
extern void s5pv210_setup_sdhci0_cfg_gpio(struct platform_device *, int w);
extern void s5pv210_setup_sdhci1_cfg_gpio(struct platform_device *, int w);
extern void s5pv210_setup_sdhci2_cfg_gpio(struct platform_device *, int w);
extern void s5pv210_setup_sdhci3_cfg_gpio(struct platform_device *, int w);
extern void exynos4_setup_sdhci0_cfg_gpio(struct platform_device *, int w);
extern void exynos4_setup_sdhci1_cfg_gpio(struct platform_device *, int w);
extern void exynos4_setup_sdhci2_cfg_gpio(struct platform_device *, int w);
extern void exynos4_setup_sdhci3_cfg_gpio(struct platform_device *, int w);
/* S3C2416 SDHCI setup */
@ -144,45 +136,6 @@ static inline void s3c6400_default_sdhci2(void) { }
#endif /* CONFIG_S3C64XX_SETUP_SDHCI */
/* S5PV210 SDHCI setup */
#ifdef CONFIG_S5PV210_SETUP_SDHCI
static inline void s5pv210_default_sdhci0(void)
{
#ifdef CONFIG_S3C_DEV_HSMMC
s3c_hsmmc0_def_platdata.cfg_gpio = s5pv210_setup_sdhci0_cfg_gpio;
#endif
}
static inline void s5pv210_default_sdhci1(void)
{
#ifdef CONFIG_S3C_DEV_HSMMC1
s3c_hsmmc1_def_platdata.cfg_gpio = s5pv210_setup_sdhci1_cfg_gpio;
#endif
}
static inline void s5pv210_default_sdhci2(void)
{
#ifdef CONFIG_S3C_DEV_HSMMC2
s3c_hsmmc2_def_platdata.cfg_gpio = s5pv210_setup_sdhci2_cfg_gpio;
#endif
}
static inline void s5pv210_default_sdhci3(void)
{
#ifdef CONFIG_S3C_DEV_HSMMC3
s3c_hsmmc3_def_platdata.cfg_gpio = s5pv210_setup_sdhci3_cfg_gpio;
#endif
}
#else
static inline void s5pv210_default_sdhci0(void) { }
static inline void s5pv210_default_sdhci1(void) { }
static inline void s5pv210_default_sdhci2(void) { }
static inline void s5pv210_default_sdhci3(void) { }
#endif /* CONFIG_S5PV210_SETUP_SDHCI */
static inline void s3c_sdhci_setname(int id, char *name)
{
switch (id) {

44
arch/arm/plat-samsung/include/plat/tv-core.h
View File

@ -1,44 +0,0 @@
/*
* arch/arm/plat-samsung/include/plat/tv.h
*
* Copyright 2011 Samsung Electronics Co., Ltd.
* Tomasz Stanislawski <t.stanislaws@samsung.com>
*
* Samsung TV driver core functions
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __SAMSUNG_PLAT_TV_H
#define __SAMSUNG_PLAT_TV_H __FILE__
/*
* These functions are only for use with the core support code, such as
* the CPU-specific initialization code.
*/
/* Re-define device name to differentiate the subsystem in various SoCs. */
static inline void s5p_hdmi_setname(char *name)
{
#ifdef CONFIG_S5P_DEV_TV
s5p_device_hdmi.name = name;
#endif
}
static inline void s5p_mixer_setname(char *name)
{
#ifdef CONFIG_S5P_DEV_TV
s5p_device_mixer.name = name;
#endif
}
static inline void s5p_sdo_setname(char *name)
{
#ifdef CONFIG_S5P_DEV_TV
s5p_device_sdo.name = name;
#endif
}
#endif /* __SAMSUNG_PLAT_TV_H */

1
arch/arm/plat-samsung/init.c
View File

@ -30,7 +30,6 @@
#include <plat/cpu.h>
#include <plat/devs.h>
#include <plat/clock.h>
static struct cpu_table *cpu;

4
arch/arm/plat-samsung/pm-gpio.c
View File

@ -196,7 +196,7 @@ struct samsung_gpio_pm samsung_gpio_pm_2bit = {
.resume = samsung_gpio_pm_2bit_resume,
};
#if defined(CONFIG_ARCH_S3C64XX) || defined(CONFIG_PLAT_S5P)
#if defined(CONFIG_ARCH_S3C64XX)
static void samsung_gpio_pm_4bit_save(struct samsung_gpio_chip *chip)
{
chip->pm_save[1] = __raw_readl(chip->base + OFFS_CON);
@ -306,7 +306,7 @@ struct samsung_gpio_pm samsung_gpio_pm_4bit = {
.save = samsung_gpio_pm_4bit_save,
.resume = samsung_gpio_pm_4bit_resume,
};
#endif /* CONFIG_ARCH_S3C64XX || CONFIG_PLAT_S5P */
#endif /* CONFIG_ARCH_S3C64XX */
/**
* samsung_pm_save_gpio() - save gpio chip data for suspend

294
arch/arm/plat-samsung/s5p-clock.c
View File

@ -1,294 +0,0 @@
/*
* Copyright 2009 Samsung Electronics Co., Ltd.
* http://www.samsung.com/
*
* S5P - Common clock support
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/init.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/list.h>
#include <linux/errno.h>
#include <linux/err.h>
#include <linux/clk.h>
#include <linux/device.h>
#include <linux/io.h>
#include <asm/div64.h>
#include <mach/regs-clock.h>
#include <plat/clock.h>
#include <plat/clock-clksrc.h>
#include <plat/s5p-clock.h>
/* fin_apll, fin_mpll and fin_epll are all the same clock, which we call
* clk_ext_xtal_mux.
*/
struct clk clk_ext_xtal_mux = {
.name = "ext_xtal",
.id = -1,
};
struct clk clk_xusbxti = {
.name = "xusbxti",
.id = -1,
.rate = 24000000,
};
struct clk s5p_clk_27m = {
.name = "clk_27m",
.id = -1,
.rate = 27000000,
};
/* 48MHz USB Phy clock output */
struct clk clk_48m = {
.name = "clk_48m",
.id = -1,
.rate = 48000000,
};
/* APLL clock output
* No need .ctrlbit, this is always on
*/
struct clk clk_fout_apll = {
.name = "fout_apll",
.id = -1,
};
/* BPLL clock output */
struct clk clk_fout_bpll = {
.name = "fout_bpll",
.id = -1,
};
struct clk clk_fout_bpll_div2 = {
.name = "fout_bpll_div2",
.id = -1,
};
/* CPLL clock output */
struct clk clk_fout_cpll = {
.name = "fout_cpll",
.id = -1,
};
/* MPLL clock output
* No need .ctrlbit, this is always on
*/
struct clk clk_fout_mpll = {
.name = "fout_mpll",
.id = -1,
};
struct clk clk_fout_mpll_div2 = {
.name = "fout_mpll_div2",
.id = -1,
};
/* EPLL clock output */
struct clk clk_fout_epll = {
.name = "fout_epll",
.id = -1,
.ctrlbit = (1 << 31),
};
/* DPLL clock output */
struct clk clk_fout_dpll = {
.name = "fout_dpll",
.id = -1,
.ctrlbit = (1 << 31),
};
/* VPLL clock output */
struct clk clk_fout_vpll = {
.name = "fout_vpll",
.id = -1,
.ctrlbit = (1 << 31),
};
/* Possible clock sources for APLL Mux */
static struct clk *clk_src_apll_list[] = {
[0] = &clk_fin_apll,
[1] = &clk_fout_apll,
};
struct clksrc_sources clk_src_apll = {
.sources = clk_src_apll_list,
.nr_sources = ARRAY_SIZE(clk_src_apll_list),
};
/* Possible clock sources for BPLL Mux */
static struct clk *clk_src_bpll_list[] = {
[0] = &clk_fin_bpll,
[1] = &clk_fout_bpll,
};
struct clksrc_sources clk_src_bpll = {
.sources = clk_src_bpll_list,
.nr_sources = ARRAY_SIZE(clk_src_bpll_list),
};
static struct clk *clk_src_bpll_fout_list[] = {
[0] = &clk_fout_bpll_div2,
[1] = &clk_fout_bpll,
};
struct clksrc_sources clk_src_bpll_fout = {
.sources = clk_src_bpll_fout_list,
.nr_sources = ARRAY_SIZE(clk_src_bpll_fout_list),
};
/* Possible clock sources for CPLL Mux */
static struct clk *clk_src_cpll_list[] = {
[0] = &clk_fin_cpll,
[1] = &clk_fout_cpll,
};
struct clksrc_sources clk_src_cpll = {
.sources = clk_src_cpll_list,
.nr_sources = ARRAY_SIZE(clk_src_cpll_list),
};
/* Possible clock sources for MPLL Mux */
static struct clk *clk_src_mpll_list[] = {
[0] = &clk_fin_mpll,
[1] = &clk_fout_mpll,
};
struct clksrc_sources clk_src_mpll = {
.sources = clk_src_mpll_list,
.nr_sources = ARRAY_SIZE(clk_src_mpll_list),
};
static struct clk *clk_src_mpll_fout_list[] = {
[0] = &clk_fout_mpll_div2,
[1] = &clk_fout_mpll,
};
struct clksrc_sources clk_src_mpll_fout = {
.sources = clk_src_mpll_fout_list,
.nr_sources = ARRAY_SIZE(clk_src_mpll_fout_list),
};
/* Possible clock sources for EPLL Mux */
static struct clk *clk_src_epll_list[] = {
[0] = &clk_fin_epll,
[1] = &clk_fout_epll,
};
struct clksrc_sources clk_src_epll = {
.sources = clk_src_epll_list,
.nr_sources = ARRAY_SIZE(clk_src_epll_list),
};
/* Possible clock sources for DPLL Mux */
static struct clk *clk_src_dpll_list[] = {
[0] = &clk_fin_dpll,
[1] = &clk_fout_dpll,
};
struct clksrc_sources clk_src_dpll = {
.sources = clk_src_dpll_list,
.nr_sources = ARRAY_SIZE(clk_src_dpll_list),
};
struct clk clk_vpll = {
.name = "vpll",
.id = -1,
};
int s5p_gatectrl(void __iomem *reg, struct clk *clk, int enable)
{
unsigned int ctrlbit = clk->ctrlbit;
u32 con;
con = __raw_readl(reg);
con = enable ? (con | ctrlbit) : (con & ~ctrlbit);
__raw_writel(con, reg);
return 0;
}
int s5p_epll_enable(struct clk *clk, int enable)
{
unsigned int ctrlbit = clk->ctrlbit;
unsigned int epll_con = __raw_readl(S5P_EPLL_CON) & ~ctrlbit;
if (enable)
__raw_writel(epll_con | ctrlbit, S5P_EPLL_CON);
else
__raw_writel(epll_con, S5P_EPLL_CON);
return 0;
}
unsigned long s5p_epll_get_rate(struct clk *clk)
{
return clk->rate;
}
int s5p_spdif_set_rate(struct clk *clk, unsigned long rate)
{
struct clk *pclk;
int ret;
pclk = clk_get_parent(clk);
if (IS_ERR(pclk))
return -EINVAL;
ret = pclk->ops->set_rate(pclk, rate);
clk_put(pclk);
return ret;
}
unsigned long s5p_spdif_get_rate(struct clk *clk)
{
struct clk *pclk;
int rate;
pclk = clk_get_parent(clk);
if (IS_ERR(pclk))
return -EINVAL;
rate = pclk->ops->get_rate(pclk);
clk_put(pclk);
return rate;
}
struct clk_ops s5p_sclk_spdif_ops = {
.set_rate = s5p_spdif_set_rate,
.get_rate = s5p_spdif_get_rate,
};
static struct clk *s5p_clks[] __initdata = {
&clk_ext_xtal_mux,
&clk_48m,
&s5p_clk_27m,
&clk_fout_apll,
&clk_fout_mpll,
&clk_fout_epll,
&clk_fout_dpll,
&clk_fout_vpll,
&clk_vpll,
&clk_xusbxti,
};
void __init s5p_register_clocks(unsigned long xtal_freq)
{
int ret;
clk_ext_xtal_mux.rate = xtal_freq;
ret = s3c24xx_register_clocks(s5p_clks, ARRAY_SIZE(s5p_clks));
if (ret > 0)
printk(KERN_ERR "Failed to register s5p clocks\n");
}

81
arch/arm/plat-samsung/s5p-dev-mfc.c
View File

@ -17,56 +17,16 @@
#include <linux/of_fdt.h>
#include <linux/of.h>
#include <plat/mfc.h>
#ifdef CONFIG_SAMSUNG_ATAGS
#include <mach/map.h>
#include <mach/irqs.h>
#include <plat/devs.h>
static struct resource s5p_mfc_resource[] = {
[0] = DEFINE_RES_MEM(S5P_PA_MFC, SZ_64K),
[1] = DEFINE_RES_IRQ(IRQ_MFC),
};
struct platform_device s5p_device_mfc = {
.name = "s5p-mfc",
.id = -1,
.num_resources = ARRAY_SIZE(s5p_mfc_resource),
.resource = s5p_mfc_resource,
};
/*
* MFC hardware has 2 memory interfaces which are modelled as two separate
* platform devices to let dma-mapping distinguish between them.
*
* MFC parent device (s5p_device_mfc) must be registered before memory
* interface specific devices (s5p_device_mfc_l and s5p_device_mfc_r).
*/
struct platform_device s5p_device_mfc_l = {
.name = "s5p-mfc-l",
.id = -1,
.dev = {
.parent = &s5p_device_mfc.dev,
.dma_mask = &s5p_device_mfc_l.dev.coherent_dma_mask,
.coherent_dma_mask = DMA_BIT_MASK(32),
},
};
struct platform_device s5p_device_mfc_r = {
.name = "s5p-mfc-r",
.id = -1,
.dev = {
.parent = &s5p_device_mfc.dev,
.dma_mask = &s5p_device_mfc_r.dev.coherent_dma_mask,
.coherent_dma_mask = DMA_BIT_MASK(32),
},
};
#else
static struct platform_device s5p_device_mfc_l;
static struct platform_device s5p_device_mfc_r;
#endif
struct s5p_mfc_dt_meminfo {
unsigned long loff;
unsigned long lsize;
unsigned long roff;
unsigned long rsize;
char *compatible;
};
struct s5p_mfc_reserved_mem {
phys_addr_t base;
@ -77,7 +37,7 @@ struct s5p_mfc_reserved_mem {
static struct s5p_mfc_reserved_mem s5p_mfc_mem[2] __initdata;
void __init s5p_mfc_reserve_mem(phys_addr_t rbase, unsigned int rsize,
static void __init s5p_mfc_reserve_mem(phys_addr_t rbase, unsigned int rsize,
phys_addr_t lbase, unsigned int lsize)
{
int i;
@ -100,28 +60,6 @@ void __init s5p_mfc_reserve_mem(phys_addr_t rbase, unsigned int rsize,
}
}
#ifdef CONFIG_SAMSUNG_ATAGS
static int __init s5p_mfc_memory_init(void)
{
int i;
for (i = 0; i < ARRAY_SIZE(s5p_mfc_mem); i++) {
struct s5p_mfc_reserved_mem *area = &s5p_mfc_mem[i];
if (!area->base)
continue;
if (dma_declare_coherent_memory(area->dev, area->base,
area->base, area->size,
DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE) == 0)
printk(KERN_ERR "Failed to declare coherent memory for MFC device (%ld bytes at 0x%08lx)\n",
area->size, (unsigned long) area->base);
}
return 0;
}
device_initcall(s5p_mfc_memory_init);
#endif
#ifdef CONFIG_OF
int __init s5p_fdt_alloc_mfc_mem(unsigned long node, const char *uname,
int depth, void *data)
{
@ -154,4 +92,3 @@ int __init s5p_fdt_alloc_mfc_mem(unsigned long node, const char *uname,
return 1;
}
#endif

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