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mtd: nand: denali: use flag instead of register macro for direction

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It is not a good idea to re-use macros that represent a specific
register bit field for the transfer direction.

It is true that bit 8 indicates the direction for the MAP10 pipeline
operation and the data DMA operation, but this is not valid across
the IP.

Use a simple flag (write: 1, read: 0) for the direction.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
This commit is contained in:
Masahiro Yamada 2017-06-13 22:45:44 +09:00 committed by Boris Brezillon
parent 00fc615fd6
commit 96a376bd93
1 changed files with 17 additions and 19 deletions
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36
drivers/mtd/nand/denali.c
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@ -63,9 +63,6 @@ static inline struct denali_nand_info *mtd_to_denali(struct mtd_info *mtd)
#define MAIN_ACCESS 0x42 #define MAIN_ACCESS 0x42
#define MAIN_SPARE_ACCESS 0x43 #define MAIN_SPARE_ACCESS 0x43
#define DENALI_READ 0
#define DENALI_WRITE 0x100
/* /*
* this is a helper macro that allows us to * this is a helper macro that allows us to
* format the bank into the proper bits for the controller * format the bank into the proper bits for the controller
@ -339,7 +336,7 @@ static int denali_dev_ready(struct mtd_info *mtd)
*/ */
static int denali_send_pipeline_cmd(struct denali_nand_info *denali, int page, static int denali_send_pipeline_cmd(struct denali_nand_info *denali, int page,
bool ecc_en, bool transfer_spare, bool ecc_en, bool transfer_spare,
int access_type, int op) int access_type, int write)
{ {
int status = PASS; int status = PASS;
uint32_t addr, cmd; uint32_t addr, cmd;
@ -350,17 +347,17 @@ static int denali_send_pipeline_cmd(struct denali_nand_info *denali, int page,
addr = BANK(denali->flash_bank) | page; addr = BANK(denali->flash_bank) | page;
if (op == DENALI_WRITE && access_type != SPARE_ACCESS) { if (write && access_type != SPARE_ACCESS) {
cmd = MODE_01 | addr; cmd = MODE_01 | addr;
iowrite32(cmd, denali->flash_mem); iowrite32(cmd, denali->flash_mem);
} else if (op == DENALI_WRITE && access_type == SPARE_ACCESS) { } else if (write && access_type == SPARE_ACCESS) {
/* read spare area */ /* read spare area */
cmd = MODE_10 | addr; cmd = MODE_10 | addr;
index_addr(denali, cmd, access_type); index_addr(denali, cmd, access_type);
cmd = MODE_01 | addr; cmd = MODE_01 | addr;
iowrite32(cmd, denali->flash_mem); iowrite32(cmd, denali->flash_mem);
} else if (op == DENALI_READ) { } else {
/* setup page read request for access type */ /* setup page read request for access type */
cmd = MODE_10 | addr; cmd = MODE_10 | addr;
index_addr(denali, cmd, access_type); index_addr(denali, cmd, access_type);
@ -422,7 +419,7 @@ static int write_oob_data(struct mtd_info *mtd, uint8_t *buf, int page)
int status = 0; int status = 0;
if (denali_send_pipeline_cmd(denali, page, false, false, SPARE_ACCESS, if (denali_send_pipeline_cmd(denali, page, false, false, SPARE_ACCESS,
DENALI_WRITE) == PASS) { 1) == PASS) {
write_data_to_flash_mem(denali, buf, mtd->oobsize); write_data_to_flash_mem(denali, buf, mtd->oobsize);
/* wait for operation to complete */ /* wait for operation to complete */
@ -447,7 +444,7 @@ static void read_oob_data(struct mtd_info *mtd, uint8_t *buf, int page)
uint32_t irq_status, addr, cmd; uint32_t irq_status, addr, cmd;
if (denali_send_pipeline_cmd(denali, page, false, true, SPARE_ACCESS, if (denali_send_pipeline_cmd(denali, page, false, true, SPARE_ACCESS,
DENALI_READ) == PASS) { 0) == PASS) {
read_data_from_flash_mem(denali, buf, mtd->oobsize); read_data_from_flash_mem(denali, buf, mtd->oobsize);
/* /*
@ -633,7 +630,7 @@ static void denali_enable_dma(struct denali_nand_info *denali, bool en)
} }
static void denali_setup_dma64(struct denali_nand_info *denali, static void denali_setup_dma64(struct denali_nand_info *denali,
dma_addr_t dma_addr, int page, int op) dma_addr_t dma_addr, int page, int write)
{ {
uint32_t mode; uint32_t mode;
const int page_count = 1; const int page_count = 1;
@ -646,7 +643,8 @@ static void denali_setup_dma64(struct denali_nand_info *denali,
* 1. setup transfer type, interrupt when complete, * 1. setup transfer type, interrupt when complete,
* burst len = 64 bytes, the number of pages * burst len = 64 bytes, the number of pages
*/ */
index_addr(denali, mode, 0x01002000 | (64 << 16) | op | page_count); index_addr(denali, mode,
0x01002000 | (64 << 16) | (write << 8) | page_count);
/* 2. set memory low address */ /* 2. set memory low address */
index_addr(denali, mode, dma_addr); index_addr(denali, mode, dma_addr);
@ -656,7 +654,7 @@ static void denali_setup_dma64(struct denali_nand_info *denali,
} }
static void denali_setup_dma32(struct denali_nand_info *denali, static void denali_setup_dma32(struct denali_nand_info *denali,
dma_addr_t dma_addr, int page, int op) dma_addr_t dma_addr, int page, int write)
{ {
uint32_t mode; uint32_t mode;
const int page_count = 1; const int page_count = 1;
@ -666,7 +664,7 @@ static void denali_setup_dma32(struct denali_nand_info *denali,
/* DMA is a four step process */ /* DMA is a four step process */
/* 1. setup transfer type and # of pages */ /* 1. setup transfer type and # of pages */
index_addr(denali, mode | page, 0x2000 | op | page_count); index_addr(denali, mode | page, 0x2000 | (write << 8) | page_count);
/* 2. set memory high address bits 23:8 */ /* 2. set memory high address bits 23:8 */
index_addr(denali, mode | ((dma_addr >> 16) << 8), 0x2200); index_addr(denali, mode | ((dma_addr >> 16) << 8), 0x2200);
@ -679,12 +677,12 @@ static void denali_setup_dma32(struct denali_nand_info *denali,
} }
static void denali_setup_dma(struct denali_nand_info *denali, static void denali_setup_dma(struct denali_nand_info *denali,
dma_addr_t dma_addr, int page, int op) dma_addr_t dma_addr, int page, int write)
{ {
if (denali->caps & DENALI_CAP_DMA_64BIT) if (denali->caps & DENALI_CAP_DMA_64BIT)
denali_setup_dma64(denali, dma_addr, page, op); denali_setup_dma64(denali, dma_addr, page, write);
else else
denali_setup_dma32(denali, dma_addr, page, op); denali_setup_dma32(denali, dma_addr, page, write);
} }
/* /*
@ -723,7 +721,7 @@ static int write_page(struct mtd_info *mtd, struct nand_chip *chip,
denali_reset_irq(denali); denali_reset_irq(denali);
denali_enable_dma(denali, true); denali_enable_dma(denali, true);
denali_setup_dma(denali, addr, page, DENALI_WRITE); denali_setup_dma(denali, addr, page, 1);
/* wait for operation to complete */ /* wait for operation to complete */
irq_status = denali_wait_for_irq(denali, irq_mask); irq_status = denali_wait_for_irq(denali, irq_mask);
@ -805,7 +803,7 @@ static int denali_read_page(struct mtd_info *mtd, struct nand_chip *chip,
dma_sync_single_for_device(denali->dev, addr, size, DMA_FROM_DEVICE); dma_sync_single_for_device(denali->dev, addr, size, DMA_FROM_DEVICE);
denali_reset_irq(denali); denali_reset_irq(denali);
denali_setup_dma(denali, addr, page, DENALI_READ); denali_setup_dma(denali, addr, page, 0);
/* wait for operation to complete */ /* wait for operation to complete */
irq_status = denali_wait_for_irq(denali, irq_mask); irq_status = denali_wait_for_irq(denali, irq_mask);
@ -848,7 +846,7 @@ static int denali_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
dma_sync_single_for_device(denali->dev, addr, size, DMA_FROM_DEVICE); dma_sync_single_for_device(denali->dev, addr, size, DMA_FROM_DEVICE);
denali_reset_irq(denali); denali_reset_irq(denali);
denali_setup_dma(denali, addr, page, DENALI_READ); denali_setup_dma(denali, addr, page, 0);
/* wait for operation to complete */ /* wait for operation to complete */
irq_status = denali_wait_for_irq(denali, irq_mask); irq_status = denali_wait_for_irq(denali, irq_mask);