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mmc: mmci: Add Qualcomm specific register defines.

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This patch adds a Qualcomm SD Card controller specific register variations
to header file. Qualcomm SDCC controller is pl180, with slight changes in
the register layout from standard pl180 register set.

Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
This commit is contained in:
Srinivas Kandagatla 2014-06-02 10:08:48 +01:00 committed by Ulf Hansson
parent c4a3576916
commit 9681a4e882
1 changed files with 17 additions and 0 deletions
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17
drivers/mmc/host/mmci.h
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@ -41,6 +41,15 @@
/* Modified PL180 on Versatile Express platform */
#define MCI_ARM_HWFCEN (1 << 12)
/* Modified on Qualcomm Integrations */
#define MCI_QCOM_CLK_WIDEBUS_8 (BIT(10) | BIT(11))
#define MCI_QCOM_CLK_FLOWENA BIT(12)
#define MCI_QCOM_CLK_INVERTOUT BIT(13)
/* select in latch data and command in */
#define MCI_QCOM_CLK_SELECT_IN_FBCLK BIT(15)
#define MCI_QCOM_CLK_SELECT_IN_DDR_MODE (BIT(14) | BIT(15))
#define MMCIARGUMENT 0x008
#define MMCICOMMAND 0x00c
#define MCI_CPSM_RESPONSE (1 << 6)
@ -54,6 +63,14 @@
#define MCI_ST_NIEN (1 << 13)
#define MCI_ST_CE_ATACMD (1 << 14)
/* Modified on Qualcomm Integrations */
#define MCI_QCOM_CSPM_DATCMD BIT(12)
#define MCI_QCOM_CSPM_MCIABORT BIT(13)
#define MCI_QCOM_CSPM_CCSENABLE BIT(14)
#define MCI_QCOM_CSPM_CCSDISABLE BIT(15)
#define MCI_QCOM_CSPM_AUTO_CMD19 BIT(16)
#define MCI_QCOM_CSPM_AUTO_CMD21 BIT(21)
#define MMCIRESPCMD 0x010
#define MMCIRESPONSE0 0x014
#define MMCIRESPONSE1 0x018