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drm/amdgpu: Update pitch on page flips without DC as well
DC already handles this correctly since amdgpu minor version 31. Bump the minor version again so that xf86-video-amdgpu can take advantage of this working without DC as well now. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -79,9 +79,10 @@
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* - 3.31.0 - Add support for per-flip tiling attribute changes with DC
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* - 3.32.0 - Add syncobj timeline support to AMDGPU_CS.
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* - 3.33.0 - Fixes for GDS ENOMEM failures in AMDGPU_CS.
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* - 3.34.0 - Non-DC can flip correctly between buffers with different pitches
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*/
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#define KMS_DRIVER_MAJOR 3
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#define KMS_DRIVER_MINOR 33
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#define KMS_DRIVER_MINOR 34
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#define KMS_DRIVER_PATCHLEVEL 0
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#define AMDGPU_MAX_TIMEOUT_PARAM_LENTH 256
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@ -236,6 +236,7 @@ static void dce_v10_0_page_flip(struct amdgpu_device *adev,
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int crtc_id, u64 crtc_base, bool async)
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{
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struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
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struct drm_framebuffer *fb = amdgpu_crtc->base.primary->fb;
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u32 tmp;
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/* flip at hsync for async, default is vsync */
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@ -243,6 +244,9 @@ static void dce_v10_0_page_flip(struct amdgpu_device *adev,
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tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL,
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GRPH_SURFACE_UPDATE_H_RETRACE_EN, async ? 1 : 0);
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WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
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/* update pitch */
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WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset,
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fb->pitches[0] / fb->format->cpp[0]);
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/* update the primary scanout address */
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WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
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upper_32_bits(crtc_base));
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@ -254,6 +254,7 @@ static void dce_v11_0_page_flip(struct amdgpu_device *adev,
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int crtc_id, u64 crtc_base, bool async)
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{
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struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
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struct drm_framebuffer *fb = amdgpu_crtc->base.primary->fb;
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u32 tmp;
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/* flip immediate for async, default is vsync */
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@ -261,6 +262,9 @@ static void dce_v11_0_page_flip(struct amdgpu_device *adev,
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tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL,
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GRPH_SURFACE_UPDATE_IMMEDIATE_EN, async ? 1 : 0);
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WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
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/* update pitch */
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WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset,
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fb->pitches[0] / fb->format->cpp[0]);
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/* update the scanout addresses */
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WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
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upper_32_bits(crtc_base));
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@ -191,10 +191,14 @@ static void dce_v6_0_page_flip(struct amdgpu_device *adev,
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int crtc_id, u64 crtc_base, bool async)
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{
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struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
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struct drm_framebuffer *fb = amdgpu_crtc->base.primary->fb;
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/* flip at hsync for async, default is vsync */
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WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, async ?
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GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_H_RETRACE_EN_MASK : 0);
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/* update pitch */
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WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset,
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fb->pitches[0] / fb->format->cpp[0]);
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/* update the scanout addresses */
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WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
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upper_32_bits(crtc_base));
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@ -184,10 +184,14 @@ static void dce_v8_0_page_flip(struct amdgpu_device *adev,
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int crtc_id, u64 crtc_base, bool async)
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{
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struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
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struct drm_framebuffer *fb = amdgpu_crtc->base.primary->fb;
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/* flip at hsync for async, default is vsync */
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WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, async ?
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GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_H_RETRACE_EN_MASK : 0);
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/* update pitch */
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WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset,
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fb->pitches[0] / fb->format->cpp[0]);
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/* update the primary scanout addresses */
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WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
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upper_32_bits(crtc_base));
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