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[ARM] Fix SA110/SA1100 cache flushing
We had two implementations for flushing the cache, which meant StrongARM caches weren't being correctly flushed. Fix this by always using the v4wb_flush_kern_cache_all method, rather than duplicating it. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Russell King
Russell King
parent
f1dc24d53e
commit
95f3df6bcb
@ -10,7 +10,7 @@
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#include <linux/config.h>
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#include <linux/linkage.h>
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#include <linux/init.h>
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#include <asm/hardware.h>
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#include <asm/memory.h>
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#include <asm/page.h>
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#include "proc-macros.S"
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@ -46,6 +46,11 @@
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*/
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#define CACHE_DLIMIT (CACHE_DSIZE * 4)
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.data
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flush_base:
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.long FLUSH_BASE
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.text
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/*
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* flush_user_cache_all()
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*
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@ -63,11 +68,21 @@ ENTRY(v4wb_flush_kern_cache_all)
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mov ip, #0
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mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
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__flush_whole_cache:
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mov r0, #FLUSH_BASE
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add r1, r0, #CACHE_DSIZE
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1: ldr r2, [r0], #32
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cmp r0, r1
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ldr r3, =flush_base
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ldr r1, [r3, #0]
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eor r1, r1, #CACHE_DSIZE
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str r1, [r3, #0]
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add r2, r1, #CACHE_DSIZE
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1: ldr r3, [r1], #32
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cmp r1, r2
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blo 1b
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#ifdef FLUSH_BASE_MINICACHE
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add r2, r2, #FLUSH_BASE_MINICACHE - FLUSH_BASE
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sub r1, r2, #512 @ only 512 bytes
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1: ldr r3, [r1], #32
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cmp r1, r2
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blo 1b
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#endif
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mcr p15, 0, ip, c7, c10, 4 @ drain write buffer
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mov pc, lr
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@ -82,6 +97,7 @@ __flush_whole_cache:
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* - flags - vma_area_struct flags describing address space
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*/
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ENTRY(v4wb_flush_user_cache_range)
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mov ip, #0
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sub r3, r1, r0 @ calculate total size
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tst r2, #VM_EXEC @ executable region?
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mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
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@ -26,22 +26,7 @@
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* the cache line size of the I and D cache
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*/
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#define DCACHELINESIZE 32
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#define FLUSH_OFFSET 32768
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.macro flush_110_dcache rd, ra, re
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ldr \rd, =flush_base
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ldr \ra, [\rd]
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eor \ra, \ra, #FLUSH_OFFSET
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str \ra, [\rd]
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add \re, \ra, #16384 @ only necessary for 16k
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1001: ldr \rd, [\ra], #DCACHELINESIZE
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teq \re, \ra
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bne 1001b
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.endm
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.data
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flush_base:
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.long FLUSH_BASE
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.text
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/*
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@ -145,13 +130,11 @@ ENTRY(cpu_sa110_dcache_clean_area)
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*/
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.align 5
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ENTRY(cpu_sa110_switch_mm)
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flush_110_dcache r3, ip, r1
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mov r1, #0
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mcr p15, 0, r1, c7, c5, 0 @ invalidate I cache
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mcr p15, 0, r1, c7, c10, 4 @ drain WB
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str lr, [sp, #-4]!
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bl v4wb_flush_kern_cache_all @ clears IP
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mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
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mcr p15, 0, r1, c8, c7, 0 @ invalidate I & D TLBs
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mov pc, lr
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mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
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ldr pc, [sp], #4
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/*
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* cpu_sa110_set_pte(ptep, pte)
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@ -30,30 +30,6 @@
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* the cache line size of the I and D cache
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*/
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#define DCACHELINESIZE 32
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#define FLUSH_OFFSET 32768
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.macro flush_1100_dcache rd, ra, re
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ldr \rd, =flush_base
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ldr \ra, [\rd]
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eor \ra, \ra, #FLUSH_OFFSET
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str \ra, [\rd]
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add \re, \ra, #8192 @ only necessary for 8k
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1001: ldr \rd, [\ra], #DCACHELINESIZE
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teq \re, \ra
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bne 1001b
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#ifdef FLUSH_BASE_MINICACHE
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add \ra, \ra, #FLUSH_BASE_MINICACHE - FLUSH_BASE
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add \re, \ra, #512 @ only 512 bytes
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1002: ldr \rd, [\ra], #DCACHELINESIZE
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teq \re, \ra
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bne 1002b
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#endif
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.endm
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.data
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flush_base:
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.long FLUSH_BASE
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.text
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__INIT
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@ -79,9 +55,8 @@ ENTRY(cpu_sa1100_proc_fin)
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stmfd sp!, {lr}
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mov ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
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msr cpsr_c, ip
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flush_1100_dcache r0, r1, r2 @ clean caches
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mov r0, #0
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mcr p15, 0, r0, c15, c2, 2 @ Disable clock switching
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bl v4wb_flush_kern_cache_all
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mcr p15, 0, ip, c15, c2, 2 @ Disable clock switching
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mrc p15, 0, r0, c1, c0, 0 @ ctrl register
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bic r0, r0, #0x1000 @ ...i............
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bic r0, r0, #0x000e @ ............wca.
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@ -167,14 +142,12 @@ ENTRY(cpu_sa1100_dcache_clean_area)
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*/
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.align 5
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ENTRY(cpu_sa1100_switch_mm)
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flush_1100_dcache r3, ip, r1
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mov ip, #0
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mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
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str lr, [sp, #-4]!
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bl v4wb_flush_kern_cache_all @ clears IP
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mcr p15, 0, ip, c9, c0, 0 @ invalidate RB
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mcr p15, 0, ip, c7, c10, 4 @ drain WB
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mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
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mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
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mov pc, lr
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ldr pc, [sp], #4
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/*
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* cpu_sa1100_set_pte(ptep, pte)
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