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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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arm64: dts: xilinx: Add the power nodes for zynqmp
Add power domain nodes for zynqmp. Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This commit is contained in:
Rajan Vaja
Michal Simek
parent
4406486805
commit
959b86ae37
@ -12,6 +12,8 @@
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* the License, or (at your option) any later version.
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*/
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#include <dt-bindings/power/xlnx-zynqmp-power.h>
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/ {
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compatible = "xlnx,zynqmp";
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#address-cells = <2>;
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@ -118,8 +120,15 @@ psci {
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firmware {
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zynqmp_firmware: zynqmp-firmware {
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compatible = "xlnx,zynqmp-firmware";
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#power-domain-cells = <1>;
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method = "smc";
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zynqmp_power: zynqmp-power {
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compatible = "xlnx,zynqmp-power";
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interrupt-parent = <&gic>;
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interrupts = <0 35 4>;
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};
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zynqmp_clk: clock-controller {
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u-boot,dm-pre-reloc;
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#clock-cells = <1>;
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@ -203,6 +212,7 @@ can0: can@ff060000 {
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interrupt-parent = <&gic>;
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tx-fifo-depth = <0x40>;
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rx-fifo-depth = <0x40>;
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power-domains = <&zynqmp_firmware PD_CAN_0>;
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};
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can1: can@ff070000 {
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@ -214,6 +224,7 @@ can1: can@ff070000 {
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interrupt-parent = <&gic>;
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tx-fifo-depth = <0x40>;
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rx-fifo-depth = <0x40>;
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power-domains = <&zynqmp_firmware PD_CAN_1>;
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};
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cci: cci@fd6e0000 {
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@ -244,6 +255,7 @@ fpd_dma_chan1: dma@fd500000 {
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interrupts = <0 124 4>;
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clock-names = "clk_main", "clk_apb";
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xlnx,bus-width = <128>;
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power-domains = <&zynqmp_firmware PD_GDMA>;
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};
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fpd_dma_chan2: dma@fd510000 {
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@ -254,6 +266,7 @@ fpd_dma_chan2: dma@fd510000 {
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interrupts = <0 125 4>;
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clock-names = "clk_main", "clk_apb";
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xlnx,bus-width = <128>;
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power-domains = <&zynqmp_firmware PD_GDMA>;
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};
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fpd_dma_chan3: dma@fd520000 {
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@ -264,6 +277,7 @@ fpd_dma_chan3: dma@fd520000 {
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interrupts = <0 126 4>;
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clock-names = "clk_main", "clk_apb";
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xlnx,bus-width = <128>;
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power-domains = <&zynqmp_firmware PD_GDMA>;
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};
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fpd_dma_chan4: dma@fd530000 {
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@ -274,6 +288,7 @@ fpd_dma_chan4: dma@fd530000 {
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interrupts = <0 127 4>;
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clock-names = "clk_main", "clk_apb";
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xlnx,bus-width = <128>;
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power-domains = <&zynqmp_firmware PD_GDMA>;
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};
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fpd_dma_chan5: dma@fd540000 {
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@ -284,6 +299,7 @@ fpd_dma_chan5: dma@fd540000 {
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interrupts = <0 128 4>;
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clock-names = "clk_main", "clk_apb";
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xlnx,bus-width = <128>;
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power-domains = <&zynqmp_firmware PD_GDMA>;
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};
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fpd_dma_chan6: dma@fd550000 {
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@ -294,6 +310,7 @@ fpd_dma_chan6: dma@fd550000 {
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interrupts = <0 129 4>;
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clock-names = "clk_main", "clk_apb";
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xlnx,bus-width = <128>;
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power-domains = <&zynqmp_firmware PD_GDMA>;
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};
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fpd_dma_chan7: dma@fd560000 {
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@ -304,6 +321,7 @@ fpd_dma_chan7: dma@fd560000 {
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interrupts = <0 130 4>;
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clock-names = "clk_main", "clk_apb";
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xlnx,bus-width = <128>;
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power-domains = <&zynqmp_firmware PD_GDMA>;
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};
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fpd_dma_chan8: dma@fd570000 {
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@ -314,6 +332,7 @@ fpd_dma_chan8: dma@fd570000 {
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interrupts = <0 131 4>;
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clock-names = "clk_main", "clk_apb";
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xlnx,bus-width = <128>;
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power-domains = <&zynqmp_firmware PD_GDMA>;
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};
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/* LPDDMA default allows only secured access. inorder to enable
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@ -328,6 +347,7 @@ lpd_dma_chan1: dma@ffa80000 {
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interrupts = <0 77 4>;
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clock-names = "clk_main", "clk_apb";
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xlnx,bus-width = <64>;
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power-domains = <&zynqmp_firmware PD_ADMA>;
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};
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lpd_dma_chan2: dma@ffa90000 {
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@ -338,6 +358,7 @@ lpd_dma_chan2: dma@ffa90000 {
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interrupts = <0 78 4>;
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clock-names = "clk_main", "clk_apb";
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xlnx,bus-width = <64>;
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power-domains = <&zynqmp_firmware PD_ADMA>;
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};
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lpd_dma_chan3: dma@ffaa0000 {
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@ -348,6 +369,7 @@ lpd_dma_chan3: dma@ffaa0000 {
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interrupts = <0 79 4>;
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clock-names = "clk_main", "clk_apb";
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xlnx,bus-width = <64>;
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power-domains = <&zynqmp_firmware PD_ADMA>;
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};
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lpd_dma_chan4: dma@ffab0000 {
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@ -358,6 +380,7 @@ lpd_dma_chan4: dma@ffab0000 {
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interrupts = <0 80 4>;
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clock-names = "clk_main", "clk_apb";
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xlnx,bus-width = <64>;
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power-domains = <&zynqmp_firmware PD_ADMA>;
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};
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lpd_dma_chan5: dma@ffac0000 {
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@ -368,6 +391,7 @@ lpd_dma_chan5: dma@ffac0000 {
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interrupts = <0 81 4>;
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clock-names = "clk_main", "clk_apb";
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xlnx,bus-width = <64>;
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power-domains = <&zynqmp_firmware PD_ADMA>;
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};
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lpd_dma_chan6: dma@ffad0000 {
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@ -378,6 +402,7 @@ lpd_dma_chan6: dma@ffad0000 {
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interrupts = <0 82 4>;
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clock-names = "clk_main", "clk_apb";
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xlnx,bus-width = <64>;
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power-domains = <&zynqmp_firmware PD_ADMA>;
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};
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lpd_dma_chan7: dma@ffae0000 {
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@ -388,6 +413,7 @@ lpd_dma_chan7: dma@ffae0000 {
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interrupts = <0 83 4>;
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clock-names = "clk_main", "clk_apb";
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xlnx,bus-width = <64>;
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power-domains = <&zynqmp_firmware PD_ADMA>;
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};
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lpd_dma_chan8: dma@ffaf0000 {
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@ -398,6 +424,7 @@ lpd_dma_chan8: dma@ffaf0000 {
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interrupts = <0 84 4>;
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clock-names = "clk_main", "clk_apb";
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xlnx,bus-width = <64>;
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power-domains = <&zynqmp_firmware PD_ADMA>;
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};
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mc: memory-controller@fd070000 {
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@ -416,6 +443,7 @@ gem0: ethernet@ff0b0000 {
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clock-names = "pclk", "hclk", "tx_clk";
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#address-cells = <1>;
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#size-cells = <0>;
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power-domains = <&zynqmp_firmware PD_ETH_0>;
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};
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gem1: ethernet@ff0c0000 {
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@ -427,6 +455,7 @@ gem1: ethernet@ff0c0000 {
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clock-names = "pclk", "hclk", "tx_clk";
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#address-cells = <1>;
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#size-cells = <0>;
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power-domains = <&zynqmp_firmware PD_ETH_1>;
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};
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gem2: ethernet@ff0d0000 {
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@ -438,6 +467,7 @@ gem2: ethernet@ff0d0000 {
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clock-names = "pclk", "hclk", "tx_clk";
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#address-cells = <1>;
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#size-cells = <0>;
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power-domains = <&zynqmp_firmware PD_ETH_2>;
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};
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gem3: ethernet@ff0e0000 {
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@ -449,6 +479,7 @@ gem3: ethernet@ff0e0000 {
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clock-names = "pclk", "hclk", "tx_clk";
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#address-cells = <1>;
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#size-cells = <0>;
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power-domains = <&zynqmp_firmware PD_ETH_3>;
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};
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gpio: gpio@ff0a0000 {
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@ -461,6 +492,7 @@ gpio: gpio@ff0a0000 {
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x0 0xff0a0000 0x0 0x1000>;
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power-domains = <&zynqmp_firmware PD_GPIO>;
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};
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i2c0: i2c@ff020000 {
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@ -471,6 +503,7 @@ i2c0: i2c@ff020000 {
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reg = <0x0 0xff020000 0x0 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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power-domains = <&zynqmp_firmware PD_I2C_0>;
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};
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i2c1: i2c@ff030000 {
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@ -481,6 +514,7 @@ i2c1: i2c@ff030000 {
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reg = <0x0 0xff030000 0x0 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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power-domains = <&zynqmp_firmware PD_I2C_1>;
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};
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pcie: pcie@fd0e0000 {
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@ -512,6 +546,7 @@ pcie: pcie@fd0e0000 {
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<0x0 0x0 0x0 0x2 &pcie_intc 0x2>,
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<0x0 0x0 0x0 0x3 &pcie_intc 0x3>,
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<0x0 0x0 0x0 0x4 &pcie_intc 0x4>;
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power-domains = <&zynqmp_firmware PD_PCIE>;
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pcie_intc: legacy-interrupt-controller {
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interrupt-controller;
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#address-cells = <0>;
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@ -535,6 +570,7 @@ sata: ahci@fd0c0000 {
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reg = <0x0 0xfd0c0000 0x0 0x2000>;
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interrupt-parent = <&gic>;
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interrupts = <0 133 4>;
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power-domains = <&zynqmp_firmware PD_SATA>;
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};
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sdhci0: mmc@ff160000 {
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@ -546,6 +582,7 @@ sdhci0: mmc@ff160000 {
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clock-names = "clk_xin", "clk_ahb";
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#clock-cells = <1>;
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clock-output-names = "clk_out_sd0", "clk_in_sd0";
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power-domains = <&zynqmp_firmware PD_SD_0>;
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};
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sdhci1: mmc@ff170000 {
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@ -557,6 +594,7 @@ sdhci1: mmc@ff170000 {
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clock-names = "clk_xin", "clk_ahb";
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#clock-cells = <1>;
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clock-output-names = "clk_out_sd1", "clk_in_sd1";
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power-domains = <&zynqmp_firmware PD_SD_1>;
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};
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smmu: smmu@fd800000 {
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@ -581,6 +619,7 @@ spi0: spi@ff040000 {
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clock-names = "ref_clk", "pclk";
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#address-cells = <1>;
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#size-cells = <0>;
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power-domains = <&zynqmp_firmware PD_SPI_0>;
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};
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spi1: spi@ff050000 {
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@ -592,6 +631,7 @@ spi1: spi@ff050000 {
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clock-names = "ref_clk", "pclk";
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#address-cells = <1>;
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#size-cells = <0>;
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power-domains = <&zynqmp_firmware PD_SPI_1>;
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};
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ttc0: timer@ff110000 {
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@ -601,6 +641,7 @@ ttc0: timer@ff110000 {
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interrupts = <0 36 4>, <0 37 4>, <0 38 4>;
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reg = <0x0 0xff110000 0x0 0x1000>;
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timer-width = <32>;
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power-domains = <&zynqmp_firmware PD_TTC_0>;
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};
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ttc1: timer@ff120000 {
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@ -610,6 +651,7 @@ ttc1: timer@ff120000 {
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interrupts = <0 39 4>, <0 40 4>, <0 41 4>;
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reg = <0x0 0xff120000 0x0 0x1000>;
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timer-width = <32>;
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power-domains = <&zynqmp_firmware PD_TTC_1>;
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};
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ttc2: timer@ff130000 {
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@ -619,6 +661,7 @@ ttc2: timer@ff130000 {
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interrupts = <0 42 4>, <0 43 4>, <0 44 4>;
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reg = <0x0 0xff130000 0x0 0x1000>;
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timer-width = <32>;
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power-domains = <&zynqmp_firmware PD_TTC_2>;
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};
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ttc3: timer@ff140000 {
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@ -628,6 +671,7 @@ ttc3: timer@ff140000 {
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interrupts = <0 45 4>, <0 46 4>, <0 47 4>;
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reg = <0x0 0xff140000 0x0 0x1000>;
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timer-width = <32>;
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power-domains = <&zynqmp_firmware PD_TTC_3>;
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};
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uart0: serial@ff000000 {
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@ -637,6 +681,7 @@ uart0: serial@ff000000 {
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interrupts = <0 21 4>;
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reg = <0x0 0xff000000 0x0 0x1000>;
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clock-names = "uart_clk", "pclk";
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power-domains = <&zynqmp_firmware PD_UART_0>;
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};
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uart1: serial@ff010000 {
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@ -646,6 +691,7 @@ uart1: serial@ff010000 {
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interrupts = <0 22 4>;
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reg = <0x0 0xff010000 0x0 0x1000>;
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clock-names = "uart_clk", "pclk";
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power-domains = <&zynqmp_firmware PD_UART_1>;
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};
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usb0: usb@fe200000 {
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@ -655,6 +701,7 @@ usb0: usb@fe200000 {
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interrupts = <0 65 4>;
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reg = <0x0 0xfe200000 0x0 0x40000>;
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clock-names = "clk_xin", "clk_ahb";
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power-domains = <&zynqmp_firmware PD_USB_0>;
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};
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usb1: usb@fe300000 {
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@ -664,6 +711,7 @@ usb1: usb@fe300000 {
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interrupts = <0 70 4>;
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reg = <0x0 0xfe300000 0x0 0x40000>;
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clock-names = "clk_xin", "clk_ahb";
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power-domains = <&zynqmp_firmware PD_USB_1>;
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};
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watchdog0: watchdog@fd4d0000 {
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