mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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ASoC: Convert WM8955 to direct regmap API usage
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
This commit is contained in:
Mark Brown
parent
9887cb9e65
commit
95860fdf0f
@ -16,6 +16,7 @@
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#include <linux/delay.h>
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#include <linux/pm.h>
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#include <linux/i2c.h>
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#include <linux/regmap.h>
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#include <linux/regulator/consumer.h>
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#include <linux/slab.h>
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#include <sound/core.h>
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@ -38,7 +39,7 @@ static const char *wm8955_supply_names[WM8955_NUM_SUPPLIES] = {
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/* codec private data */
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struct wm8955_priv {
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enum snd_soc_control_type control_type;
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struct regmap *regmap;
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unsigned int mclk_rate;
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@ -48,69 +49,85 @@ struct wm8955_priv {
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struct regulator_bulk_data supplies[WM8955_NUM_SUPPLIES];
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};
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static const u16 wm8955_reg[WM8955_MAX_REGISTER + 1] = {
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0x0000, /* R0 */
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0x0000, /* R1 */
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0x0079, /* R2 - LOUT1 volume */
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0x0079, /* R3 - ROUT1 volume */
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0x0000, /* R4 */
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0x0008, /* R5 - DAC Control */
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0x0000, /* R6 */
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0x000A, /* R7 - Audio Interface */
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0x0000, /* R8 - Sample Rate */
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0x0000, /* R9 */
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0x00FF, /* R10 - Left DAC volume */
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0x00FF, /* R11 - Right DAC volume */
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0x000F, /* R12 - Bass control */
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0x000F, /* R13 - Treble control */
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0x0000, /* R14 */
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0x0000, /* R15 - Reset */
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0x0000, /* R16 */
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0x0000, /* R17 */
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0x0000, /* R18 */
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0x0000, /* R19 */
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0x0000, /* R20 */
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0x0000, /* R21 */
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0x0000, /* R22 */
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0x00C1, /* R23 - Additional control (1) */
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0x0000, /* R24 - Additional control (2) */
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0x0000, /* R25 - Power Management (1) */
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0x0000, /* R26 - Power Management (2) */
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0x0000, /* R27 - Additional Control (3) */
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0x0000, /* R28 */
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0x0000, /* R29 */
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0x0000, /* R30 */
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0x0000, /* R31 */
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0x0000, /* R32 */
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0x0000, /* R33 */
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0x0050, /* R34 - Left out Mix (1) */
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0x0050, /* R35 - Left out Mix (2) */
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0x0050, /* R36 - Right out Mix (1) */
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0x0050, /* R37 - Right Out Mix (2) */
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0x0050, /* R38 - Mono out Mix (1) */
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0x0050, /* R39 - Mono out Mix (2) */
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0x0079, /* R40 - LOUT2 volume */
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0x0079, /* R41 - ROUT2 volume */
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0x0079, /* R42 - MONOOUT volume */
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0x0000, /* R43 - Clocking / PLL */
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0x0103, /* R44 - PLL Control 1 */
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0x0024, /* R45 - PLL Control 2 */
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0x01BA, /* R46 - PLL Control 3 */
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0x0000, /* R47 */
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0x0000, /* R48 */
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0x0000, /* R49 */
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0x0000, /* R50 */
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0x0000, /* R51 */
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0x0000, /* R52 */
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0x0000, /* R53 */
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0x0000, /* R54 */
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0x0000, /* R55 */
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0x0000, /* R56 */
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0x0000, /* R57 */
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0x0000, /* R58 */
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0x0000, /* R59 - PLL Control 4 */
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static const struct reg_default wm8955_reg_defaults[] = {
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{ 2, 0x0079 }, /* R2 - LOUT1 volume */
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{ 3, 0x0079 }, /* R3 - ROUT1 volume */
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{ 5, 0x0008 }, /* R5 - DAC Control */
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{ 7, 0x000A }, /* R7 - Audio Interface */
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{ 8, 0x0000 }, /* R8 - Sample Rate */
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{ 10, 0x00FF }, /* R10 - Left DAC volume */
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{ 11, 0x00FF }, /* R11 - Right DAC volume */
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{ 12, 0x000F }, /* R12 - Bass control */
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{ 13, 0x000F }, /* R13 - Treble control */
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{ 23, 0x00C1 }, /* R23 - Additional control (1) */
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{ 24, 0x0000 }, /* R24 - Additional control (2) */
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{ 25, 0x0000 }, /* R25 - Power Management (1) */
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{ 26, 0x0000 }, /* R26 - Power Management (2) */
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{ 27, 0x0000 }, /* R27 - Additional Control (3) */
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{ 34, 0x0050 }, /* R34 - Left out Mix (1) */
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{ 35, 0x0050 }, /* R35 - Left out Mix (2) */
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{ 36, 0x0050 }, /* R36 - Right out Mix (1) */
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{ 37, 0x0050 }, /* R37 - Right Out Mix (2) */
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{ 38, 0x0050 }, /* R38 - Mono out Mix (1) */
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{ 39, 0x0050 }, /* R39 - Mono out Mix (2) */
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{ 40, 0x0079 }, /* R40 - LOUT2 volume */
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{ 41, 0x0079 }, /* R41 - ROUT2 volume */
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{ 42, 0x0079 }, /* R42 - MONOOUT volume */
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{ 43, 0x0000 }, /* R43 - Clocking / PLL */
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{ 44, 0x0103 }, /* R44 - PLL Control 1 */
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{ 45, 0x0024 }, /* R45 - PLL Control 2 */
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{ 46, 0x01BA }, /* R46 - PLL Control 3 */
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{ 59, 0x0000 }, /* R59 - PLL Control 4 */
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};
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static bool wm8955_writeable(struct device *dev, unsigned int reg)
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{
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switch (reg) {
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case WM8955_LOUT1_VOLUME:
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case WM8955_ROUT1_VOLUME:
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case WM8955_DAC_CONTROL:
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case WM8955_AUDIO_INTERFACE:
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case WM8955_SAMPLE_RATE:
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case WM8955_LEFT_DAC_VOLUME:
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case WM8955_RIGHT_DAC_VOLUME:
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case WM8955_BASS_CONTROL:
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case WM8955_TREBLE_CONTROL:
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case WM8955_RESET:
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case WM8955_ADDITIONAL_CONTROL_1:
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case WM8955_ADDITIONAL_CONTROL_2:
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case WM8955_POWER_MANAGEMENT_1:
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case WM8955_POWER_MANAGEMENT_2:
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case WM8955_ADDITIONAL_CONTROL_3:
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case WM8955_LEFT_OUT_MIX_1:
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case WM8955_LEFT_OUT_MIX_2:
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case WM8955_RIGHT_OUT_MIX_1:
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case WM8955_RIGHT_OUT_MIX_2:
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case WM8955_MONO_OUT_MIX_1:
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case WM8955_MONO_OUT_MIX_2:
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case WM8955_LOUT2_VOLUME:
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case WM8955_ROUT2_VOLUME:
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case WM8955_MONOOUT_VOLUME:
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case WM8955_CLOCKING_PLL:
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case WM8955_PLL_CONTROL_1:
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case WM8955_PLL_CONTROL_2:
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case WM8955_PLL_CONTROL_3:
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case WM8955_PLL_CONTROL_4:
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return true;
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default:
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return false;
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}
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}
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static bool wm8955_volatile(struct device *dev, unsigned int reg)
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{
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switch (reg) {
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case WM8955_RESET:
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return true;
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default:
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return false;
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}
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}
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static int wm8955_reset(struct snd_soc_codec *codec)
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{
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return snd_soc_write(codec, WM8955_RESET, 0);
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@ -765,8 +782,7 @@ static int wm8955_set_bias_level(struct snd_soc_codec *codec,
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enum snd_soc_bias_level level)
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{
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struct wm8955_priv *wm8955 = snd_soc_codec_get_drvdata(codec);
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u16 *reg_cache = codec->reg_cache;
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int ret, i;
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int ret;
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switch (level) {
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case SND_SOC_BIAS_ON:
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@ -795,7 +811,7 @@ static int wm8955_set_bias_level(struct snd_soc_codec *codec,
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return ret;
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}
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snd_soc_cache_sync(codec);
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regcache_sync(wm8955->regmap);
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/* Enable VREF and VMID */
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snd_soc_update_bits(codec, WM8955_POWER_MANAGEMENT_1,
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@ -869,8 +885,12 @@ static struct snd_soc_dai_driver wm8955_dai = {
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#ifdef CONFIG_PM
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static int wm8955_suspend(struct snd_soc_codec *codec)
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{
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struct wm8955_priv *wm8955 = snd_soc_codec_get_drvdata(codec);
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wm8955_set_bias_level(codec, SND_SOC_BIAS_OFF);
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regcache_mark_dirty(wm8955->regmap);
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return 0;
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}
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@ -889,10 +909,11 @@ static int wm8955_probe(struct snd_soc_codec *codec)
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{
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struct wm8955_priv *wm8955 = snd_soc_codec_get_drvdata(codec);
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struct wm8955_pdata *pdata = dev_get_platdata(codec->dev);
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u16 *reg_cache = codec->reg_cache;
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int ret, i;
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ret = snd_soc_codec_set_cache_io(codec, 7, 9, wm8955->control_type);
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codec->control_data = wm8955->regmap;
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ret = snd_soc_codec_set_cache_io(codec, 7, 9, SND_SOC_REGMAP);
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if (ret != 0) {
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dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
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return ret;
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@ -947,12 +968,12 @@ static int wm8955_probe(struct snd_soc_codec *codec)
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/* Set platform data values */
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if (pdata) {
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if (pdata->out2_speaker)
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reg_cache[WM8955_ADDITIONAL_CONTROL_2]
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|= WM8955_ROUT2INV;
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snd_soc_update_bits(codec, WM8955_ADDITIONAL_CONTROL_2,
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WM8955_ROUT2INV, WM8955_ROUT2INV);
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if (pdata->monoin_diff)
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reg_cache[WM8955_MONO_OUT_MIX_1]
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|= WM8955_DMEN;
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snd_soc_update_bits(codec, WM8955_MONO_OUT_MIX_1,
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WM8955_DMEN, WM8955_DMEN);
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}
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wm8955_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
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@ -985,9 +1006,19 @@ static struct snd_soc_codec_driver soc_codec_dev_wm8955 = {
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.suspend = wm8955_suspend,
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.resume = wm8955_resume,
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.set_bias_level = wm8955_set_bias_level,
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.reg_cache_size = ARRAY_SIZE(wm8955_reg),
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.reg_word_size = sizeof(u16),
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.reg_cache_default = wm8955_reg,
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};
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static const struct regmap_config wm8955_regmap = {
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.reg_bits = 7,
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.val_bits = 9,
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.max_register = WM8955_MAX_REGISTER,
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.volatile_reg = wm8955_volatile,
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.writeable_reg = wm8955_writeable,
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.cache_type = REGCACHE_RBTREE,
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.reg_defaults = wm8955_reg_defaults,
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.num_reg_defaults = ARRAY_SIZE(wm8955_reg_defaults),
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};
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static __devinit int wm8955_i2c_probe(struct i2c_client *i2c,
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@ -1001,18 +1032,35 @@ static __devinit int wm8955_i2c_probe(struct i2c_client *i2c,
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if (wm8955 == NULL)
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return -ENOMEM;
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wm8955->regmap = regmap_init_i2c(i2c, &wm8955_regmap);
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if (IS_ERR(wm8955->regmap)) {
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ret = PTR_ERR(wm8955->regmap);
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dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
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ret);
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return ret;
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}
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i2c_set_clientdata(i2c, wm8955);
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wm8955->control_type = SND_SOC_I2C;
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ret = snd_soc_register_codec(&i2c->dev,
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&soc_codec_dev_wm8955, &wm8955_dai, 1);
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if (ret != 0)
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goto err;
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return ret;
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err:
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regmap_exit(wm8955->regmap);
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return ret;
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}
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static __devexit int wm8955_i2c_remove(struct i2c_client *client)
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{
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struct wm8955_priv *wm8955 = i2c_get_clientdata(client);
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snd_soc_unregister_codec(&client->dev);
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regmap_exit(wm8955->regmap);
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return 0;
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}
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