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drm/i915: Split out i915_gem_object_set_tiling()
Expose an interface for changing the tiling and stride on an object, that includes the complexity of checking for conflicting bindings and fence registers. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/20170110121045.27144-2-chris@chris-wilson.co.uk
This commit is contained in:
Chris Wilson
parent
111dbcab3d
commit
957870f934
@ -337,6 +337,9 @@ i915_gem_object_get_tile_row_size(struct drm_i915_gem_object *obj)
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i915_gem_object_get_tile_height(obj));
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}
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int i915_gem_object_set_tiling(struct drm_i915_gem_object *obj,
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unsigned int tiling, unsigned int stride);
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static inline struct intel_engine_cs *
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i915_gem_object_last_write_engine(struct drm_i915_gem_object *obj)
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{
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@ -129,61 +129,56 @@ u32 i915_gem_fence_alignment(struct drm_i915_private *i915, u32 size,
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/* Check pitch constriants for all chips & tiling formats */
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static bool
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i915_tiling_ok(struct drm_i915_private *dev_priv,
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int stride, int size, int tiling_mode)
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i915_tiling_ok(struct drm_i915_gem_object *obj,
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unsigned int tiling, unsigned int stride)
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{
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int tile_width;
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struct drm_i915_private *i915 = to_i915(obj->base.dev);
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unsigned int tile_width;
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/* Linear is always fine */
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if (tiling_mode == I915_TILING_NONE)
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if (tiling == I915_TILING_NONE)
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return true;
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if (tiling_mode > I915_TILING_LAST)
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if (tiling > I915_TILING_LAST)
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return false;
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if (IS_GEN2(dev_priv) ||
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(tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev_priv)))
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tile_width = 128;
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else
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tile_width = 512;
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/* check maximum stride & object size */
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/* i965+ stores the end address of the gtt mapping in the fence
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* reg, so dont bother to check the size */
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if (INTEL_GEN(dev_priv) >= 7) {
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if (INTEL_GEN(i915) >= 7) {
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if (stride / 128 > GEN7_FENCE_MAX_PITCH_VAL)
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return false;
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} else if (INTEL_GEN(dev_priv) >= 4) {
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} else if (INTEL_GEN(i915) >= 4) {
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if (stride / 128 > I965_FENCE_MAX_PITCH_VAL)
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return false;
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} else {
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if (stride > 8192)
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return false;
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if (IS_GEN3(dev_priv)) {
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if (size > I830_FENCE_MAX_SIZE_VAL << 20)
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if (IS_GEN3(i915)) {
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if (obj->base.size > I830_FENCE_MAX_SIZE_VAL << 20)
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return false;
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} else {
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if (size > I830_FENCE_MAX_SIZE_VAL << 19)
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if (obj->base.size > I830_FENCE_MAX_SIZE_VAL << 19)
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return false;
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}
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}
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if (stride < tile_width)
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if (IS_GEN2(i915) ||
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(tiling == I915_TILING_Y && HAS_128_BYTE_Y_TILING(i915)))
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tile_width = 128;
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else
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tile_width = 512;
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if (stride & (tile_width - 1))
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return false;
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/* 965+ just needs multiples of tile width */
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if (INTEL_GEN(dev_priv) >= 4) {
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if (stride & (tile_width - 1))
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return false;
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if (INTEL_GEN(i915) >= 4)
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return true;
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}
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/* Pre-965 needs power of two tile widths */
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if (stride & (stride - 1))
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return false;
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return true;
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return is_power_of_2(stride);
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}
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static bool i915_vma_fence_prepare(struct i915_vma *vma,
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@ -232,6 +227,98 @@ i915_gem_object_fence_prepare(struct drm_i915_gem_object *obj,
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return 0;
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}
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int
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i915_gem_object_set_tiling(struct drm_i915_gem_object *obj,
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unsigned int tiling, unsigned int stride)
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{
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struct drm_i915_private *i915 = to_i915(obj->base.dev);
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struct i915_vma *vma;
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int err;
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/* Make sure we don't cross-contaminate obj->tiling_and_stride */
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BUILD_BUG_ON(I915_TILING_LAST & STRIDE_MASK);
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GEM_BUG_ON(!i915_tiling_ok(obj, tiling, stride));
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GEM_BUG_ON(!stride ^ (tiling == I915_TILING_NONE));
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lockdep_assert_held(&i915->drm.struct_mutex);
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if ((tiling | stride) == obj->tiling_and_stride)
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return 0;
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if (obj->framebuffer_references)
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return -EBUSY;
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/* We need to rebind the object if its current allocation
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* no longer meets the alignment restrictions for its new
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* tiling mode. Otherwise we can just leave it alone, but
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* need to ensure that any fence register is updated before
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* the next fenced (either through the GTT or by the BLT unit
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* on older GPUs) access.
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*
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* After updating the tiling parameters, we then flag whether
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* we need to update an associated fence register. Note this
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* has to also include the unfenced register the GPU uses
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* whilst executing a fenced command for an untiled object.
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*/
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err = i915_gem_object_fence_prepare(obj, tiling, stride);
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if (err)
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return err;
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/* If the memory has unknown (i.e. varying) swizzling, we pin the
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* pages to prevent them being swapped out and causing corruption
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* due to the change in swizzling.
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*/
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mutex_lock(&obj->mm.lock);
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if (obj->mm.pages &&
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obj->mm.madv == I915_MADV_WILLNEED &&
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i915->quirks & QUIRK_PIN_SWIZZLED_PAGES) {
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if (tiling == I915_TILING_NONE) {
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GEM_BUG_ON(!obj->mm.quirked);
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__i915_gem_object_unpin_pages(obj);
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obj->mm.quirked = false;
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}
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if (!i915_gem_object_is_tiled(obj)) {
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GEM_BUG_ON(!obj->mm.quirked);
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__i915_gem_object_pin_pages(obj);
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obj->mm.quirked = true;
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}
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}
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mutex_unlock(&obj->mm.lock);
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list_for_each_entry(vma, &obj->vma_list, obj_link) {
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if (!i915_vma_is_ggtt(vma))
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break;
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vma->fence_size =
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i915_gem_fence_size(i915, vma->size, tiling, stride);
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vma->fence_alignment =
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i915_gem_fence_alignment(i915,
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vma->size, tiling, stride);
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if (vma->fence)
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vma->fence->dirty = true;
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}
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obj->tiling_and_stride = tiling | stride;
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/* Force the fence to be reacquired for GTT access */
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i915_gem_release_mmap(obj);
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/* Try to preallocate memory required to save swizzling on put-pages */
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if (i915_gem_object_needs_bit17_swizzle(obj)) {
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if (!obj->bit_17) {
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obj->bit_17 = kcalloc(BITS_TO_LONGS(obj->base.size >> PAGE_SHIFT),
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sizeof(long), GFP_KERNEL);
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}
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} else {
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kfree(obj->bit_17);
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obj->bit_17 = NULL;
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}
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return 0;
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}
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/**
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* i915_gem_set_tiling_ioctl - IOCTL handler to set tiling mode
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* @dev: DRM device
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@ -251,26 +338,15 @@ i915_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
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struct drm_file *file)
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{
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struct drm_i915_gem_set_tiling *args = data;
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struct drm_i915_private *dev_priv = to_i915(dev);
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struct drm_i915_gem_object *obj;
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int err = 0;
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/* Make sure we don't cross-contaminate obj->tiling_and_stride */
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BUILD_BUG_ON(I915_TILING_LAST & STRIDE_MASK);
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int err;
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obj = i915_gem_object_lookup(file, args->handle);
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if (!obj)
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return -ENOENT;
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if (!i915_tiling_ok(dev_priv,
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args->stride, obj->base.size, args->tiling_mode)) {
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i915_gem_object_put(obj);
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return -EINVAL;
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}
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mutex_lock(&dev->struct_mutex);
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if (obj->pin_display || obj->framebuffer_references) {
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err = -EBUSY;
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if (!i915_tiling_ok(obj, args->tiling_mode, args->stride)) {
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err = -EINVAL;
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goto err;
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}
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@ -279,9 +355,9 @@ i915_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
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args->stride = 0;
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} else {
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if (args->tiling_mode == I915_TILING_X)
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args->swizzle_mode = dev_priv->mm.bit_6_swizzle_x;
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args->swizzle_mode = to_i915(dev)->mm.bit_6_swizzle_x;
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else
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args->swizzle_mode = dev_priv->mm.bit_6_swizzle_y;
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args->swizzle_mode = to_i915(dev)->mm.bit_6_swizzle_y;
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/* Hide bit 17 swizzling from the user. This prevents old Mesa
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* from aborting the application on sw fallbacks to bit 17,
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@ -303,84 +379,19 @@ i915_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
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}
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}
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if (args->tiling_mode != i915_gem_object_get_tiling(obj) ||
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args->stride != i915_gem_object_get_stride(obj)) {
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/* We need to rebind the object if its current allocation
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* no longer meets the alignment restrictions for its new
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* tiling mode. Otherwise we can just leave it alone, but
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* need to ensure that any fence register is updated before
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* the next fenced (either through the GTT or by the BLT unit
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* on older GPUs) access.
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*
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* After updating the tiling parameters, we then flag whether
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* we need to update an associated fence register. Note this
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* has to also include the unfenced register the GPU uses
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* whilst executing a fenced command for an untiled object.
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*/
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err = mutex_lock_interruptible(&dev->struct_mutex);
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if (err)
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goto err;
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err = i915_gem_object_fence_prepare(obj,
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args->tiling_mode,
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args->stride);
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if (!err) {
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struct i915_vma *vma;
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err = i915_gem_object_set_tiling(obj, args->tiling_mode, args->stride);
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mutex_unlock(&dev->struct_mutex);
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mutex_lock(&obj->mm.lock);
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if (obj->mm.pages &&
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obj->mm.madv == I915_MADV_WILLNEED &&
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dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES) {
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if (args->tiling_mode == I915_TILING_NONE) {
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GEM_BUG_ON(!obj->mm.quirked);
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__i915_gem_object_unpin_pages(obj);
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obj->mm.quirked = false;
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}
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if (!i915_gem_object_is_tiled(obj)) {
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GEM_BUG_ON(!obj->mm.quirked);
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__i915_gem_object_pin_pages(obj);
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obj->mm.quirked = true;
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}
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}
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mutex_unlock(&obj->mm.lock);
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list_for_each_entry(vma, &obj->vma_list, obj_link) {
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if (!i915_vma_is_ggtt(vma))
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break;
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vma->fence_size = i915_gem_fence_size(dev_priv, vma->size,
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args->tiling_mode,
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args->stride);
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vma->fence_alignment = i915_gem_fence_alignment(dev_priv, vma->size,
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args->tiling_mode,
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args->stride);
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if (vma->fence)
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vma->fence->dirty = true;
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}
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obj->tiling_and_stride =
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args->stride | args->tiling_mode;
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/* Force the fence to be reacquired for GTT access */
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i915_gem_release_mmap(obj);
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}
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}
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/* we have to maintain this existing ABI... */
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/* We have to maintain this existing ABI... */
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args->stride = i915_gem_object_get_stride(obj);
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args->tiling_mode = i915_gem_object_get_tiling(obj);
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/* Try to preallocate memory required to save swizzling on put-pages */
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if (i915_gem_object_needs_bit17_swizzle(obj)) {
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if (obj->bit_17 == NULL) {
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obj->bit_17 = kcalloc(BITS_TO_LONGS(obj->base.size >> PAGE_SHIFT),
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sizeof(long), GFP_KERNEL);
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}
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} else {
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kfree(obj->bit_17);
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obj->bit_17 = NULL;
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}
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err:
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i915_gem_object_put(obj);
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mutex_unlock(&dev->struct_mutex);
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return err;
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}
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