AuxXxilium/linux_dsm_epyc7002
1
0
Fork 0
mirror of https://github.com/AuxXxilium/linux_dsm_epyc7002.git synced 2024-12-20 01:37:41 +07:00
Code Issues Actions Packages Projects Releases Wiki Activity

drm/amd/pp: Fix error handling when smu return failed on Vega10.

Browse Source 
Clamp the clock index to a valid range when reading it back

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Rex Zhu 2018-02-11 12:38:58 +08:00 committed by Alex Deucher
parent 40d5250dbb
commit 952e5daa25
1 changed files with 14 additions and 12 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

26
drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
View File

@ -3912,28 +3912,30 @@ static int vega10_read_sensor(struct pp_hwmgr *hwmgr, int idx,
switch (idx) { switch (idx) {
case AMDGPU_PP_SENSOR_GFX_SCLK: case AMDGPU_PP_SENSOR_GFX_SCLK:
ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrentGfxclkIndex); smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrentGfxclkIndex);
if (!ret) { vega10_read_arg_from_smc(hwmgr, &sclk_idx);
vega10_read_arg_from_smc(hwmgr, &sclk_idx); if (sclk_idx < dpm_table->gfx_table.count) {
*((uint32_t *)value) = dpm_table->gfx_table.dpm_levels[sclk_idx].value; *((uint32_t *)value) = dpm_table->gfx_table.dpm_levels[sclk_idx].value;
*size = 4; *size = 4;
} else {
ret = -EINVAL;
} }
break; break;
case AMDGPU_PP_SENSOR_GFX_MCLK: case AMDGPU_PP_SENSOR_GFX_MCLK:
ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrentUclkIndex); smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrentUclkIndex);
if (!ret) { vega10_read_arg_from_smc(hwmgr, &mclk_idx);
vega10_read_arg_from_smc(hwmgr, &mclk_idx); if (mclk_idx < dpm_table->mem_table.count) {
*((uint32_t *)value) = dpm_table->mem_table.dpm_levels[mclk_idx].value; *((uint32_t *)value) = dpm_table->mem_table.dpm_levels[mclk_idx].value;
*size = 4; *size = 4;
} else {
ret = -EINVAL;
} }
break; break;
case AMDGPU_PP_SENSOR_GPU_LOAD: case AMDGPU_PP_SENSOR_GPU_LOAD:
ret = smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_GetAverageGfxActivity, 0); smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_GetAverageGfxActivity, 0);
if (!ret) { vega10_read_arg_from_smc(hwmgr, &activity_percent);
vega10_read_arg_from_smc(hwmgr, &activity_percent); *((uint32_t *)value) = activity_percent > 100 ? 100 : activity_percent;
*((uint32_t *)value) = activity_percent > 100 ? 100 : activity_percent; *size = 4;
*size = 4;
}
break; break;
case AMDGPU_PP_SENSOR_GPU_TEMP: case AMDGPU_PP_SENSOR_GPU_TEMP:
*((uint32_t *)value) = vega10_thermal_get_temperature(hwmgr); *((uint32_t *)value) = vega10_thermal_get_temperature(hwmgr);