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drm/amd/pp: Fix error handling when smu return failed on Vega10.
Clamp the clock index to a valid range when reading it back Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -3912,28 +3912,30 @@ static int vega10_read_sensor(struct pp_hwmgr *hwmgr, int idx,
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switch (idx) {
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case AMDGPU_PP_SENSOR_GFX_SCLK:
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ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrentGfxclkIndex);
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if (!ret) {
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vega10_read_arg_from_smc(hwmgr, &sclk_idx);
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smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrentGfxclkIndex);
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vega10_read_arg_from_smc(hwmgr, &sclk_idx);
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if (sclk_idx < dpm_table->gfx_table.count) {
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*((uint32_t *)value) = dpm_table->gfx_table.dpm_levels[sclk_idx].value;
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*size = 4;
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} else {
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ret = -EINVAL;
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}
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break;
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case AMDGPU_PP_SENSOR_GFX_MCLK:
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ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrentUclkIndex);
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if (!ret) {
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vega10_read_arg_from_smc(hwmgr, &mclk_idx);
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smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrentUclkIndex);
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vega10_read_arg_from_smc(hwmgr, &mclk_idx);
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if (mclk_idx < dpm_table->mem_table.count) {
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*((uint32_t *)value) = dpm_table->mem_table.dpm_levels[mclk_idx].value;
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*size = 4;
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} else {
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ret = -EINVAL;
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}
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break;
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case AMDGPU_PP_SENSOR_GPU_LOAD:
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ret = smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_GetAverageGfxActivity, 0);
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if (!ret) {
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vega10_read_arg_from_smc(hwmgr, &activity_percent);
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*((uint32_t *)value) = activity_percent > 100 ? 100 : activity_percent;
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*size = 4;
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}
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smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_GetAverageGfxActivity, 0);
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vega10_read_arg_from_smc(hwmgr, &activity_percent);
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*((uint32_t *)value) = activity_percent > 100 ? 100 : activity_percent;
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*size = 4;
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break;
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case AMDGPU_PP_SENSOR_GPU_TEMP:
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*((uint32_t *)value) = vega10_thermal_get_temperature(hwmgr);
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