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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-11-24 19:30:52 +07:00
drm/ast: POST code for the new AST2500
This is used when the BMC isn't running any code and thus has to be initialized by the host. The code originates from Aspeed (Y.C. Chen) and has been cleaned up for coding style purposes by BenH. Signed-off-by: Y.C. Chen <yc_chen@aspeedtech.com> Acked-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Dave Airlie <airlied@redhat.com>
This commit is contained in:
Y.C. Chen
Dave Airlie
parent
d95618ef0a
commit
94fdc2a86a
@ -141,4 +141,66 @@ static const struct ast_dramstruct ast2100_dram_table_data[] = {
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{ 0xffff, 0xffffffff },
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};
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/*
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* AST2500 DRAM settings modules
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*/
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#define REGTBL_NUM 17
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#define REGIDX_010 0
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#define REGIDX_014 1
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#define REGIDX_018 2
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#define REGIDX_020 3
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#define REGIDX_024 4
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#define REGIDX_02C 5
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#define REGIDX_030 6
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#define REGIDX_214 7
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#define REGIDX_2E0 8
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#define REGIDX_2E4 9
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#define REGIDX_2E8 10
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#define REGIDX_2EC 11
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#define REGIDX_2F0 12
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#define REGIDX_2F4 13
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#define REGIDX_2F8 14
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#define REGIDX_RFC 15
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#define REGIDX_PLL 16
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static const u32 ast2500_ddr3_1600_timing_table[REGTBL_NUM] = {
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0x64604D38, /* 0x010 */
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0x29690599, /* 0x014 */
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0x00000300, /* 0x018 */
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0x00000000, /* 0x020 */
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0x00000000, /* 0x024 */
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0x02181E70, /* 0x02C */
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0x00000040, /* 0x030 */
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0x00000024, /* 0x214 */
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0x02001300, /* 0x2E0 */
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0x0E0000A0, /* 0x2E4 */
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0x000E001B, /* 0x2E8 */
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0x35B8C105, /* 0x2EC */
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0x08090408, /* 0x2F0 */
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0x9B000800, /* 0x2F4 */
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0x0E400A00, /* 0x2F8 */
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0x9971452F, /* tRFC */
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0x000071C1 /* PLL */
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};
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static const u32 ast2500_ddr4_1600_timing_table[REGTBL_NUM] = {
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0x63604E37, /* 0x010 */
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0xE97AFA99, /* 0x014 */
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0x00019000, /* 0x018 */
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0x08000000, /* 0x020 */
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0x00000400, /* 0x024 */
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0x00000410, /* 0x02C */
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0x00000101, /* 0x030 */
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0x00000024, /* 0x214 */
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0x03002900, /* 0x2E0 */
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0x0E0000A0, /* 0x2E4 */
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0x000E001C, /* 0x2E8 */
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0x35B8C106, /* 0x2EC */
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0x08080607, /* 0x2F0 */
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0x9B000900, /* 0x2F4 */
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0x0E400A00, /* 0x2F8 */
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0x99714545, /* tRFC */
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0x000071C1 /* PLL */
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};
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#endif
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@ -32,6 +32,7 @@
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#include "ast_dram_tables.h"
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static void ast_post_chip_2300(struct drm_device *dev);
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static void ast_post_chip_2500(struct drm_device *dev);
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void ast_enable_vga(struct drm_device *dev)
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{
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@ -82,7 +83,8 @@ ast_set_def_ext_reg(struct drm_device *dev)
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for (i = 0x81; i <= 0x9f; i++)
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ast_set_index_reg(ast, AST_IO_CRTC_PORT, i, 0x00);
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if (ast->chip == AST2300 || ast->chip == AST2400) {
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if (ast->chip == AST2300 || ast->chip == AST2400 ||
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ast->chip == AST2500) {
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if (dev->pdev->revision >= 0x20)
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ext_reg_info = extreginfo_ast2300;
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else
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@ -106,7 +108,8 @@ ast_set_def_ext_reg(struct drm_device *dev)
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/* Enable RAMDAC for A1 */
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reg = 0x04;
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if (ast->chip == AST2300 || ast->chip == AST2400)
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if (ast->chip == AST2300 || ast->chip == AST2400 ||
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ast->chip == AST2500)
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reg |= 0x20;
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ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb6, 0xff, reg);
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}
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@ -380,7 +383,9 @@ void ast_post_gpu(struct drm_device *dev)
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ast_set_def_ext_reg(dev);
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if (ast->config_mode == ast_use_p2a) {
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if (ast->chip == AST2300 || ast->chip == AST2400)
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if (ast->chip == AST2500)
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ast_post_chip_2500(dev);
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else if (ast->chip == AST2300 || ast->chip == AST2400)
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ast_post_chip_2300(dev);
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else
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ast_init_dram_reg(dev);
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@ -506,6 +511,11 @@ static u32 mmc_test_single2(struct ast_private *ast, u32 datagen)
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return mmc_test2(ast, datagen, 0x05);
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}
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static bool mmc_test_single_2500(struct ast_private *ast, u32 datagen)
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{
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return mmc_test(ast, datagen, 0x85);
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}
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static int cbr_test(struct ast_private *ast)
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{
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u32 data;
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@ -1672,3 +1682,404 @@ static void ast_post_chip_2300(struct drm_device *dev)
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} while ((reg & 0x40) == 0);
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}
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static bool cbr_test_2500(struct ast_private *ast)
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{
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ast_moutdwm(ast, 0x1E6E0074, 0x0000FFFF);
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ast_moutdwm(ast, 0x1E6E007C, 0xFF00FF00);
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if (!mmc_test_burst(ast, 0))
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return false;
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if (!mmc_test_single_2500(ast, 0))
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return false;
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return true;
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}
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static bool ddr_test_2500(struct ast_private *ast)
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{
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ast_moutdwm(ast, 0x1E6E0074, 0x0000FFFF);
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ast_moutdwm(ast, 0x1E6E007C, 0xFF00FF00);
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if (!mmc_test_burst(ast, 0))
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return false;
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if (!mmc_test_burst(ast, 1))
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return false;
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if (!mmc_test_burst(ast, 2))
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return false;
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if (!mmc_test_burst(ast, 3))
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return false;
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if (!mmc_test_single_2500(ast, 0))
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return false;
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return true;
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}
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static void ddr_init_common_2500(struct ast_private *ast)
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{
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ast_moutdwm(ast, 0x1E6E0034, 0x00020080);
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ast_moutdwm(ast, 0x1E6E0008, 0x2003000F);
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ast_moutdwm(ast, 0x1E6E0038, 0x00000FFF);
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ast_moutdwm(ast, 0x1E6E0040, 0x88448844);
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ast_moutdwm(ast, 0x1E6E0044, 0x24422288);
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ast_moutdwm(ast, 0x1E6E0048, 0x22222222);
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ast_moutdwm(ast, 0x1E6E004C, 0x22222222);
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ast_moutdwm(ast, 0x1E6E0050, 0x80000000);
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ast_moutdwm(ast, 0x1E6E0208, 0x00000000);
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ast_moutdwm(ast, 0x1E6E0218, 0x00000000);
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ast_moutdwm(ast, 0x1E6E0220, 0x00000000);
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ast_moutdwm(ast, 0x1E6E0228, 0x00000000);
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ast_moutdwm(ast, 0x1E6E0230, 0x00000000);
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ast_moutdwm(ast, 0x1E6E02A8, 0x00000000);
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ast_moutdwm(ast, 0x1E6E02B0, 0x00000000);
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ast_moutdwm(ast, 0x1E6E0240, 0x86000000);
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ast_moutdwm(ast, 0x1E6E0244, 0x00008600);
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ast_moutdwm(ast, 0x1E6E0248, 0x80000000);
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ast_moutdwm(ast, 0x1E6E024C, 0x80808080);
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}
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static void ddr_phy_init_2500(struct ast_private *ast)
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{
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u32 data, pass, timecnt;
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pass = 0;
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ast_moutdwm(ast, 0x1E6E0060, 0x00000005);
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while (!pass) {
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for (timecnt = 0; timecnt < TIMEOUT; timecnt++) {
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data = ast_mindwm(ast, 0x1E6E0060) & 0x1;
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if (!data)
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break;
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}
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if (timecnt != TIMEOUT) {
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data = ast_mindwm(ast, 0x1E6E0300) & 0x000A0000;
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if (!data)
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pass = 1;
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}
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if (!pass) {
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ast_moutdwm(ast, 0x1E6E0060, 0x00000000);
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udelay(10); /* delay 10 us */
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ast_moutdwm(ast, 0x1E6E0060, 0x00000005);
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}
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}
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ast_moutdwm(ast, 0x1E6E0060, 0x00000006);
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}
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/*
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* Check DRAM Size
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* 1Gb : 0x80000000 ~ 0x87FFFFFF
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* 2Gb : 0x80000000 ~ 0x8FFFFFFF
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* 4Gb : 0x80000000 ~ 0x9FFFFFFF
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* 8Gb : 0x80000000 ~ 0xBFFFFFFF
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*/
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static void check_dram_size_2500(struct ast_private *ast, u32 tRFC)
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{
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u32 reg_04, reg_14;
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reg_04 = ast_mindwm(ast, 0x1E6E0004) & 0xfffffffc;
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reg_14 = ast_mindwm(ast, 0x1E6E0014) & 0xffffff00;
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ast_moutdwm(ast, 0xA0100000, 0x41424344);
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ast_moutdwm(ast, 0x90100000, 0x35363738);
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ast_moutdwm(ast, 0x88100000, 0x292A2B2C);
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ast_moutdwm(ast, 0x80100000, 0x1D1E1F10);
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/* Check 8Gbit */
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if (ast_mindwm(ast, 0xA0100000) == 0x41424344) {
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reg_04 |= 0x03;
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reg_14 |= (tRFC >> 24) & 0xFF;
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/* Check 4Gbit */
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} else if (ast_mindwm(ast, 0x90100000) == 0x35363738) {
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reg_04 |= 0x02;
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reg_14 |= (tRFC >> 16) & 0xFF;
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/* Check 2Gbit */
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} else if (ast_mindwm(ast, 0x88100000) == 0x292A2B2C) {
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reg_04 |= 0x01;
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reg_14 |= (tRFC >> 8) & 0xFF;
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} else {
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reg_14 |= tRFC & 0xFF;
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}
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ast_moutdwm(ast, 0x1E6E0004, reg_04);
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ast_moutdwm(ast, 0x1E6E0014, reg_14);
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}
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static void enable_cache_2500(struct ast_private *ast)
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{
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u32 reg_04, data;
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reg_04 = ast_mindwm(ast, 0x1E6E0004);
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ast_moutdwm(ast, 0x1E6E0004, reg_04 | 0x1000);
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do
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data = ast_mindwm(ast, 0x1E6E0004);
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while (!(data & 0x80000));
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ast_moutdwm(ast, 0x1E6E0004, reg_04 | 0x400);
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}
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static void set_mpll_2500(struct ast_private *ast)
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{
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u32 addr, data, param;
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/* Reset MMC */
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ast_moutdwm(ast, 0x1E6E0000, 0xFC600309);
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ast_moutdwm(ast, 0x1E6E0034, 0x00020080);
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for (addr = 0x1e6e0004; addr < 0x1e6e0090;) {
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ast_moutdwm(ast, addr, 0x0);
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addr += 4;
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}
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ast_moutdwm(ast, 0x1E6E0034, 0x00020000);
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ast_moutdwm(ast, 0x1E6E2000, 0x1688A8A8);
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data = ast_mindwm(ast, 0x1E6E2070) & 0x00800000;
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if (data) {
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/* CLKIN = 25MHz */
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param = 0x930023E0;
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ast_moutdwm(ast, 0x1E6E2160, 0x00011320);
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} else {
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/* CLKIN = 24MHz */
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param = 0x93002400;
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}
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ast_moutdwm(ast, 0x1E6E2020, param);
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udelay(100);
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}
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static void reset_mmc_2500(struct ast_private *ast)
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{
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ast_moutdwm(ast, 0x1E78505C, 0x00000004);
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ast_moutdwm(ast, 0x1E785044, 0x00000001);
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ast_moutdwm(ast, 0x1E785048, 0x00004755);
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ast_moutdwm(ast, 0x1E78504C, 0x00000013);
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mdelay(100);
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ast_moutdwm(ast, 0x1E785054, 0x00000077);
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ast_moutdwm(ast, 0x1E6E0000, 0xFC600309);
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}
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static void ddr3_init_2500(struct ast_private *ast, const u32 *ddr_table)
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{
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ast_moutdwm(ast, 0x1E6E0004, 0x00000303);
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ast_moutdwm(ast, 0x1E6E0010, ddr_table[REGIDX_010]);
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ast_moutdwm(ast, 0x1E6E0014, ddr_table[REGIDX_014]);
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ast_moutdwm(ast, 0x1E6E0018, ddr_table[REGIDX_018]);
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ast_moutdwm(ast, 0x1E6E0020, ddr_table[REGIDX_020]); /* MODEREG4/6 */
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ast_moutdwm(ast, 0x1E6E0024, ddr_table[REGIDX_024]); /* MODEREG5 */
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ast_moutdwm(ast, 0x1E6E002C, ddr_table[REGIDX_02C] | 0x100); /* MODEREG0/2 */
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ast_moutdwm(ast, 0x1E6E0030, ddr_table[REGIDX_030]); /* MODEREG1/3 */
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/* DDR PHY Setting */
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ast_moutdwm(ast, 0x1E6E0200, 0x02492AAE);
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ast_moutdwm(ast, 0x1E6E0204, 0x00001001);
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ast_moutdwm(ast, 0x1E6E020C, 0x55E00B0B);
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ast_moutdwm(ast, 0x1E6E0210, 0x20000000);
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ast_moutdwm(ast, 0x1E6E0214, ddr_table[REGIDX_214]);
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ast_moutdwm(ast, 0x1E6E02E0, ddr_table[REGIDX_2E0]);
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ast_moutdwm(ast, 0x1E6E02E4, ddr_table[REGIDX_2E4]);
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ast_moutdwm(ast, 0x1E6E02E8, ddr_table[REGIDX_2E8]);
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ast_moutdwm(ast, 0x1E6E02EC, ddr_table[REGIDX_2EC]);
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ast_moutdwm(ast, 0x1E6E02F0, ddr_table[REGIDX_2F0]);
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ast_moutdwm(ast, 0x1E6E02F4, ddr_table[REGIDX_2F4]);
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ast_moutdwm(ast, 0x1E6E02F8, ddr_table[REGIDX_2F8]);
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ast_moutdwm(ast, 0x1E6E0290, 0x00100008);
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ast_moutdwm(ast, 0x1E6E02C0, 0x00000006);
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/* Controller Setting */
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ast_moutdwm(ast, 0x1E6E0034, 0x00020091);
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/* Wait DDR PHY init done */
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ddr_phy_init_2500(ast);
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ast_moutdwm(ast, 0x1E6E0120, ddr_table[REGIDX_PLL]);
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ast_moutdwm(ast, 0x1E6E000C, 0x42AA5C81);
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ast_moutdwm(ast, 0x1E6E0034, 0x0001AF93);
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check_dram_size_2500(ast, ddr_table[REGIDX_RFC]);
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enable_cache_2500(ast);
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ast_moutdwm(ast, 0x1E6E001C, 0x00000008);
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ast_moutdwm(ast, 0x1E6E0038, 0xFFFFFF00);
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}
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static void ddr4_init_2500(struct ast_private *ast, const u32 *ddr_table)
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{
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u32 data, data2, pass, retrycnt;
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u32 ddr_vref, phy_vref;
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u32 min_ddr_vref = 0, min_phy_vref = 0;
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u32 max_ddr_vref = 0, max_phy_vref = 0;
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ast_moutdwm(ast, 0x1E6E0004, 0x00000313);
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ast_moutdwm(ast, 0x1E6E0010, ddr_table[REGIDX_010]);
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ast_moutdwm(ast, 0x1E6E0014, ddr_table[REGIDX_014]);
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ast_moutdwm(ast, 0x1E6E0018, ddr_table[REGIDX_018]);
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ast_moutdwm(ast, 0x1E6E0020, ddr_table[REGIDX_020]); /* MODEREG4/6 */
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ast_moutdwm(ast, 0x1E6E0024, ddr_table[REGIDX_024]); /* MODEREG5 */
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ast_moutdwm(ast, 0x1E6E002C, ddr_table[REGIDX_02C] | 0x100); /* MODEREG0/2 */
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ast_moutdwm(ast, 0x1E6E0030, ddr_table[REGIDX_030]); /* MODEREG1/3 */
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/* DDR PHY Setting */
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ast_moutdwm(ast, 0x1E6E0200, 0x42492AAE);
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ast_moutdwm(ast, 0x1E6E0204, 0x09002000);
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ast_moutdwm(ast, 0x1E6E020C, 0x55E00B0B);
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ast_moutdwm(ast, 0x1E6E0210, 0x20000000);
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ast_moutdwm(ast, 0x1E6E0214, ddr_table[REGIDX_214]);
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ast_moutdwm(ast, 0x1E6E02E0, ddr_table[REGIDX_2E0]);
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ast_moutdwm(ast, 0x1E6E02E4, ddr_table[REGIDX_2E4]);
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ast_moutdwm(ast, 0x1E6E02E8, ddr_table[REGIDX_2E8]);
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ast_moutdwm(ast, 0x1E6E02EC, ddr_table[REGIDX_2EC]);
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ast_moutdwm(ast, 0x1E6E02F0, ddr_table[REGIDX_2F0]);
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ast_moutdwm(ast, 0x1E6E02F4, ddr_table[REGIDX_2F4]);
|
||||
ast_moutdwm(ast, 0x1E6E02F8, ddr_table[REGIDX_2F8]);
|
||||
ast_moutdwm(ast, 0x1E6E0290, 0x00100008);
|
||||
ast_moutdwm(ast, 0x1E6E02C4, 0x3C183C3C);
|
||||
ast_moutdwm(ast, 0x1E6E02C8, 0x00631E0E);
|
||||
|
||||
/* Controller Setting */
|
||||
ast_moutdwm(ast, 0x1E6E0034, 0x0001A991);
|
||||
|
||||
/* Train PHY Vref first */
|
||||
pass = 0;
|
||||
|
||||
for (retrycnt = 0; retrycnt < 4 && pass == 0; retrycnt++) {
|
||||
max_phy_vref = 0x0;
|
||||
pass = 0;
|
||||
ast_moutdwm(ast, 0x1E6E02C0, 0x00001C06);
|
||||
for (phy_vref = 0x40; phy_vref < 0x80; phy_vref++) {
|
||||
ast_moutdwm(ast, 0x1E6E000C, 0x00000000);
|
||||
ast_moutdwm(ast, 0x1E6E0060, 0x00000000);
|
||||
ast_moutdwm(ast, 0x1E6E02CC, phy_vref | (phy_vref << 8));
|
||||
/* Fire DFI Init */
|
||||
ddr_phy_init_2500(ast);
|
||||
ast_moutdwm(ast, 0x1E6E000C, 0x00005C01);
|
||||
if (cbr_test_2500(ast)) {
|
||||
pass++;
|
||||
data = ast_mindwm(ast, 0x1E6E03D0);
|
||||
data2 = data >> 8;
|
||||
data = data & 0xff;
|
||||
if (data > data2)
|
||||
data = data2;
|
||||
if (max_phy_vref < data) {
|
||||
max_phy_vref = data;
|
||||
min_phy_vref = phy_vref;
|
||||
}
|
||||
} else if (pass > 0)
|
||||
break;
|
||||
}
|
||||
}
|
||||
ast_moutdwm(ast, 0x1E6E02CC, min_phy_vref | (min_phy_vref << 8));
|
||||
|
||||
/* Train DDR Vref next */
|
||||
pass = 0;
|
||||
|
||||
for (retrycnt = 0; retrycnt < 4 && pass == 0; retrycnt++) {
|
||||
min_ddr_vref = 0xFF;
|
||||
max_ddr_vref = 0x0;
|
||||
pass = 0;
|
||||
for (ddr_vref = 0x00; ddr_vref < 0x40; ddr_vref++) {
|
||||
ast_moutdwm(ast, 0x1E6E000C, 0x00000000);
|
||||
ast_moutdwm(ast, 0x1E6E0060, 0x00000000);
|
||||
ast_moutdwm(ast, 0x1E6E02C0, 0x00000006 | (ddr_vref << 8));
|
||||
/* Fire DFI Init */
|
||||
ddr_phy_init_2500(ast);
|
||||
ast_moutdwm(ast, 0x1E6E000C, 0x00005C01);
|
||||
if (cbr_test_2500(ast)) {
|
||||
pass++;
|
||||
if (min_ddr_vref > ddr_vref)
|
||||
min_ddr_vref = ddr_vref;
|
||||
if (max_ddr_vref < ddr_vref)
|
||||
max_ddr_vref = ddr_vref;
|
||||
} else if (pass != 0)
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
ast_moutdwm(ast, 0x1E6E000C, 0x00000000);
|
||||
ast_moutdwm(ast, 0x1E6E0060, 0x00000000);
|
||||
ddr_vref = (min_ddr_vref + max_ddr_vref + 1) >> 1;
|
||||
ast_moutdwm(ast, 0x1E6E02C0, 0x00000006 | (ddr_vref << 8));
|
||||
|
||||
/* Wait DDR PHY init done */
|
||||
ddr_phy_init_2500(ast);
|
||||
|
||||
ast_moutdwm(ast, 0x1E6E0120, ddr_table[REGIDX_PLL]);
|
||||
ast_moutdwm(ast, 0x1E6E000C, 0x42AA5C81);
|
||||
ast_moutdwm(ast, 0x1E6E0034, 0x0001AF93);
|
||||
|
||||
check_dram_size_2500(ast, ddr_table[REGIDX_RFC]);
|
||||
enable_cache_2500(ast);
|
||||
ast_moutdwm(ast, 0x1E6E001C, 0x00000008);
|
||||
ast_moutdwm(ast, 0x1E6E0038, 0xFFFFFF00);
|
||||
}
|
||||
|
||||
static bool ast_dram_init_2500(struct ast_private *ast)
|
||||
{
|
||||
u32 data;
|
||||
u32 max_tries = 5;
|
||||
|
||||
do {
|
||||
if (max_tries-- == 0)
|
||||
return false;
|
||||
set_mpll_2500(ast);
|
||||
reset_mmc_2500(ast);
|
||||
ddr_init_common_2500(ast);
|
||||
|
||||
data = ast_mindwm(ast, 0x1E6E2070);
|
||||
if (data & 0x01000000)
|
||||
ddr4_init_2500(ast, ast2500_ddr4_1600_timing_table);
|
||||
else
|
||||
ddr3_init_2500(ast, ast2500_ddr3_1600_timing_table);
|
||||
} while (!ddr_test_2500(ast));
|
||||
|
||||
ast_moutdwm(ast, 0x1E6E2040, ast_mindwm(ast, 0x1E6E2040) | 0x41);
|
||||
|
||||
/* Patch code */
|
||||
data = ast_mindwm(ast, 0x1E6E200C) & 0xF9FFFFFF;
|
||||
ast_moutdwm(ast, 0x1E6E200C, data | 0x10000000);
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
void ast_post_chip_2500(struct drm_device *dev)
|
||||
{
|
||||
struct ast_private *ast = dev->dev_private;
|
||||
u32 temp;
|
||||
u8 reg;
|
||||
|
||||
reg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff);
|
||||
if ((reg & 0x80) == 0) {/* vga only */
|
||||
/* Clear bus lock condition */
|
||||
ast_moutdwm(ast, 0x1e600000, 0xAEED1A03);
|
||||
ast_moutdwm(ast, 0x1e600084, 0x00010000);
|
||||
ast_moutdwm(ast, 0x1e600088, 0x00000000);
|
||||
ast_moutdwm(ast, 0x1e6e2000, 0x1688A8A8);
|
||||
ast_write32(ast, 0xf004, 0x1e6e0000);
|
||||
ast_write32(ast, 0xf000, 0x1);
|
||||
ast_write32(ast, 0x12000, 0x1688a8a8);
|
||||
while (ast_read32(ast, 0x12000) != 0x1)
|
||||
;
|
||||
|
||||
ast_write32(ast, 0x10000, 0xfc600309);
|
||||
while (ast_read32(ast, 0x10000) != 0x1)
|
||||
;
|
||||
|
||||
/* Slow down CPU/AHB CLK in VGA only mode */
|
||||
temp = ast_read32(ast, 0x12008);
|
||||
temp |= 0x73;
|
||||
ast_write32(ast, 0x12008, temp);
|
||||
|
||||
/* Reset USB port to patch USB unknown device issue */
|
||||
ast_moutdwm(ast, 0x1e6e2090, 0x20000000);
|
||||
temp = ast_mindwm(ast, 0x1e6e2094);
|
||||
temp |= 0x00004000;
|
||||
ast_moutdwm(ast, 0x1e6e2094, temp);
|
||||
temp = ast_mindwm(ast, 0x1e6e2070);
|
||||
if (temp & 0x00800000) {
|
||||
ast_moutdwm(ast, 0x1e6e207c, 0x00800000);
|
||||
mdelay(100);
|
||||
ast_moutdwm(ast, 0x1e6e2070, 0x00800000);
|
||||
}
|
||||
|
||||
if (!ast_dram_init_2500(ast))
|
||||
DRM_ERROR("DRAM init failed !\n");
|
||||
|
||||
temp = ast_mindwm(ast, 0x1e6e2040);
|
||||
ast_moutdwm(ast, 0x1e6e2040, temp | 0x40);
|
||||
}
|
||||
|
||||
/* wait ready */
|
||||
do {
|
||||
reg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff);
|
||||
} while ((reg & 0x40) == 0);
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user