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drm/amd/display: extended the programming sequence to VFlip as well
Signed-off-by: Charlene Liu <charlene.liu@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.com> Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -1316,6 +1316,9 @@ void dc_update_surfaces_for_stream(struct dc *dc,
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for (j = 0; j < context->res_ctx.pool->pipe_count; j++) {
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struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
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struct pipe_ctx *cur_pipe_ctx;
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bool is_new_pipe_surface = true;
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if (pipe_ctx->surface != surface)
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continue;
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/*lock all the MCPP if blnd is enable for DRR*/
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@ -1324,26 +1327,16 @@ void dc_update_surfaces_for_stream(struct dc *dc,
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surface_count != context->res_ctx.pool->pipe_count)) &&
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!pipe_ctx->tg->funcs->is_blanked(pipe_ctx->tg)) {
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lock_mask = PIPE_LOCK_CONTROL_MPCC_ADDR;
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core_dc->hwss.pipe_control_lock(
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core_dc,
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pipe_ctx,
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lock_mask,
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true);
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}
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}
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for (j = 0; j < context->res_ctx.pool->pipe_count; j++) {
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struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
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struct pipe_ctx *cur_pipe_ctx;
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bool is_new_pipe_surface = true;
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if (pipe_ctx->surface != surface)
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continue;
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if (update_type != UPDATE_TYPE_FAST &&
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!pipe_ctx->tg->funcs->is_blanked(pipe_ctx->tg)) {
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lock_mask = PIPE_LOCK_CONTROL_GRAPHICS |
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PIPE_LOCK_CONTROL_SCL |
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PIPE_LOCK_CONTROL_BLENDER |
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PIPE_LOCK_CONTROL_MODE;
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}
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if (lock_mask != 0) {
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core_dc->hwss.pipe_control_lock(
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core_dc,
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pipe_ctx,
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@ -1389,7 +1382,7 @@ void dc_update_surfaces_for_stream(struct dc *dc,
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}
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}
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if (update_type == UPDATE_TYPE_FAST && (lock_mask == 0))
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if ((update_type == UPDATE_TYPE_FAST) && lock_mask == 0)
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return;
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for (i = context->res_ctx.pool->pipe_count - 1; i >= 0; i--) {
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