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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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iwlwifi: trans: add a new op for getting DMA data
Op mode will need this data in order to feed FW with it. Signed-off-by: Sara Sharon <sara.sharon@intel.com> Signed-off-by: Luca Coelho <luciano.coelho@intel.com>
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@ -439,6 +439,20 @@ struct iwl_trans_txq_scd_cfg {
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int frame_limit;
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int frame_limit;
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};
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};
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/**
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* struct iwl_trans_rxq_dma_data - RX queue DMA data
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* @fr_bd_cb: DMA address of free BD cyclic buffer
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* @fr_bd_wid: Initial write index of the free BD cyclic buffer
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* @urbd_stts_wrptr: DMA address of urbd_stts_wrptr
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* @ur_bd_cb: DMA address of used BD cyclic buffer
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*/
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struct iwl_trans_rxq_dma_data {
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u64 fr_bd_cb;
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u32 fr_bd_wid;
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u64 urbd_stts_wrptr;
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u64 ur_bd_cb;
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};
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/**
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/**
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* struct iwl_trans_ops - transport specific operations
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* struct iwl_trans_ops - transport specific operations
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*
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*
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@ -559,6 +573,8 @@ struct iwl_trans_ops {
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int cmd_id, int size,
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int cmd_id, int size,
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unsigned int queue_wdg_timeout);
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unsigned int queue_wdg_timeout);
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void (*txq_free)(struct iwl_trans *trans, int queue);
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void (*txq_free)(struct iwl_trans *trans, int queue);
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int (*rxq_dma_data)(struct iwl_trans *trans, int queue,
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struct iwl_trans_rxq_dma_data *data);
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void (*txq_set_shared_mode)(struct iwl_trans *trans, u32 txq_id,
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void (*txq_set_shared_mode)(struct iwl_trans *trans, u32 txq_id,
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bool shared);
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bool shared);
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@ -947,6 +963,16 @@ iwl_trans_txq_enable_cfg(struct iwl_trans *trans, int queue, u16 ssn,
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cfg, queue_wdg_timeout);
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cfg, queue_wdg_timeout);
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}
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}
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static inline int
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iwl_trans_get_rxq_dma_data(struct iwl_trans *trans, int queue,
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struct iwl_trans_rxq_dma_data *data)
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{
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if (WARN_ON_ONCE(!trans->ops->rxq_dma_data))
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return -ENOTSUPP;
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return trans->ops->rxq_dma_data(trans, queue, data);
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}
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static inline void
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static inline void
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iwl_trans_txq_free(struct iwl_trans *trans, int queue)
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iwl_trans_txq_free(struct iwl_trans *trans, int queue)
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{
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{
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@ -2265,6 +2265,22 @@ void iwl_trans_pcie_log_scd_error(struct iwl_trans *trans, struct iwl_txq *txq)
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iwl_read_direct32(trans, FH_TX_TRB_REG(fifo)));
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iwl_read_direct32(trans, FH_TX_TRB_REG(fifo)));
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}
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}
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static int iwl_trans_pcie_rxq_dma_data(struct iwl_trans *trans, int queue,
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struct iwl_trans_rxq_dma_data *data)
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{
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struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
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if (queue >= trans->num_rx_queues || !trans_pcie->rxq)
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return -EINVAL;
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data->fr_bd_cb = trans_pcie->rxq[queue].bd_dma;
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data->urbd_stts_wrptr = trans_pcie->rxq[queue].rb_stts_dma;
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data->ur_bd_cb = trans_pcie->rxq[queue].used_bd_dma;
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data->fr_bd_wid = 0;
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return 0;
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}
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static int iwl_trans_pcie_wait_txq_empty(struct iwl_trans *trans, int txq_idx)
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static int iwl_trans_pcie_wait_txq_empty(struct iwl_trans *trans, int txq_idx)
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{
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{
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struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
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struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
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@ -3212,6 +3228,7 @@ static const struct iwl_trans_ops trans_ops_pcie_gen2 = {
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.txq_alloc = iwl_trans_pcie_dyn_txq_alloc,
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.txq_alloc = iwl_trans_pcie_dyn_txq_alloc,
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.txq_free = iwl_trans_pcie_dyn_txq_free,
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.txq_free = iwl_trans_pcie_dyn_txq_free,
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.wait_txq_empty = iwl_trans_pcie_wait_txq_empty,
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.wait_txq_empty = iwl_trans_pcie_wait_txq_empty,
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.rxq_dma_data = iwl_trans_pcie_rxq_dma_data,
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};
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};
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struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev,
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struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev,
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