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Update psci support to the arm,psci-1.0 to mt8173
Add display PWM driver to mt8173 Add mediatek general porpose timer to mt8173 -----BEGIN PGP SIGNATURE----- Version: GnuPG v2 iQIcBAABAgAGBQJWdximAAoJELQ5Ylss8dNDsZ4QAIDi9HPJpKzHCs+W/7+F3e+P LZ+fIEYzRhhKgBWCGOWmbrOAVweOhi5ja5tk2IlOcLvZceY7X03EZLsPV0WCofKW F7Hcp/Qs+VhAVinUlz5Zgx8nuS3BAd+U9iOi/2CcGczj8zYB9Un2cfV4ZqTImgol 5zgt3kXpqX3RiZ/ubkUODMsH9RLcW1yRuIyzDUlNO18GjV0+luat9Ws+fU+dMOyM RnfjLALnga3QwIol0tMFktLJpfbwCkKKtLY3kRKEjS1FFg+4ucSwnBfRetxtdEcQ ebBwF2Vh/tvx/13ewer5Xjmz/J2qRriK8WWqK88CPbSguvRjSpnwJpurGtirfT4B AbrlIRZyhjwyhw4Us2KCTnOvjmsuHUKsvGTJPyLBpBCsQ1s9cL/DDhbd+z3j5hdM qekKvGP5yygYcqyc1t5tOs5POO1Ey2/vZ4cJdfWql/0AXhwDSgjr//rUYuAAsMrJ g/ySJPN4erb3hR3CbfLwbYMW9wErTbUGGRbe3Buzx7nTd/zhax1psbakS2SyI2q9 410Plhm1iHhildOyJjAINMMqXqE4uyo1eCXxr2/Ul93Xf1epcvaerBFVE/Fk2DHc ecIN8ufWaKfkBbBCeAs1XYVeO5zbv4YyvTTw07B2A9bKs44Skk8zOhsKJIw6ydjT lU2HvzhLowA8fExy1Viy =xWtj -----END PGP SIGNATURE----- Merge tag 'v4.4-next-arm64' of https://github.com/mbgg/linux-mediatek into next/dt64 Update psci support to the arm,psci-1.0 to mt8173 Add display PWM driver to mt8173 Add mediatek general porpose timer to mt8173 * tag 'v4.4-next-arm64' of https://github.com/mbgg/linux-mediatek: arm64: dts: mediatek: mt8173 PSCI-1.0 support arm64: dts: mt8173: add MT8173 display PWM driver support node arm64: dts: mt8173: add timer node Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
commit
9205a7ade8
@ -92,6 +92,13 @@ &mmc1 {
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};
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};
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&pio {
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&pio {
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disp_pwm0_pins: disp_pwm0_pins {
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pins1 {
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pinmux = <MT8173_PIN_87_DISP_PWM0__FUNC_DISP_PWM0>;
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output-low;
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};
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};
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mmc0_pins_default: mmc0default {
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mmc0_pins_default: mmc0default {
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pins_cmd_dat {
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pins_cmd_dat {
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pinmux = <MT8173_PIN_57_MSDC0_DAT0__FUNC_MSDC0_DAT0>,
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pinmux = <MT8173_PIN_57_MSDC0_DAT0__FUNC_MSDC0_DAT0>,
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@ -190,6 +197,12 @@ pins_clk {
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};
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};
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};
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};
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&pwm0 {
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pinctrl-names = "default";
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pinctrl-0 = <&disp_pwm0_pins>;
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status = "okay";
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};
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&pwrap {
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&pwrap {
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pmic: mt6397 {
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pmic: mt6397 {
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compatible = "mediatek,mt6397";
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compatible = "mediatek,mt6397";
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@ -95,7 +95,7 @@ CPU_SLEEP_0: cpu-sleep-0 {
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};
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};
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psci {
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psci {
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compatible = "arm,psci";
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compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci";
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method = "smc";
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method = "smc";
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cpu_suspend = <0x84000001>;
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cpu_suspend = <0x84000001>;
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cpu_off = <0x84000002>;
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cpu_off = <0x84000002>;
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@ -247,6 +247,15 @@ watchdog: watchdog@10007000 {
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reg = <0 0x10007000 0 0x100>;
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reg = <0 0x10007000 0 0x100>;
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};
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};
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timer: timer@10008000 {
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compatible = "mediatek,mt8173-timer",
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"mediatek,mt6577-timer";
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reg = <0 0x10008000 0 0x1000>;
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interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&infracfg CLK_INFRA_CLK_13M>,
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<&topckgen CLK_TOP_RTC_SEL>;
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};
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pwrap: pwrap@1000d000 {
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pwrap: pwrap@1000d000 {
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compatible = "mediatek,mt8173-pwrap";
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compatible = "mediatek,mt8173-pwrap";
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reg = <0 0x1000d000 0 0x1000>;
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reg = <0 0x1000d000 0 0x1000>;
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@ -516,6 +525,28 @@ mmsys: clock-controller@14000000 {
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#clock-cells = <1>;
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#clock-cells = <1>;
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};
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};
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pwm0: pwm@1401e000 {
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compatible = "mediatek,mt8173-disp-pwm",
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"mediatek,mt6595-disp-pwm";
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reg = <0 0x1401e000 0 0x1000>;
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#pwm-cells = <2>;
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clocks = <&mmsys CLK_MM_DISP_PWM026M>,
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<&mmsys CLK_MM_DISP_PWM0MM>;
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clock-names = "main", "mm";
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status = "disabled";
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};
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pwm1: pwm@1401f000 {
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compatible = "mediatek,mt8173-disp-pwm",
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"mediatek,mt6595-disp-pwm";
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reg = <0 0x1401f000 0 0x1000>;
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#pwm-cells = <2>;
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clocks = <&mmsys CLK_MM_DISP_PWM126M>,
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<&mmsys CLK_MM_DISP_PWM1MM>;
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clock-names = "main", "mm";
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status = "disabled";
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};
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imgsys: clock-controller@15000000 {
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imgsys: clock-controller@15000000 {
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compatible = "mediatek,mt8173-imgsys", "syscon";
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compatible = "mediatek,mt8173-imgsys", "syscon";
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reg = <0 0x15000000 0 0x1000>;
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reg = <0 0x15000000 0 0x1000>;
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