mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-14 01:56:45 +07:00
Merge branch 'Reuse-ptp_qoriq-driver-for-dpaa2-ptp'
Yangbo Lu says: ==================== Reuse ptp_qoriq driver for dpaa2-ptp Although dpaa2-ptp.c driver is a fsl_mc_driver which is using MC APIs for register accessing, it's same IP block with eTSEC/DPAA/ENETC 1588 timer. This patch-set is to convert to reuse ptp_qoriq driver by using register ioremap and dropping related MC APIs. However the interrupts could only be handled by MC which fires MSIs to ARM cores. So the interrupt enabling and handling still rely on MC APIs. MC APIs for interrupt and PPS event support are also added by this patch-set. --- Changes for v2: - Allowed to compile with COMPILE_TEST. ==================== Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
David S. Miller
commit
91d0a48a48
@ -4,7 +4,8 @@ General Properties:
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- compatible Should be "fsl,etsec-ptp" for eTSEC
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Should be "fsl,fman-ptp-timer" for DPAA FMan
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Should be "fsl,enetc-ptp" for ENETC
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Should be "fsl,dpaa2-ptp" for DPAA2
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Should be "fsl,enetc-ptp" for ENETC
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- reg Offset and length of the register set for the device
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- interrupts There should be at least two interrupts. Some devices
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have as many as four PTP related interrupts.
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@ -4922,13 +4922,6 @@ L: linux-kernel@vger.kernel.org
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S: Maintained
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F: drivers/staging/fsl-dpaa2/ethsw
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DPAA2 PTP CLOCK DRIVER
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M: Yangbo Lu <yangbo.lu@nxp.com>
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L: netdev@vger.kernel.org
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S: Maintained
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F: drivers/net/ethernet/freescale/dpaa2/dpaa2-ptp*
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F: drivers/net/ethernet/freescale/dpaa2/dprtc*
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DPT_I2O SCSI RAID DRIVER
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M: Adaptec OEM Raid Solutions <aacraid@microsemi.com>
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L: linux-scsi@vger.kernel.org
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@ -6371,6 +6364,8 @@ FREESCALE QORIQ PTP CLOCK DRIVER
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M: Yangbo Lu <yangbo.lu@nxp.com>
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L: netdev@vger.kernel.org
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S: Maintained
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F: drivers/net/ethernet/freescale/dpaa2/dpaa2-ptp*
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F: drivers/net/ethernet/freescale/dpaa2/dprtc*
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F: drivers/net/ethernet/freescale/enetc/enetc_ptp.c
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F: drivers/ptp/ptp_qoriq.c
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F: drivers/ptp/ptp_qoriq_debugfs.c
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@ -609,6 +609,14 @@ smmu: iommu@5000000 {
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<GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
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};
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ptp-timer@8b95000 {
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compatible = "fsl,dpaa2-ptp";
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reg = <0x0 0x8b95000 0x0 0x100>;
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clocks = <&clockgen 4 0>;
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little-endian;
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fsl,extts-fifo;
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};
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cluster1_core0_watchdog: wdt@c000000 {
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compatible = "arm,sp805-wdt", "arm,primecell";
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reg = <0x0 0xc000000 0x0 0x1000>;
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@ -321,6 +321,14 @@ sec_jr3: jr@40000 {
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};
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};
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ptp-timer@8b95000 {
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compatible = "fsl,dpaa2-ptp";
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reg = <0x0 0x8b95000 0x0 0x100>;
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clocks = <&clockgen 4 1>;
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little-endian;
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fsl,extts-fifo;
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};
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fsl_mc: fsl-mc@80c000000 {
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compatible = "fsl,qoriq-mc";
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reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */
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@ -848,6 +848,14 @@ smmu: iommu@5000000 {
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dma-coherent;
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};
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ptp-timer@8b95000 {
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compatible = "fsl,dpaa2-ptp";
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reg = <0x0 0x8b95000 0x0 0x100>;
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clocks = <&clockgen 4 1>;
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little-endian;
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fsl,extts-fifo;
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};
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fsl_mc: fsl-mc@80c000000 {
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compatible = "fsl,qoriq-mc";
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reg = <0x00000008 0x0c000000 0 0x40>,
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@ -10,8 +10,7 @@ config FSL_DPAA2_ETH
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config FSL_DPAA2_PTP_CLOCK
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tristate "Freescale DPAA2 PTP Clock"
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depends on FSL_DPAA2_ETH
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imply PTP_1588_CLOCK
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depends on FSL_DPAA2_ETH && PTP_1588_CLOCK_QORIQ
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default y
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help
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This driver adds support for using the DPAA2 1588 timer module
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@ -5,114 +5,58 @@
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*/
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#include <linux/module.h>
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#include <linux/slab.h>
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#include <linux/ptp_clock_kernel.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/msi.h>
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#include <linux/fsl/mc.h>
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#include <linux/fsl/ptp_qoriq.h>
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#include "dpaa2-ptp.h"
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struct ptp_dpaa2_priv {
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struct fsl_mc_device *ptp_mc_dev;
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struct ptp_clock *clock;
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struct ptp_clock_info caps;
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u32 freq_comp;
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};
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/* PTP clock operations */
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static int ptp_dpaa2_adjfreq(struct ptp_clock_info *ptp, s32 ppb)
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static int dpaa2_ptp_enable(struct ptp_clock_info *ptp,
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struct ptp_clock_request *rq, int on)
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{
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struct ptp_dpaa2_priv *ptp_dpaa2 =
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container_of(ptp, struct ptp_dpaa2_priv, caps);
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struct fsl_mc_device *mc_dev = ptp_dpaa2->ptp_mc_dev;
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struct device *dev = &mc_dev->dev;
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u64 adj;
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u32 diff, tmr_add;
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int neg_adj = 0;
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int err = 0;
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struct ptp_qoriq *ptp_qoriq = container_of(ptp, struct ptp_qoriq, caps);
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struct fsl_mc_device *mc_dev;
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struct device *dev;
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u32 mask = 0;
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u32 bit;
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int err;
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if (ppb < 0) {
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neg_adj = 1;
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ppb = -ppb;
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dev = ptp_qoriq->dev;
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mc_dev = to_fsl_mc_device(dev);
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switch (rq->type) {
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case PTP_CLK_REQ_PPS:
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bit = DPRTC_EVENT_PPS;
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break;
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default:
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return -EOPNOTSUPP;
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}
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tmr_add = ptp_dpaa2->freq_comp;
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adj = tmr_add;
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adj *= ppb;
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diff = div_u64(adj, 1000000000ULL);
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tmr_add = neg_adj ? tmr_add - diff : tmr_add + diff;
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err = dprtc_set_freq_compensation(mc_dev->mc_io, 0,
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mc_dev->mc_handle, tmr_add);
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if (err)
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dev_err(dev, "dprtc_set_freq_compensation err %d\n", err);
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return err;
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}
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static int ptp_dpaa2_adjtime(struct ptp_clock_info *ptp, s64 delta)
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{
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struct ptp_dpaa2_priv *ptp_dpaa2 =
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container_of(ptp, struct ptp_dpaa2_priv, caps);
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struct fsl_mc_device *mc_dev = ptp_dpaa2->ptp_mc_dev;
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struct device *dev = &mc_dev->dev;
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s64 now;
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int err = 0;
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err = dprtc_get_time(mc_dev->mc_io, 0, mc_dev->mc_handle, &now);
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if (err) {
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dev_err(dev, "dprtc_get_time err %d\n", err);
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err = dprtc_get_irq_mask(mc_dev->mc_io, 0, mc_dev->mc_handle,
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DPRTC_IRQ_INDEX, &mask);
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if (err < 0) {
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dev_err(dev, "dprtc_get_irq_mask(): %d\n", err);
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return err;
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}
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now += delta;
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if (on)
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mask |= bit;
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else
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mask &= ~bit;
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err = dprtc_set_time(mc_dev->mc_io, 0, mc_dev->mc_handle, now);
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if (err)
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dev_err(dev, "dprtc_set_time err %d\n", err);
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return err;
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}
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static int ptp_dpaa2_gettime(struct ptp_clock_info *ptp, struct timespec64 *ts)
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{
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struct ptp_dpaa2_priv *ptp_dpaa2 =
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container_of(ptp, struct ptp_dpaa2_priv, caps);
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struct fsl_mc_device *mc_dev = ptp_dpaa2->ptp_mc_dev;
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struct device *dev = &mc_dev->dev;
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u64 ns;
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u32 remainder;
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int err = 0;
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err = dprtc_get_time(mc_dev->mc_io, 0, mc_dev->mc_handle, &ns);
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if (err) {
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dev_err(dev, "dprtc_get_time err %d\n", err);
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err = dprtc_set_irq_mask(mc_dev->mc_io, 0, mc_dev->mc_handle,
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DPRTC_IRQ_INDEX, mask);
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if (err < 0) {
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dev_err(dev, "dprtc_set_irq_mask(): %d\n", err);
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return err;
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}
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ts->tv_sec = div_u64_rem(ns, 1000000000, &remainder);
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ts->tv_nsec = remainder;
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return err;
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return 0;
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}
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static int ptp_dpaa2_settime(struct ptp_clock_info *ptp,
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const struct timespec64 *ts)
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{
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struct ptp_dpaa2_priv *ptp_dpaa2 =
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container_of(ptp, struct ptp_dpaa2_priv, caps);
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struct fsl_mc_device *mc_dev = ptp_dpaa2->ptp_mc_dev;
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struct device *dev = &mc_dev->dev;
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u64 ns;
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int err = 0;
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ns = ts->tv_sec * 1000000000ULL;
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ns += ts->tv_nsec;
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err = dprtc_set_time(mc_dev->mc_io, 0, mc_dev->mc_handle, ns);
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if (err)
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dev_err(dev, "dprtc_set_time err %d\n", err);
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return err;
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}
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static const struct ptp_clock_info ptp_dpaa2_caps = {
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static const struct ptp_clock_info dpaa2_ptp_caps = {
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.owner = THIS_MODULE,
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.name = "DPAA2 PTP Clock",
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.max_adj = 512000,
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@ -121,21 +65,58 @@ static const struct ptp_clock_info ptp_dpaa2_caps = {
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.n_per_out = 3,
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.n_pins = 0,
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.pps = 1,
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.adjfreq = ptp_dpaa2_adjfreq,
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.adjtime = ptp_dpaa2_adjtime,
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.gettime64 = ptp_dpaa2_gettime,
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.settime64 = ptp_dpaa2_settime,
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.adjfine = ptp_qoriq_adjfine,
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.adjtime = ptp_qoriq_adjtime,
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.gettime64 = ptp_qoriq_gettime,
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.settime64 = ptp_qoriq_settime,
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.enable = dpaa2_ptp_enable,
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};
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static irqreturn_t dpaa2_ptp_irq_handler_thread(int irq, void *priv)
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{
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struct ptp_qoriq *ptp_qoriq = priv;
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struct ptp_clock_event event;
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struct fsl_mc_device *mc_dev;
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struct device *dev;
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u32 status = 0;
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int err;
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dev = ptp_qoriq->dev;
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mc_dev = to_fsl_mc_device(dev);
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err = dprtc_get_irq_status(mc_dev->mc_io, 0, mc_dev->mc_handle,
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DPRTC_IRQ_INDEX, &status);
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if (unlikely(err)) {
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dev_err(dev, "dprtc_get_irq_status err %d\n", err);
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return IRQ_NONE;
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}
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if (status & DPRTC_EVENT_PPS) {
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event.type = PTP_CLOCK_PPS;
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ptp_clock_event(ptp_qoriq->clock, &event);
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}
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err = dprtc_clear_irq_status(mc_dev->mc_io, 0, mc_dev->mc_handle,
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DPRTC_IRQ_INDEX, status);
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if (unlikely(err)) {
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dev_err(dev, "dprtc_clear_irq_status err %d\n", err);
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return IRQ_NONE;
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}
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return IRQ_HANDLED;
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}
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static int dpaa2_ptp_probe(struct fsl_mc_device *mc_dev)
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{
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struct device *dev = &mc_dev->dev;
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struct ptp_dpaa2_priv *ptp_dpaa2;
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u32 tmr_add = 0;
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struct fsl_mc_device_irq *irq;
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struct ptp_qoriq *ptp_qoriq;
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struct device_node *node;
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void __iomem *base;
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int err;
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|
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ptp_dpaa2 = devm_kzalloc(dev, sizeof(*ptp_dpaa2), GFP_KERNEL);
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if (!ptp_dpaa2)
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ptp_qoriq = devm_kzalloc(dev, sizeof(*ptp_qoriq), GFP_KERNEL);
|
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if (!ptp_qoriq)
|
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return -ENOMEM;
|
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|
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err = fsl_mc_portal_allocate(mc_dev, 0, &mc_dev->mc_io);
|
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@ -154,30 +135,60 @@ static int dpaa2_ptp_probe(struct fsl_mc_device *mc_dev)
|
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goto err_free_mcp;
|
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}
|
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|
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ptp_dpaa2->ptp_mc_dev = mc_dev;
|
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ptp_qoriq->dev = dev;
|
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|
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err = dprtc_get_freq_compensation(mc_dev->mc_io, 0,
|
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mc_dev->mc_handle, &tmr_add);
|
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node = of_find_compatible_node(NULL, NULL, "fsl,dpaa2-ptp");
|
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if (!node) {
|
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err = -ENODEV;
|
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goto err_close;
|
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}
|
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|
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dev->of_node = node;
|
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|
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base = of_iomap(node, 0);
|
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if (!base) {
|
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err = -ENOMEM;
|
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goto err_close;
|
||||
}
|
||||
|
||||
err = fsl_mc_allocate_irqs(mc_dev);
|
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if (err) {
|
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dev_err(dev, "dprtc_get_freq_compensation err %d\n", err);
|
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goto err_close;
|
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dev_err(dev, "MC irqs allocation failed\n");
|
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goto err_unmap;
|
||||
}
|
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|
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ptp_dpaa2->freq_comp = tmr_add;
|
||||
ptp_dpaa2->caps = ptp_dpaa2_caps;
|
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irq = mc_dev->irqs[0];
|
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ptp_qoriq->irq = irq->msi_desc->irq;
|
||||
|
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ptp_dpaa2->clock = ptp_clock_register(&ptp_dpaa2->caps, dev);
|
||||
if (IS_ERR(ptp_dpaa2->clock)) {
|
||||
err = PTR_ERR(ptp_dpaa2->clock);
|
||||
goto err_close;
|
||||
err = devm_request_threaded_irq(dev, ptp_qoriq->irq, NULL,
|
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dpaa2_ptp_irq_handler_thread,
|
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IRQF_NO_SUSPEND | IRQF_ONESHOT,
|
||||
dev_name(dev), ptp_qoriq);
|
||||
if (err < 0) {
|
||||
dev_err(dev, "devm_request_threaded_irq(): %d\n", err);
|
||||
goto err_free_mc_irq;
|
||||
}
|
||||
|
||||
dpaa2_phc_index = ptp_clock_index(ptp_dpaa2->clock);
|
||||
err = dprtc_set_irq_enable(mc_dev->mc_io, 0, mc_dev->mc_handle,
|
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DPRTC_IRQ_INDEX, 1);
|
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if (err < 0) {
|
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dev_err(dev, "dprtc_set_irq_enable(): %d\n", err);
|
||||
goto err_free_mc_irq;
|
||||
}
|
||||
|
||||
dev_set_drvdata(dev, ptp_dpaa2);
|
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err = ptp_qoriq_init(ptp_qoriq, base, &dpaa2_ptp_caps);
|
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if (err)
|
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goto err_free_mc_irq;
|
||||
|
||||
dpaa2_phc_index = ptp_qoriq->phc_index;
|
||||
dev_set_drvdata(dev, ptp_qoriq);
|
||||
|
||||
return 0;
|
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|
||||
err_free_mc_irq:
|
||||
fsl_mc_free_irqs(mc_dev);
|
||||
err_unmap:
|
||||
iounmap(base);
|
||||
err_close:
|
||||
dprtc_close(mc_dev->mc_io, 0, mc_dev->mc_handle);
|
||||
err_free_mcp:
|
||||
@ -188,12 +199,15 @@ static int dpaa2_ptp_probe(struct fsl_mc_device *mc_dev)
|
||||
|
||||
static int dpaa2_ptp_remove(struct fsl_mc_device *mc_dev)
|
||||
{
|
||||
struct ptp_dpaa2_priv *ptp_dpaa2;
|
||||
struct device *dev = &mc_dev->dev;
|
||||
struct ptp_qoriq *ptp_qoriq;
|
||||
|
||||
ptp_dpaa2 = dev_get_drvdata(dev);
|
||||
ptp_clock_unregister(ptp_dpaa2->clock);
|
||||
ptp_qoriq = dev_get_drvdata(dev);
|
||||
|
||||
dpaa2_phc_index = -1;
|
||||
ptp_qoriq_free(ptp_qoriq);
|
||||
|
||||
fsl_mc_free_irqs(mc_dev);
|
||||
dprtc_close(mc_dev->mc_io, 0, mc_dev->mc_handle);
|
||||
fsl_mc_portal_free(mc_dev->mc_io);
|
||||
|
||||
|
||||
@ -17,22 +17,54 @@
|
||||
#define DPRTC_CMDID_CLOSE DPRTC_CMD(0x800)
|
||||
#define DPRTC_CMDID_OPEN DPRTC_CMD(0x810)
|
||||
|
||||
#define DPRTC_CMDID_SET_FREQ_COMPENSATION DPRTC_CMD(0x1d1)
|
||||
#define DPRTC_CMDID_GET_FREQ_COMPENSATION DPRTC_CMD(0x1d2)
|
||||
#define DPRTC_CMDID_GET_TIME DPRTC_CMD(0x1d3)
|
||||
#define DPRTC_CMDID_SET_TIME DPRTC_CMD(0x1d4)
|
||||
#define DPRTC_CMDID_SET_IRQ_ENABLE DPRTC_CMD(0x012)
|
||||
#define DPRTC_CMDID_GET_IRQ_ENABLE DPRTC_CMD(0x013)
|
||||
#define DPRTC_CMDID_SET_IRQ_MASK DPRTC_CMD(0x014)
|
||||
#define DPRTC_CMDID_GET_IRQ_MASK DPRTC_CMD(0x015)
|
||||
#define DPRTC_CMDID_GET_IRQ_STATUS DPRTC_CMD(0x016)
|
||||
#define DPRTC_CMDID_CLEAR_IRQ_STATUS DPRTC_CMD(0x017)
|
||||
|
||||
#pragma pack(push, 1)
|
||||
struct dprtc_cmd_open {
|
||||
__le32 dprtc_id;
|
||||
};
|
||||
|
||||
struct dprtc_get_freq_compensation {
|
||||
__le32 freq_compensation;
|
||||
struct dprtc_cmd_get_irq {
|
||||
__le32 pad;
|
||||
u8 irq_index;
|
||||
};
|
||||
|
||||
struct dprtc_time {
|
||||
__le64 time;
|
||||
struct dprtc_cmd_set_irq_enable {
|
||||
u8 en;
|
||||
u8 pad[3];
|
||||
u8 irq_index;
|
||||
};
|
||||
|
||||
struct dprtc_rsp_get_irq_enable {
|
||||
u8 en;
|
||||
};
|
||||
|
||||
struct dprtc_cmd_set_irq_mask {
|
||||
__le32 mask;
|
||||
u8 irq_index;
|
||||
};
|
||||
|
||||
struct dprtc_rsp_get_irq_mask {
|
||||
__le32 mask;
|
||||
};
|
||||
|
||||
struct dprtc_cmd_get_irq_status {
|
||||
__le32 status;
|
||||
u8 irq_index;
|
||||
};
|
||||
|
||||
struct dprtc_rsp_get_irq_status {
|
||||
__le32 status;
|
||||
};
|
||||
|
||||
struct dprtc_cmd_clear_irq_status {
|
||||
__le32 status;
|
||||
u8 irq_index;
|
||||
};
|
||||
|
||||
#pragma pack(pop)
|
||||
|
||||
@ -74,121 +74,220 @@ int dprtc_close(struct fsl_mc_io *mc_io,
|
||||
}
|
||||
|
||||
/**
|
||||
* dprtc_set_freq_compensation() - Sets a new frequency compensation value.
|
||||
* dprtc_set_irq_enable() - Set overall interrupt state.
|
||||
* @mc_io: Pointer to MC portal's I/O object
|
||||
* @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
|
||||
* @token: Token of DPRTC object
|
||||
* @irq_index: The interrupt index to configure
|
||||
* @en: Interrupt state - enable = 1, disable = 0
|
||||
*
|
||||
* @mc_io: Pointer to MC portal's I/O object
|
||||
* @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
|
||||
* @token: Token of DPRTC object
|
||||
* @freq_compensation: The new frequency compensation value to set.
|
||||
* Allows GPP software to control when interrupts are generated.
|
||||
* Each interrupt can have up to 32 causes. The enable/disable control's the
|
||||
* overall interrupt state. if the interrupt is disabled no causes will cause
|
||||
* an interrupt.
|
||||
*
|
||||
* Return: '0' on Success; Error code otherwise.
|
||||
*/
|
||||
int dprtc_set_freq_compensation(struct fsl_mc_io *mc_io,
|
||||
u32 cmd_flags,
|
||||
u16 token,
|
||||
u32 freq_compensation)
|
||||
int dprtc_set_irq_enable(struct fsl_mc_io *mc_io,
|
||||
u32 cmd_flags,
|
||||
u16 token,
|
||||
u8 irq_index,
|
||||
u8 en)
|
||||
{
|
||||
struct dprtc_get_freq_compensation *cmd_params;
|
||||
struct dprtc_cmd_set_irq_enable *cmd_params;
|
||||
struct fsl_mc_command cmd = { 0 };
|
||||
|
||||
cmd.header = mc_encode_cmd_header(DPRTC_CMDID_SET_FREQ_COMPENSATION,
|
||||
cmd.header = mc_encode_cmd_header(DPRTC_CMDID_SET_IRQ_ENABLE,
|
||||
cmd_flags,
|
||||
token);
|
||||
cmd_params = (struct dprtc_get_freq_compensation *)cmd.params;
|
||||
cmd_params->freq_compensation = cpu_to_le32(freq_compensation);
|
||||
cmd_params = (struct dprtc_cmd_set_irq_enable *)cmd.params;
|
||||
cmd_params->irq_index = irq_index;
|
||||
cmd_params->en = en;
|
||||
|
||||
return mc_send_command(mc_io, &cmd);
|
||||
}
|
||||
|
||||
/**
|
||||
* dprtc_get_freq_compensation() - Retrieves the frequency compensation value
|
||||
*
|
||||
* @mc_io: Pointer to MC portal's I/O object
|
||||
* @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
|
||||
* @token: Token of DPRTC object
|
||||
* @freq_compensation: Frequency compensation value
|
||||
* dprtc_get_irq_enable() - Get overall interrupt state
|
||||
* @mc_io: Pointer to MC portal's I/O object
|
||||
* @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
|
||||
* @token: Token of DPRTC object
|
||||
* @irq_index: The interrupt index to configure
|
||||
* @en: Returned interrupt state - enable = 1, disable = 0
|
||||
*
|
||||
* Return: '0' on Success; Error code otherwise.
|
||||
*/
|
||||
int dprtc_get_freq_compensation(struct fsl_mc_io *mc_io,
|
||||
u32 cmd_flags,
|
||||
u16 token,
|
||||
u32 *freq_compensation)
|
||||
int dprtc_get_irq_enable(struct fsl_mc_io *mc_io,
|
||||
u32 cmd_flags,
|
||||
u16 token,
|
||||
u8 irq_index,
|
||||
u8 *en)
|
||||
{
|
||||
struct dprtc_get_freq_compensation *rsp_params;
|
||||
struct dprtc_rsp_get_irq_enable *rsp_params;
|
||||
struct dprtc_cmd_get_irq *cmd_params;
|
||||
struct fsl_mc_command cmd = { 0 };
|
||||
int err;
|
||||
|
||||
cmd.header = mc_encode_cmd_header(DPRTC_CMDID_GET_FREQ_COMPENSATION,
|
||||
cmd.header = mc_encode_cmd_header(DPRTC_CMDID_GET_IRQ_ENABLE,
|
||||
cmd_flags,
|
||||
token);
|
||||
cmd_params = (struct dprtc_cmd_get_irq *)cmd.params;
|
||||
cmd_params->irq_index = irq_index;
|
||||
|
||||
err = mc_send_command(mc_io, &cmd);
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
rsp_params = (struct dprtc_get_freq_compensation *)cmd.params;
|
||||
*freq_compensation = le32_to_cpu(rsp_params->freq_compensation);
|
||||
rsp_params = (struct dprtc_rsp_get_irq_enable *)cmd.params;
|
||||
*en = rsp_params->en;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* dprtc_get_time() - Returns the current RTC time.
|
||||
*
|
||||
* dprtc_set_irq_mask() - Set interrupt mask.
|
||||
* @mc_io: Pointer to MC portal's I/O object
|
||||
* @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
|
||||
* @token: Token of DPRTC object
|
||||
* @time: Current RTC time.
|
||||
* @irq_index: The interrupt index to configure
|
||||
* @mask: Event mask to trigger interrupt;
|
||||
* each bit:
|
||||
* 0 = ignore event
|
||||
* 1 = consider event for asserting IRQ
|
||||
*
|
||||
* Every interrupt can have up to 32 causes and the interrupt model supports
|
||||
* masking/unmasking each cause independently
|
||||
*
|
||||
* Return: '0' on Success; Error code otherwise.
|
||||
*/
|
||||
int dprtc_get_time(struct fsl_mc_io *mc_io,
|
||||
u32 cmd_flags,
|
||||
u16 token,
|
||||
uint64_t *time)
|
||||
int dprtc_set_irq_mask(struct fsl_mc_io *mc_io,
|
||||
u32 cmd_flags,
|
||||
u16 token,
|
||||
u8 irq_index,
|
||||
u32 mask)
|
||||
{
|
||||
struct dprtc_time *rsp_params;
|
||||
struct fsl_mc_command cmd = { 0 };
|
||||
int err;
|
||||
|
||||
cmd.header = mc_encode_cmd_header(DPRTC_CMDID_GET_TIME,
|
||||
cmd_flags,
|
||||
token);
|
||||
|
||||
err = mc_send_command(mc_io, &cmd);
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
rsp_params = (struct dprtc_time *)cmd.params;
|
||||
*time = le64_to_cpu(rsp_params->time);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* dprtc_set_time() - Updates current RTC time.
|
||||
*
|
||||
* @mc_io: Pointer to MC portal's I/O object
|
||||
* @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
|
||||
* @token: Token of DPRTC object
|
||||
* @time: New RTC time.
|
||||
*
|
||||
* Return: '0' on Success; Error code otherwise.
|
||||
*/
|
||||
int dprtc_set_time(struct fsl_mc_io *mc_io,
|
||||
u32 cmd_flags,
|
||||
u16 token,
|
||||
uint64_t time)
|
||||
{
|
||||
struct dprtc_time *cmd_params;
|
||||
struct dprtc_cmd_set_irq_mask *cmd_params;
|
||||
struct fsl_mc_command cmd = { 0 };
|
||||
|
||||
cmd.header = mc_encode_cmd_header(DPRTC_CMDID_SET_TIME,
|
||||
cmd.header = mc_encode_cmd_header(DPRTC_CMDID_SET_IRQ_MASK,
|
||||
cmd_flags,
|
||||
token);
|
||||
cmd_params = (struct dprtc_time *)cmd.params;
|
||||
cmd_params->time = cpu_to_le64(time);
|
||||
cmd_params = (struct dprtc_cmd_set_irq_mask *)cmd.params;
|
||||
cmd_params->mask = cpu_to_le32(mask);
|
||||
cmd_params->irq_index = irq_index;
|
||||
|
||||
return mc_send_command(mc_io, &cmd);
|
||||
}
|
||||
|
||||
/**
|
||||
* dprtc_get_irq_mask() - Get interrupt mask.
|
||||
* @mc_io: Pointer to MC portal's I/O object
|
||||
* @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
|
||||
* @token: Token of DPRTC object
|
||||
* @irq_index: The interrupt index to configure
|
||||
* @mask: Returned event mask to trigger interrupt
|
||||
*
|
||||
* Every interrupt can have up to 32 causes and the interrupt model supports
|
||||
* masking/unmasking each cause independently
|
||||
*
|
||||
* Return: '0' on Success; Error code otherwise.
|
||||
*/
|
||||
int dprtc_get_irq_mask(struct fsl_mc_io *mc_io,
|
||||
u32 cmd_flags,
|
||||
u16 token,
|
||||
u8 irq_index,
|
||||
u32 *mask)
|
||||
{
|
||||
struct dprtc_rsp_get_irq_mask *rsp_params;
|
||||
struct dprtc_cmd_get_irq *cmd_params;
|
||||
struct fsl_mc_command cmd = { 0 };
|
||||
int err;
|
||||
|
||||
cmd.header = mc_encode_cmd_header(DPRTC_CMDID_GET_IRQ_MASK,
|
||||
cmd_flags,
|
||||
token);
|
||||
cmd_params = (struct dprtc_cmd_get_irq *)cmd.params;
|
||||
cmd_params->irq_index = irq_index;
|
||||
|
||||
err = mc_send_command(mc_io, &cmd);
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
rsp_params = (struct dprtc_rsp_get_irq_mask *)cmd.params;
|
||||
*mask = le32_to_cpu(rsp_params->mask);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* dprtc_get_irq_status() - Get the current status of any pending interrupts.
|
||||
*
|
||||
* @mc_io: Pointer to MC portal's I/O object
|
||||
* @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
|
||||
* @token: Token of DPRTC object
|
||||
* @irq_index: The interrupt index to configure
|
||||
* @status: Returned interrupts status - one bit per cause:
|
||||
* 0 = no interrupt pending
|
||||
* 1 = interrupt pending
|
||||
*
|
||||
* Return: '0' on Success; Error code otherwise.
|
||||
*/
|
||||
int dprtc_get_irq_status(struct fsl_mc_io *mc_io,
|
||||
u32 cmd_flags,
|
||||
u16 token,
|
||||
u8 irq_index,
|
||||
u32 *status)
|
||||
{
|
||||
struct dprtc_cmd_get_irq_status *cmd_params;
|
||||
struct dprtc_rsp_get_irq_status *rsp_params;
|
||||
struct fsl_mc_command cmd = { 0 };
|
||||
int err;
|
||||
|
||||
cmd.header = mc_encode_cmd_header(DPRTC_CMDID_GET_IRQ_STATUS,
|
||||
cmd_flags,
|
||||
token);
|
||||
cmd_params = (struct dprtc_cmd_get_irq_status *)cmd.params;
|
||||
cmd_params->status = cpu_to_le32(*status);
|
||||
cmd_params->irq_index = irq_index;
|
||||
|
||||
err = mc_send_command(mc_io, &cmd);
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
rsp_params = (struct dprtc_rsp_get_irq_status *)cmd.params;
|
||||
*status = le32_to_cpu(rsp_params->status);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* dprtc_clear_irq_status() - Clear a pending interrupt's status
|
||||
*
|
||||
* @mc_io: Pointer to MC portal's I/O object
|
||||
* @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
|
||||
* @token: Token of DPRTC object
|
||||
* @irq_index: The interrupt index to configure
|
||||
* @status: Bits to clear (W1C) - one bit per cause:
|
||||
* 0 = don't change
|
||||
* 1 = clear status bit
|
||||
*
|
||||
* Return: '0' on Success; Error code otherwise.
|
||||
*/
|
||||
int dprtc_clear_irq_status(struct fsl_mc_io *mc_io,
|
||||
u32 cmd_flags,
|
||||
u16 token,
|
||||
u8 irq_index,
|
||||
u32 status)
|
||||
{
|
||||
struct dprtc_cmd_clear_irq_status *cmd_params;
|
||||
struct fsl_mc_command cmd = { 0 };
|
||||
|
||||
cmd.header = mc_encode_cmd_header(DPRTC_CMDID_CLEAR_IRQ_STATUS,
|
||||
cmd_flags,
|
||||
token);
|
||||
cmd_params = (struct dprtc_cmd_clear_irq_status *)cmd.params;
|
||||
cmd_params->irq_index = irq_index;
|
||||
cmd_params->status = cpu_to_le32(status);
|
||||
|
||||
return mc_send_command(mc_io, &cmd);
|
||||
}
|
||||
|
||||
@ -13,6 +13,14 @@
|
||||
|
||||
struct fsl_mc_io;
|
||||
|
||||
/**
|
||||
* Number of irq's
|
||||
*/
|
||||
#define DPRTC_MAX_IRQ_NUM 1
|
||||
#define DPRTC_IRQ_INDEX 0
|
||||
|
||||
#define DPRTC_EVENT_PPS 0x08000000
|
||||
|
||||
int dprtc_open(struct fsl_mc_io *mc_io,
|
||||
u32 cmd_flags,
|
||||
int dprtc_id,
|
||||
@ -22,24 +30,40 @@ int dprtc_close(struct fsl_mc_io *mc_io,
|
||||
u32 cmd_flags,
|
||||
u16 token);
|
||||
|
||||
int dprtc_set_freq_compensation(struct fsl_mc_io *mc_io,
|
||||
u32 cmd_flags,
|
||||
u16 token,
|
||||
u32 freq_compensation);
|
||||
int dprtc_set_irq_enable(struct fsl_mc_io *mc_io,
|
||||
u32 cmd_flags,
|
||||
u16 token,
|
||||
u8 irq_index,
|
||||
u8 en);
|
||||
|
||||
int dprtc_get_freq_compensation(struct fsl_mc_io *mc_io,
|
||||
u32 cmd_flags,
|
||||
u16 token,
|
||||
u32 *freq_compensation);
|
||||
int dprtc_get_irq_enable(struct fsl_mc_io *mc_io,
|
||||
u32 cmd_flags,
|
||||
u16 token,
|
||||
u8 irq_index,
|
||||
u8 *en);
|
||||
|
||||
int dprtc_get_time(struct fsl_mc_io *mc_io,
|
||||
u32 cmd_flags,
|
||||
u16 token,
|
||||
uint64_t *time);
|
||||
int dprtc_set_irq_mask(struct fsl_mc_io *mc_io,
|
||||
u32 cmd_flags,
|
||||
u16 token,
|
||||
u8 irq_index,
|
||||
u32 mask);
|
||||
|
||||
int dprtc_set_time(struct fsl_mc_io *mc_io,
|
||||
u32 cmd_flags,
|
||||
u16 token,
|
||||
uint64_t time);
|
||||
int dprtc_get_irq_mask(struct fsl_mc_io *mc_io,
|
||||
u32 cmd_flags,
|
||||
u16 token,
|
||||
u8 irq_index,
|
||||
u32 *mask);
|
||||
|
||||
int dprtc_get_irq_status(struct fsl_mc_io *mc_io,
|
||||
u32 cmd_flags,
|
||||
u16 token,
|
||||
u8 irq_index,
|
||||
u32 *status);
|
||||
|
||||
int dprtc_clear_irq_status(struct fsl_mc_io *mc_io,
|
||||
u32 cmd_flags,
|
||||
u16 token,
|
||||
u8 irq_index,
|
||||
u32 status);
|
||||
|
||||
#endif /* __FSL_DPRTC_H */
|
||||
|
||||
@ -44,7 +44,7 @@ config PTP_1588_CLOCK_DTE
|
||||
|
||||
config PTP_1588_CLOCK_QORIQ
|
||||
tristate "Freescale QorIQ 1588 timer as PTP clock"
|
||||
depends on GIANFAR || FSL_DPAA_ETH || FSL_ENETC || FSL_ENETC_VF
|
||||
depends on GIANFAR || FSL_DPAA_ETH || FSL_DPAA2_ETH || FSL_ENETC || FSL_ENETC_VF || COMPILE_TEST
|
||||
depends on PTP_1588_CLOCK
|
||||
default y
|
||||
help
|
||||
|
||||
Loading…
Reference in New Issue
Block a user