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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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drm/amd/powerplay: add multimedia power gating support for Fiji.
Acked-by: Jammy Zhou <Jammy.Zhou@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com>
This commit is contained in:
Eric Huang
Alex Deucher
parent
b57fd5663e
commit
91c4c98155
@ -7,7 +7,8 @@ HARDWARE_MGR = hwmgr.o processpptables.o functiontables.o \
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cz_clockpowergating.o \
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tonga_processpptables.o ppatomctrl.o \
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tonga_hwmgr.o pppcielanes.o tonga_thermal.o\
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fiji_powertune.o fiji_hwmgr.o tonga_clockpowergating.o
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fiji_powertune.o fiji_hwmgr.o tonga_clockpowergating.o \
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fiji_clockpowergating.o
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AMD_PP_HWMGR = $(addprefix $(AMD_PP_PATH)/hwmgr/,$(HARDWARE_MGR))
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114
drivers/gpu/drm/amd/powerplay/hwmgr/fiji_clockpowergating.c
Normal file
114
drivers/gpu/drm/amd/powerplay/hwmgr/fiji_clockpowergating.c
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@ -0,0 +1,114 @@
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/*
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* Copyright 2015 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#include "hwmgr.h"
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#include "fiji_clockpowergating.h"
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#include "fiji_ppsmc.h"
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#include "fiji_hwmgr.h"
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int fiji_phm_disable_clock_power_gating(struct pp_hwmgr *hwmgr)
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{
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struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
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data->uvd_power_gated = false;
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data->vce_power_gated = false;
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data->samu_power_gated = false;
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data->acp_power_gated = false;
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return 0;
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}
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int fiji_phm_powergate_uvd(struct pp_hwmgr *hwmgr, bool bgate)
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{
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struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
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if (data->uvd_power_gated == bgate)
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return 0;
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data->uvd_power_gated = bgate;
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if (bgate)
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fiji_update_uvd_dpm(hwmgr, true);
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else
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fiji_update_uvd_dpm(hwmgr, false);
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return 0;
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}
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int fiji_phm_powergate_vce(struct pp_hwmgr *hwmgr, bool bgate)
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{
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struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
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struct phm_set_power_state_input states;
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const struct pp_power_state *pcurrent;
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struct pp_power_state *requested;
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if (data->vce_power_gated == bgate)
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return 0;
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data->vce_power_gated = bgate;
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pcurrent = hwmgr->current_ps;
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requested = hwmgr->request_ps;
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states.pcurrent_state = &(pcurrent->hardware);
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states.pnew_state = &(requested->hardware);
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fiji_update_vce_dpm(hwmgr, &states);
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fiji_enable_disable_vce_dpm(hwmgr, !bgate);
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return 0;
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}
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int fiji_phm_powergate_samu(struct pp_hwmgr *hwmgr, bool bgate)
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{
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struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
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if (data->samu_power_gated == bgate)
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return 0;
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data->samu_power_gated = bgate;
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if (bgate)
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fiji_update_samu_dpm(hwmgr, true);
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else
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fiji_update_samu_dpm(hwmgr, false);
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return 0;
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}
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int fiji_phm_powergate_acp(struct pp_hwmgr *hwmgr, bool bgate)
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{
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struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
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if (data->acp_power_gated == bgate)
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return 0;
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data->acp_power_gated = bgate;
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if (bgate)
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fiji_update_acp_dpm(hwmgr, true);
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else
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fiji_update_acp_dpm(hwmgr, false);
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return 0;
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}
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35
drivers/gpu/drm/amd/powerplay/hwmgr/fiji_clockpowergating.h
Normal file
35
drivers/gpu/drm/amd/powerplay/hwmgr/fiji_clockpowergating.h
Normal file
@ -0,0 +1,35 @@
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/*
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* Copyright 2015 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#ifndef _FIJI_CLOCK_POWER_GATING_H_
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#define _FIJI_CLOCK_POWER_GATING_H_
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#include "fiji_hwmgr.h"
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#include "pp_asicblocks.h"
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extern int fiji_phm_powergate_vce(struct pp_hwmgr *hwmgr, bool bgate);
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extern int fiji_phm_powergate_uvd(struct pp_hwmgr *hwmgr, bool bgate);
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extern int fiji_phm_powergate_samu(struct pp_hwmgr *hwmgr, bool bgate);
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extern int fiji_phm_powergate_acp(struct pp_hwmgr *hwmgr, bool bgate);
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extern int fiji_phm_disable_clock_power_gating(struct pp_hwmgr *hwmgr);
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#endif /* _TONGA_CLOCK_POWER_GATING_H_ */
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@ -51,6 +51,8 @@
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#include "pp_acpi.h"
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#include "amd_pcie_helpers.h"
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#include "fiji_clockpowergating.h"
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#define VOLTAGE_SCALE 4
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#define SMC_RAM_END 0x40000
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#define VDDC_VDDCI_DELTA 300
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@ -4385,14 +4387,70 @@ static int fiji_generate_dpm_level_enable_mask(
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return 0;
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}
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static int fiji_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable)
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int fiji_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable)
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{
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return smum_send_msg_to_smc(hwmgr->smumgr, enable ?
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(PPSMC_Msg)PPSMC_MSG_UVDDPM_Enable :
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(PPSMC_Msg)PPSMC_MSG_UVDDPM_Disable);
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}
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int fiji_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable)
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{
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return smum_send_msg_to_smc(hwmgr->smumgr, enable?
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PPSMC_MSG_VCEDPM_Enable :
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PPSMC_MSG_VCEDPM_Disable);
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}
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static int fiji_update_vce_dpm(struct pp_hwmgr *hwmgr, const void *input)
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int fiji_enable_disable_samu_dpm(struct pp_hwmgr *hwmgr, bool enable)
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{
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return smum_send_msg_to_smc(hwmgr->smumgr, enable?
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PPSMC_MSG_SAMUDPM_Enable :
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PPSMC_MSG_SAMUDPM_Disable);
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}
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int fiji_enable_disable_acp_dpm(struct pp_hwmgr *hwmgr, bool enable)
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{
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return smum_send_msg_to_smc(hwmgr->smumgr, enable?
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PPSMC_MSG_ACPDPM_Enable :
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PPSMC_MSG_ACPDPM_Disable);
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}
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int fiji_update_uvd_dpm(struct pp_hwmgr *hwmgr, bool bgate)
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{
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struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
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uint32_t mm_boot_level_offset, mm_boot_level_value;
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struct phm_ppt_v1_information *table_info =
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(struct phm_ppt_v1_information *)(hwmgr->pptable);
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if (!bgate) {
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data->smc_state_table.UvdBootLevel = 0;
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if (table_info->mm_dep_table->count > 0)
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data->smc_state_table.UvdBootLevel =
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(uint8_t) (table_info->mm_dep_table->count - 1);
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mm_boot_level_offset = data->dpm_table_start +
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offsetof(SMU73_Discrete_DpmTable, UvdBootLevel);
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mm_boot_level_offset /= 4;
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mm_boot_level_offset *= 4;
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mm_boot_level_value = cgs_read_ind_register(hwmgr->device,
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CGS_IND_REG__SMC, mm_boot_level_offset);
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mm_boot_level_value &= 0x00FFFFFF;
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mm_boot_level_value |= data->smc_state_table.UvdBootLevel << 24;
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cgs_write_ind_register(hwmgr->device,
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CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
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if (!phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
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PHM_PlatformCaps_UVDDPM) ||
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phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
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PHM_PlatformCaps_StablePState))
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smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
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PPSMC_MSG_UVDDPM_SetEnabledMask,
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(uint32_t)(1 << data->smc_state_table.UvdBootLevel));
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}
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return fiji_enable_disable_uvd_dpm(hwmgr, !bgate);
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}
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int fiji_update_vce_dpm(struct pp_hwmgr *hwmgr, const void *input)
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{
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const struct phm_set_power_state_input *states =
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(const struct phm_set_power_state_input *)input;
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@ -4438,6 +4496,68 @@ static int fiji_update_vce_dpm(struct pp_hwmgr *hwmgr, const void *input)
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return 0;
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}
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int fiji_update_samu_dpm(struct pp_hwmgr *hwmgr, bool bgate)
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{
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struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
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uint32_t mm_boot_level_offset, mm_boot_level_value;
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struct phm_ppt_v1_information *table_info =
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(struct phm_ppt_v1_information *)(hwmgr->pptable);
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if (!bgate) {
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data->smc_state_table.SamuBootLevel =
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(uint8_t) (table_info->mm_dep_table->count - 1);
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mm_boot_level_offset = data->dpm_table_start +
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offsetof(SMU73_Discrete_DpmTable, SamuBootLevel);
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mm_boot_level_offset /= 4;
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mm_boot_level_offset *= 4;
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mm_boot_level_value = cgs_read_ind_register(hwmgr->device,
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CGS_IND_REG__SMC, mm_boot_level_offset);
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mm_boot_level_value &= 0xFFFFFF00;
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mm_boot_level_value |= data->smc_state_table.SamuBootLevel << 0;
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cgs_write_ind_register(hwmgr->device,
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CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
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if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
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PHM_PlatformCaps_StablePState))
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smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
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PPSMC_MSG_SAMUDPM_SetEnabledMask,
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(uint32_t)(1 << data->smc_state_table.SamuBootLevel));
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}
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return fiji_enable_disable_samu_dpm(hwmgr, !bgate);
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}
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int fiji_update_acp_dpm(struct pp_hwmgr *hwmgr, bool bgate)
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{
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struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
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uint32_t mm_boot_level_offset, mm_boot_level_value;
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struct phm_ppt_v1_information *table_info =
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(struct phm_ppt_v1_information *)(hwmgr->pptable);
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if (!bgate) {
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data->smc_state_table.AcpBootLevel =
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(uint8_t) (table_info->mm_dep_table->count - 1);
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mm_boot_level_offset = data->dpm_table_start +
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offsetof(SMU73_Discrete_DpmTable, AcpBootLevel);
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mm_boot_level_offset /= 4;
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mm_boot_level_offset *= 4;
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mm_boot_level_value = cgs_read_ind_register(hwmgr->device,
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CGS_IND_REG__SMC, mm_boot_level_offset);
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mm_boot_level_value &= 0xFFFF00FF;
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mm_boot_level_value |= data->smc_state_table.AcpBootLevel << 8;
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cgs_write_ind_register(hwmgr->device,
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CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
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if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
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PHM_PlatformCaps_StablePState))
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smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
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PPSMC_MSG_ACPDPM_SetEnabledMask,
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(uint32_t)(1 << data->smc_state_table.AcpBootLevel));
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}
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return fiji_enable_disable_acp_dpm(hwmgr, !bgate);
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}
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static int fiji_update_sclk_threshold(struct pp_hwmgr *hwmgr)
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{
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struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
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@ -4747,6 +4867,9 @@ static const struct pp_hwmgr_func fiji_hwmgr_funcs = {
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.get_sclk = &fiji_dpm_get_sclk,
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.get_mclk = &fiji_dpm_get_mclk,
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.print_current_perforce_level = &fiji_print_current_perforce_level,
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.powergate_uvd = &fiji_phm_powergate_uvd,
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.powergate_vce = &fiji_phm_powergate_vce,
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.disable_clock_power_gating = &fiji_phm_disable_clock_power_gating,
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};
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int fiji_hwmgr_init(struct pp_hwmgr *hwmgr)
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@ -339,6 +339,11 @@ enum Fiji_I2CLineID {
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extern int tonga_initializa_dynamic_state_adjustment_rule_settings(struct pp_hwmgr *hwmgr);
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extern int tonga_hwmgr_backend_fini(struct pp_hwmgr *hwmgr);
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extern int tonga_get_mc_microcode_version (struct pp_hwmgr *hwmgr);
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int fiji_update_vce_dpm(struct pp_hwmgr *hwmgr, const void *input);
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int fiji_update_uvd_dpm(struct pp_hwmgr *hwmgr, bool bgate);
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int fiji_update_samu_dpm(struct pp_hwmgr *hwmgr, bool bgate);
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int fiji_update_acp_dpm(struct pp_hwmgr *hwmgr, bool bgate);
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int fiji_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable);
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#define PP_HOST_TO_SMC_UL(X) cpu_to_be32(X)
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#define PP_SMC_TO_HOST_UL(X) be32_to_cpu(X)
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