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[PATCH] sky2: use standard pci register capabilties for error register
Use the standard pci capability mechanism to access PCI express error registers, rather than hard coding the offset. Mask off the PCI express error from ever occuring on non-PCI express systems. Signed-off-by: Stephen Hemminger <shemminger@osdl.org> Signed-off-by: Jeff Garzik <jeff@garzik.org>
This commit is contained in:
Stephen Hemminger
Jeff Garzik
parent
e0ed545903
commit
91aeb3edbc
@ -2093,7 +2093,7 @@ static void sky2_hw_intr(struct sky2_hw *hw)
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sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
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sky2_pci_write16(hw, PCI_STATUS,
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pci_err | PCI_STATUS_ERROR_BITS);
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pci_err | PCI_STATUS_ERROR_BITS);
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sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
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}
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@ -2101,7 +2101,8 @@ static void sky2_hw_intr(struct sky2_hw *hw)
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/* PCI-Express uncorrectable Error occurred */
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u32 pex_err;
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pex_err = sky2_pci_read32(hw, PEX_UNC_ERR_STAT);
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pex_err = sky2_pci_read32(hw,
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hw->err_cap + PCI_ERR_UNCOR_STATUS);
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if (net_ratelimit())
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printk(KERN_ERR PFX "%s: pci express error (0x%x)\n",
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@ -2109,15 +2110,20 @@ static void sky2_hw_intr(struct sky2_hw *hw)
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/* clear the interrupt */
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sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
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sky2_pci_write32(hw, PEX_UNC_ERR_STAT,
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0xffffffffUL);
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sky2_pci_write32(hw,
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hw->err_cap + PCI_ERR_UNCOR_STATUS,
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0xffffffffUL);
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sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
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if (pex_err & PEX_FATAL_ERRORS) {
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/* In case of fatal error mask off to keep from getting stuck */
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if (pex_err & (PCI_ERR_UNC_POISON_TLP | PCI_ERR_UNC_FCP
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| PCI_ERR_UNC_DLP)) {
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u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
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hwmsk &= ~Y2_IS_PCI_EXP;
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sky2_write32(hw, B0_HWE_IMSK, hwmsk);
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}
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}
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if (status & Y2_HWE_L1_MASK)
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@ -2298,6 +2304,7 @@ static int sky2_reset(struct sky2_hw *hw)
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u16 status;
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u8 t8;
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int i;
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u32 msk;
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sky2_write8(hw, B0_CTST, CS_RST_CLR);
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@ -2338,9 +2345,13 @@ static int sky2_reset(struct sky2_hw *hw)
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sky2_write8(hw, B0_CTST, CS_MRST_CLR);
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/* clear any PEX errors */
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if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
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sky2_pci_write32(hw, PEX_UNC_ERR_STAT, 0xffffffffUL);
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if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP)) {
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hw->err_cap = pci_find_ext_capability(hw->pdev, PCI_EXT_CAP_ID_ERR);
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if (hw->err_cap)
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sky2_pci_write32(hw,
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hw->err_cap + PCI_ERR_UNCOR_STATUS,
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0xffffffffUL);
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}
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hw->pmd_type = sky2_read8(hw, B2_PMD_TYP);
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hw->ports = 1;
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@ -2397,7 +2408,10 @@ static int sky2_reset(struct sky2_hw *hw)
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sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
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}
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sky2_write32(hw, B0_HWE_IMSK, Y2_HWE_ALL_MASK);
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msk = Y2_HWE_ALL_MASK;
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if (!hw->err_cap)
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msk &= ~Y2_IS_PCI_EXP;
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sky2_write32(hw, B0_HWE_IMSK, msk);
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for (i = 0; i < hw->ports; i++)
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sky2_gmac_reset(hw, i);
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@ -4,24 +4,15 @@
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#ifndef _SKY2_H
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#define _SKY2_H
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/* PCI config registers */
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/* PCI device specific config registers */
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enum {
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PCI_DEV_REG1 = 0x40,
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PCI_DEV_REG2 = 0x44,
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PCI_DEV_STATUS = 0x7c,
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PCI_DEV_REG3 = 0x80,
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PCI_DEV_REG4 = 0x84,
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PCI_DEV_REG5 = 0x88,
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};
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enum {
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PEX_DEV_CAP = 0xe4,
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PEX_DEV_CTRL = 0xe8,
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PEX_DEV_STA = 0xea,
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PEX_LNK_STAT = 0xf2,
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PEX_UNC_ERR_STAT= 0x104,
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};
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/* Yukon-2 */
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enum pci_dev_reg_1 {
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PCI_Y2_PIG_ENA = 1<<31, /* Enable Plug-in-Go (YUKON-2) */
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@ -70,39 +61,6 @@ enum pci_dev_reg_4 {
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PCI_STATUS_REC_MASTER_ABORT | \
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PCI_STATUS_REC_TARGET_ABORT | \
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PCI_STATUS_PARITY)
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enum pex_dev_ctrl {
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PEX_DC_MAX_RRS_MSK = 7<<12, /* Bit 14..12: Max. Read Request Size */
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PEX_DC_EN_NO_SNOOP = 1<<11,/* Enable No Snoop */
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PEX_DC_EN_AUX_POW = 1<<10,/* Enable AUX Power */
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PEX_DC_EN_PHANTOM = 1<<9, /* Enable Phantom Functions */
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PEX_DC_EN_EXT_TAG = 1<<8, /* Enable Extended Tag Field */
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PEX_DC_MAX_PLS_MSK = 7<<5, /* Bit 7.. 5: Max. Payload Size Mask */
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PEX_DC_EN_REL_ORD = 1<<4, /* Enable Relaxed Ordering */
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PEX_DC_EN_UNS_RQ_RP = 1<<3, /* Enable Unsupported Request Reporting */
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PEX_DC_EN_FAT_ER_RP = 1<<2, /* Enable Fatal Error Reporting */
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PEX_DC_EN_NFA_ER_RP = 1<<1, /* Enable Non-Fatal Error Reporting */
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PEX_DC_EN_COR_ER_RP = 1<<0, /* Enable Correctable Error Reporting */
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};
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#define PEX_DC_MAX_RD_RQ_SIZE(x) (((x)<<12) & PEX_DC_MAX_RRS_MSK)
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/* PEX_UNC_ERR_STAT PEX Uncorrectable Errors Status Register (Yukon-2) */
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enum pex_err {
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PEX_UNSUP_REQ = 1<<20, /* Unsupported Request Error */
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PEX_MALFOR_TLP = 1<<18, /* Malformed TLP */
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PEX_UNEXP_COMP = 1<<16, /* Unexpected Completion */
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PEX_COMP_TO = 1<<14, /* Completion Timeout */
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PEX_FLOW_CTRL_P = 1<<13, /* Flow Control Protocol Error */
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PEX_POIS_TLP = 1<<12, /* Poisoned TLP */
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PEX_DATA_LINK_P = 1<<4, /* Data Link Protocol Error */
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PEX_FATAL_ERRORS= (PEX_MALFOR_TLP | PEX_FLOW_CTRL_P | PEX_DATA_LINK_P),
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};
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enum csr_regs {
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B0_RAP = 0x0000,
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B0_CTST = 0x0004,
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@ -1873,6 +1831,7 @@ struct sky2_hw {
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struct net_device *dev[2];
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int pm_cap;
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int err_cap;
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u8 chip_id;
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u8 chip_rev;
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u8 pmd_type;
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