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ASoC: Intel: Skylake: add code loader DMA operations
This patch starts adding code loader DMA handling internal operations for setting up bdle, controller, spb, cleanup routines and buffer filling Signed-off-by: Subhransu S. Prusty <subhransu.s.prusty@intel.com> Signed-off-by: Jeeja KP <jeeja.kp@intel.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com> Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Vinod Koul
Mark Brown
parent
e30903877f
commit
914426c865
194
sound/soc/intel/skylake/skl-sst-cldma.c
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194
sound/soc/intel/skylake/skl-sst-cldma.c
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@ -0,0 +1,194 @@
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/*
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* skl-sst-cldma.c - Code Loader DMA handler
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*
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* Copyright (C) 2015, Intel Corporation.
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* Author: Subhransu S. Prusty <subhransu.s.prusty@intel.com>
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* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as version 2, as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*/
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#include <linux/device.h>
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#include <linux/mm.h>
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#include <linux/kthread.h>
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#include "../common/sst-dsp.h"
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#include "../common/sst-dsp-priv.h"
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static void skl_cldma_int_enable(struct sst_dsp *ctx)
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{
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sst_dsp_shim_update_bits_unlocked(ctx, SKL_ADSP_REG_ADSPIC,
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SKL_ADSPIC_CL_DMA, SKL_ADSPIC_CL_DMA);
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}
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void skl_cldma_int_disable(struct sst_dsp *ctx)
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{
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sst_dsp_shim_update_bits_unlocked(ctx,
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SKL_ADSP_REG_ADSPIC, SKL_ADSPIC_CL_DMA, 0);
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}
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/* Code loader helper APIs */
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static void skl_cldma_setup_bdle(struct sst_dsp *ctx,
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struct snd_dma_buffer *dmab_data,
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u32 **bdlp, int size, int with_ioc)
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{
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u32 *bdl = *bdlp;
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ctx->cl_dev.frags = 0;
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while (size > 0) {
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phys_addr_t addr = virt_to_phys(dmab_data->area +
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(ctx->cl_dev.frags * ctx->cl_dev.bufsize));
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bdl[0] = cpu_to_le32(lower_32_bits(addr));
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bdl[1] = cpu_to_le32(upper_32_bits(addr));
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bdl[2] = cpu_to_le32(ctx->cl_dev.bufsize);
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size -= ctx->cl_dev.bufsize;
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bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01);
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bdl += 4;
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ctx->cl_dev.frags++;
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}
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}
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/*
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* Setup controller
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* Configure the registers to update the dma buffer address and
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* enable interrupts.
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* Note: Using the channel 1 for transfer
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*/
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static void skl_cldma_setup_controller(struct sst_dsp *ctx,
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struct snd_dma_buffer *dmab_bdl, unsigned int max_size,
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u32 count)
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{
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sst_dsp_shim_write(ctx, SKL_ADSP_REG_CL_SD_BDLPL,
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CL_SD_BDLPLBA(dmab_bdl->addr));
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sst_dsp_shim_write(ctx, SKL_ADSP_REG_CL_SD_BDLPU,
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CL_SD_BDLPUBA(dmab_bdl->addr));
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sst_dsp_shim_write(ctx, SKL_ADSP_REG_CL_SD_CBL, max_size);
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sst_dsp_shim_write(ctx, SKL_ADSP_REG_CL_SD_LVI, count - 1);
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sst_dsp_shim_update_bits(ctx, SKL_ADSP_REG_CL_SD_CTL,
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CL_SD_CTL_IOCE_MASK, CL_SD_CTL_IOCE(1));
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sst_dsp_shim_update_bits(ctx, SKL_ADSP_REG_CL_SD_CTL,
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CL_SD_CTL_FEIE_MASK, CL_SD_CTL_FEIE(1));
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sst_dsp_shim_update_bits(ctx, SKL_ADSP_REG_CL_SD_CTL,
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CL_SD_CTL_DEIE_MASK, CL_SD_CTL_DEIE(1));
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sst_dsp_shim_update_bits(ctx, SKL_ADSP_REG_CL_SD_CTL,
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CL_SD_CTL_STRM_MASK, CL_SD_CTL_STRM(FW_CL_STREAM_NUMBER));
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}
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static void skl_cldma_setup_spb(struct sst_dsp *ctx,
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unsigned int size, bool enable)
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{
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if (enable)
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sst_dsp_shim_update_bits_unlocked(ctx,
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SKL_ADSP_REG_CL_SPBFIFO_SPBFCCTL,
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CL_SPBFIFO_SPBFCCTL_SPIBE_MASK,
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CL_SPBFIFO_SPBFCCTL_SPIBE(1));
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sst_dsp_shim_write_unlocked(ctx, SKL_ADSP_REG_CL_SPBFIFO_SPIB, size);
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}
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static void skl_cldma_cleanup_spb(struct sst_dsp *ctx)
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{
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sst_dsp_shim_update_bits_unlocked(ctx,
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SKL_ADSP_REG_CL_SPBFIFO_SPBFCCTL,
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CL_SPBFIFO_SPBFCCTL_SPIBE_MASK,
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CL_SPBFIFO_SPBFCCTL_SPIBE(0));
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sst_dsp_shim_write_unlocked(ctx, SKL_ADSP_REG_CL_SPBFIFO_SPIB, 0);
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}
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static void skl_cldma_trigger(struct sst_dsp *ctx, bool enable)
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{
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if (enable)
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sst_dsp_shim_update_bits_unlocked(ctx,
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SKL_ADSP_REG_CL_SD_CTL,
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CL_SD_CTL_RUN_MASK, CL_SD_CTL_RUN(1));
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else
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sst_dsp_shim_update_bits_unlocked(ctx,
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SKL_ADSP_REG_CL_SD_CTL,
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CL_SD_CTL_RUN_MASK, CL_SD_CTL_RUN(0));
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}
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static void skl_cldma_cleanup(struct sst_dsp *ctx)
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{
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skl_cldma_cleanup_spb(ctx);
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sst_dsp_shim_update_bits(ctx, SKL_ADSP_REG_CL_SD_CTL,
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CL_SD_CTL_IOCE_MASK, CL_SD_CTL_IOCE(0));
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sst_dsp_shim_update_bits(ctx, SKL_ADSP_REG_CL_SD_CTL,
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CL_SD_CTL_FEIE_MASK, CL_SD_CTL_FEIE(0));
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sst_dsp_shim_update_bits(ctx, SKL_ADSP_REG_CL_SD_CTL,
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CL_SD_CTL_DEIE_MASK, CL_SD_CTL_DEIE(0));
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sst_dsp_shim_update_bits(ctx, SKL_ADSP_REG_CL_SD_CTL,
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CL_SD_CTL_STRM_MASK, CL_SD_CTL_STRM(0));
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sst_dsp_shim_write(ctx, SKL_ADSP_REG_CL_SD_BDLPL, CL_SD_BDLPLBA(0));
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sst_dsp_shim_write(ctx, SKL_ADSP_REG_CL_SD_BDLPU, 0);
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sst_dsp_shim_write(ctx, SKL_ADSP_REG_CL_SD_CBL, 0);
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sst_dsp_shim_write(ctx, SKL_ADSP_REG_CL_SD_LVI, 0);
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}
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static int skl_cldma_wait_interruptible(struct sst_dsp *ctx)
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{
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int ret = 0;
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if (!wait_event_timeout(ctx->cl_dev.wait_queue,
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ctx->cl_dev.wait_condition,
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msecs_to_jiffies(SKL_WAIT_TIMEOUT))) {
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dev_err(ctx->dev, "%s: Wait timeout\n", __func__);
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ret = -EIO;
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goto cleanup;
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}
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dev_dbg(ctx->dev, "%s: Event wake\n", __func__);
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if (ctx->cl_dev.wake_status != SKL_CL_DMA_BUF_COMPLETE) {
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dev_err(ctx->dev, "%s: DMA Error\n", __func__);
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ret = -EIO;
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}
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cleanup:
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ctx->cl_dev.wake_status = SKL_CL_DMA_STATUS_NONE;
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return ret;
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}
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static void skl_cldma_stop(struct sst_dsp *ctx)
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{
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ctx->cl_dev.ops.cl_trigger(ctx, false);
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}
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static void skl_cldma_fill_buffer(struct sst_dsp *ctx, unsigned int size,
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const void *curr_pos, bool intr_enable, bool trigger)
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{
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dev_dbg(ctx->dev, "Size: %x, intr_enable: %d\n", size, intr_enable);
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dev_dbg(ctx->dev, "buf_pos_index:%d, trigger:%d\n",
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ctx->cl_dev.dma_buffer_offset, trigger);
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dev_dbg(ctx->dev, "spib position: %d\n", ctx->cl_dev.curr_spib_pos);
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memcpy(ctx->cl_dev.dmab_data.area + ctx->cl_dev.dma_buffer_offset,
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curr_pos, size);
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if (ctx->cl_dev.curr_spib_pos == ctx->cl_dev.bufsize)
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ctx->cl_dev.dma_buffer_offset = 0;
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else
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ctx->cl_dev.dma_buffer_offset = ctx->cl_dev.curr_spib_pos;
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ctx->cl_dev.wait_condition = false;
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if (intr_enable)
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skl_cldma_int_enable(ctx);
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ctx->cl_dev.ops.cl_setup_spb(ctx, ctx->cl_dev.curr_spib_pos, trigger);
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if (trigger)
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ctx->cl_dev.ops.cl_trigger(ctx, true);
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}
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@ -188,4 +188,64 @@
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#define CL_SPBFIFO_SPBFCCTL_SPIBE(x) \
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((x << CL_SPBFIFO_SPBFCCTL_SPIBE_SHIFT) & CL_SPBFIFO_SPBFCCTL_SPIBE_MASK)
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/* SST IPC SKL defines */
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#define SKL_WAIT_TIMEOUT 500 /* 500 msec */
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#define SKL_MAX_BUFFER_SIZE (32 * PAGE_SIZE)
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enum skl_cl_dma_wake_states {
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SKL_CL_DMA_STATUS_NONE = 0,
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SKL_CL_DMA_BUF_COMPLETE,
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SKL_CL_DMA_ERR, /* TODO: Expand the error states */
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};
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struct sst_dsp;
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struct skl_cl_dev_ops {
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void (*cl_setup_bdle)(struct sst_dsp *ctx,
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struct snd_dma_buffer *dmab_data,
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u32 **bdlp, int size, int with_ioc);
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void (*cl_setup_controller)(struct sst_dsp *ctx,
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struct snd_dma_buffer *dmab_bdl,
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unsigned int max_size, u32 page_count);
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void (*cl_setup_spb)(struct sst_dsp *ctx,
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unsigned int size, bool enable);
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void (*cl_cleanup_spb)(struct sst_dsp *ctx);
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void (*cl_trigger)(struct sst_dsp *ctx, bool enable);
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void (*cl_cleanup_controller)(struct sst_dsp *ctx);
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int (*cl_copy_to_dmabuf)(struct sst_dsp *ctx,
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const void *bin, u32 size);
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void (*cl_stop_dma)(struct sst_dsp *ctx);
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};
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/**
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* skl_cl_dev - holds information for code loader dma transfer
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*
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* @dmab_data: buffer pointer
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* @dmab_bdl: buffer descriptor list
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* @bufsize: ring buffer size
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* @frags: Last valid buffer descriptor index in the BDL
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* @curr_spib_pos: Current position in ring buffer
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* @dma_buffer_offset: dma buffer offset
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* @ops: operations supported on CL dma
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* @wait_queue: wait queue to wake for wake event
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* @wake_status: DMA wake status
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* @wait_condition: condition to wait on wait queue
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* @cl_dma_lock: for synchronized access to cldma
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*/
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struct skl_cl_dev {
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struct snd_dma_buffer dmab_data;
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struct snd_dma_buffer dmab_bdl;
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unsigned int bufsize;
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unsigned int frags;
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unsigned int curr_spib_pos;
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unsigned int dma_buffer_offset;
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struct skl_cl_dev_ops ops;
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wait_queue_head_t wait_queue;
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int wake_status;
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bool wait_condition;
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};
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#endif /* SKL_SST_CLDMA_H_ */
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