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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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iommu/arm-smmu: Track context bank state
Echoing what we do for Stream Map Entries, maintain a software shadow state for context bank configuration. With this in place, we are mere moments away from blissfully easy suspend/resume support. Reviewed-by: Sricharan R <sricharan@codeaurora.org> Signed-off-by: Robin Murphy <robin.murphy@arm.com> [will: fix sparse warning by only clearing .cfg during domain destruction] Signed-off-by: Will Deacon <will.deacon@arm.com>
This commit is contained in:
Robin Murphy
Will Deacon
parent
7aa8619a66
commit
90df373cc6
@ -338,6 +338,13 @@ struct arm_smmu_smr {
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bool valid;
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};
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struct arm_smmu_cb {
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u64 ttbr[2];
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u32 tcr[2];
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u32 mair[2];
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struct arm_smmu_cfg *cfg;
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};
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struct arm_smmu_master_cfg {
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struct arm_smmu_device *smmu;
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s16 smendx[];
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@ -380,6 +387,7 @@ struct arm_smmu_device {
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u32 num_context_banks;
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u32 num_s2_context_banks;
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DECLARE_BITMAP(context_map, ARM_SMMU_MAX_CBS);
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struct arm_smmu_cb *cbs;
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atomic_t irptndx;
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u32 num_mapping_groups;
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@ -776,17 +784,74 @@ static irqreturn_t arm_smmu_global_fault(int irq, void *dev)
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static void arm_smmu_init_context_bank(struct arm_smmu_domain *smmu_domain,
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struct io_pgtable_cfg *pgtbl_cfg)
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{
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u32 reg, reg2;
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u64 reg64;
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bool stage1;
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struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
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struct arm_smmu_device *smmu = smmu_domain->smmu;
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struct arm_smmu_cb *cb = &smmu_domain->smmu->cbs[cfg->cbndx];
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bool stage1 = cfg->cbar != CBAR_TYPE_S2_TRANS;
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cb->cfg = cfg;
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/* TTBCR */
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if (stage1) {
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if (cfg->fmt == ARM_SMMU_CTX_FMT_AARCH32_S) {
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cb->tcr[0] = pgtbl_cfg->arm_v7s_cfg.tcr;
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} else {
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cb->tcr[0] = pgtbl_cfg->arm_lpae_s1_cfg.tcr;
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cb->tcr[1] = pgtbl_cfg->arm_lpae_s1_cfg.tcr >> 32;
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cb->tcr[1] |= TTBCR2_SEP_UPSTREAM;
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if (cfg->fmt == ARM_SMMU_CTX_FMT_AARCH64)
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cb->tcr[1] |= TTBCR2_AS;
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}
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} else {
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cb->tcr[0] = pgtbl_cfg->arm_lpae_s2_cfg.vtcr;
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}
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/* TTBRs */
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if (stage1) {
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if (cfg->fmt == ARM_SMMU_CTX_FMT_AARCH32_S) {
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cb->ttbr[0] = pgtbl_cfg->arm_v7s_cfg.ttbr[0];
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cb->ttbr[1] = pgtbl_cfg->arm_v7s_cfg.ttbr[1];
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} else {
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cb->ttbr[0] = pgtbl_cfg->arm_lpae_s1_cfg.ttbr[0];
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cb->ttbr[0] |= (u64)cfg->asid << TTBRn_ASID_SHIFT;
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cb->ttbr[1] = pgtbl_cfg->arm_lpae_s1_cfg.ttbr[1];
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cb->ttbr[1] |= (u64)cfg->asid << TTBRn_ASID_SHIFT;
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}
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} else {
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cb->ttbr[0] = pgtbl_cfg->arm_lpae_s2_cfg.vttbr;
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}
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/* MAIRs (stage-1 only) */
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if (stage1) {
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if (cfg->fmt == ARM_SMMU_CTX_FMT_AARCH32_S) {
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cb->mair[0] = pgtbl_cfg->arm_v7s_cfg.prrr;
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cb->mair[1] = pgtbl_cfg->arm_v7s_cfg.nmrr;
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} else {
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cb->mair[0] = pgtbl_cfg->arm_lpae_s1_cfg.mair[0];
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cb->mair[1] = pgtbl_cfg->arm_lpae_s1_cfg.mair[1];
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}
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}
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}
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static void arm_smmu_write_context_bank(struct arm_smmu_device *smmu, int idx)
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{
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u32 reg;
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bool stage1;
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struct arm_smmu_cb *cb = &smmu->cbs[idx];
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struct arm_smmu_cfg *cfg = cb->cfg;
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void __iomem *cb_base, *gr1_base;
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cb_base = ARM_SMMU_CB(smmu, idx);
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/* Unassigned context banks only need disabling */
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if (!cfg) {
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writel_relaxed(0, cb_base + ARM_SMMU_CB_SCTLR);
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return;
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}
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gr1_base = ARM_SMMU_GR1(smmu);
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stage1 = cfg->cbar != CBAR_TYPE_S2_TRANS;
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cb_base = ARM_SMMU_CB(smmu, cfg->cbndx);
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/* CBA2R */
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if (smmu->version > ARM_SMMU_V1) {
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if (cfg->fmt == ARM_SMMU_CTX_FMT_AARCH64)
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reg = CBA2R_RW64_64BIT;
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@ -796,7 +861,7 @@ static void arm_smmu_init_context_bank(struct arm_smmu_domain *smmu_domain,
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if (smmu->features & ARM_SMMU_FEAT_VMID16)
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reg |= cfg->vmid << CBA2R_VMID_SHIFT;
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writel_relaxed(reg, gr1_base + ARM_SMMU_GR1_CBA2R(cfg->cbndx));
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writel_relaxed(reg, gr1_base + ARM_SMMU_GR1_CBA2R(idx));
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}
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/* CBAR */
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@ -815,72 +880,41 @@ static void arm_smmu_init_context_bank(struct arm_smmu_domain *smmu_domain,
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/* 8-bit VMIDs live in CBAR */
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reg |= cfg->vmid << CBAR_VMID_SHIFT;
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}
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writel_relaxed(reg, gr1_base + ARM_SMMU_GR1_CBAR(cfg->cbndx));
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writel_relaxed(reg, gr1_base + ARM_SMMU_GR1_CBAR(idx));
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/*
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* TTBCR
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* We must write this before the TTBRs, since it determines the
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* access behaviour of some fields (in particular, ASID[15:8]).
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*/
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if (stage1) {
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if (cfg->fmt == ARM_SMMU_CTX_FMT_AARCH32_S) {
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reg = pgtbl_cfg->arm_v7s_cfg.tcr;
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reg2 = 0;
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} else {
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reg = pgtbl_cfg->arm_lpae_s1_cfg.tcr;
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reg2 = pgtbl_cfg->arm_lpae_s1_cfg.tcr >> 32;
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reg2 |= TTBCR2_SEP_UPSTREAM;
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if (cfg->fmt == ARM_SMMU_CTX_FMT_AARCH64)
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reg2 |= TTBCR2_AS;
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}
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if (smmu->version > ARM_SMMU_V1)
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writel_relaxed(reg2, cb_base + ARM_SMMU_CB_TTBCR2);
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} else {
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reg = pgtbl_cfg->arm_lpae_s2_cfg.vtcr;
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}
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writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBCR);
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if (stage1 && smmu->version > ARM_SMMU_V1)
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writel_relaxed(cb->tcr[1], cb_base + ARM_SMMU_CB_TTBCR2);
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writel_relaxed(cb->tcr[0], cb_base + ARM_SMMU_CB_TTBCR);
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/* TTBRs */
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if (stage1) {
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if (cfg->fmt == ARM_SMMU_CTX_FMT_AARCH32_S) {
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reg = pgtbl_cfg->arm_v7s_cfg.ttbr[0];
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writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBR0);
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reg = pgtbl_cfg->arm_v7s_cfg.ttbr[1];
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writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBR1);
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writel_relaxed(cfg->asid, cb_base + ARM_SMMU_CB_CONTEXTIDR);
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} else {
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reg64 = pgtbl_cfg->arm_lpae_s1_cfg.ttbr[0];
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reg64 |= (u64)cfg->asid << TTBRn_ASID_SHIFT;
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writeq_relaxed(reg64, cb_base + ARM_SMMU_CB_TTBR0);
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reg64 = pgtbl_cfg->arm_lpae_s1_cfg.ttbr[1];
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reg64 |= (u64)cfg->asid << TTBRn_ASID_SHIFT;
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writeq_relaxed(reg64, cb_base + ARM_SMMU_CB_TTBR1);
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}
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if (cfg->fmt == ARM_SMMU_CTX_FMT_AARCH32_S) {
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writel_relaxed(cfg->asid, cb_base + ARM_SMMU_CB_CONTEXTIDR);
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writel_relaxed(cb->ttbr[0], cb_base + ARM_SMMU_CB_TTBR0);
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writel_relaxed(cb->ttbr[1], cb_base + ARM_SMMU_CB_TTBR1);
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} else {
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reg64 = pgtbl_cfg->arm_lpae_s2_cfg.vttbr;
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writeq_relaxed(reg64, cb_base + ARM_SMMU_CB_TTBR0);
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writeq_relaxed(cb->ttbr[0], cb_base + ARM_SMMU_CB_TTBR0);
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if (stage1)
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writeq_relaxed(cb->ttbr[1], cb_base + ARM_SMMU_CB_TTBR1);
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}
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/* MAIRs (stage-1 only) */
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if (stage1) {
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if (cfg->fmt == ARM_SMMU_CTX_FMT_AARCH32_S) {
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reg = pgtbl_cfg->arm_v7s_cfg.prrr;
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reg2 = pgtbl_cfg->arm_v7s_cfg.nmrr;
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} else {
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reg = pgtbl_cfg->arm_lpae_s1_cfg.mair[0];
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reg2 = pgtbl_cfg->arm_lpae_s1_cfg.mair[1];
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}
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writel_relaxed(reg, cb_base + ARM_SMMU_CB_S1_MAIR0);
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writel_relaxed(reg2, cb_base + ARM_SMMU_CB_S1_MAIR1);
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writel_relaxed(cb->mair[0], cb_base + ARM_SMMU_CB_S1_MAIR0);
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writel_relaxed(cb->mair[1], cb_base + ARM_SMMU_CB_S1_MAIR1);
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}
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/* SCTLR */
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reg = SCTLR_CFIE | SCTLR_CFRE | SCTLR_AFE | SCTLR_TRE | SCTLR_M;
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if (stage1)
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reg |= SCTLR_S1_ASIDPNE;
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#ifdef __BIG_ENDIAN
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reg |= SCTLR_E;
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#endif
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if (IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
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reg |= SCTLR_E;
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writel_relaxed(reg, cb_base + ARM_SMMU_CB_SCTLR);
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}
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@ -1043,6 +1077,7 @@ static int arm_smmu_init_domain_context(struct iommu_domain *domain,
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/* Initialise the context bank with our page table cfg */
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arm_smmu_init_context_bank(smmu_domain, &pgtbl_cfg);
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arm_smmu_write_context_bank(smmu, cfg->cbndx);
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/*
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* Request context fault interrupt. Do this last to avoid the
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@ -1075,7 +1110,6 @@ static void arm_smmu_destroy_domain_context(struct iommu_domain *domain)
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struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain);
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struct arm_smmu_device *smmu = smmu_domain->smmu;
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struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
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void __iomem *cb_base;
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int irq;
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if (!smmu || domain->type == IOMMU_DOMAIN_IDENTITY)
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@ -1085,8 +1119,8 @@ static void arm_smmu_destroy_domain_context(struct iommu_domain *domain)
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* Disable the context bank and free the page tables before freeing
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* it.
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*/
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cb_base = ARM_SMMU_CB(smmu, cfg->cbndx);
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writel_relaxed(0, cb_base + ARM_SMMU_CB_SCTLR);
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smmu->cbs[cfg->cbndx].cfg = NULL;
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arm_smmu_write_context_bank(smmu, cfg->cbndx);
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if (cfg->irptndx != INVALID_IRPTNDX) {
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irq = smmu->irqs[smmu->num_global_irqs + cfg->irptndx];
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@ -1729,7 +1763,6 @@ static struct iommu_ops arm_smmu_ops = {
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static void arm_smmu_device_reset(struct arm_smmu_device *smmu)
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{
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void __iomem *gr0_base = ARM_SMMU_GR0(smmu);
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void __iomem *cb_base;
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int i;
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u32 reg, major;
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@ -1765,8 +1798,9 @@ static void arm_smmu_device_reset(struct arm_smmu_device *smmu)
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/* Make sure all context banks are disabled and clear CB_FSR */
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for (i = 0; i < smmu->num_context_banks; ++i) {
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cb_base = ARM_SMMU_CB(smmu, i);
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writel_relaxed(0, cb_base + ARM_SMMU_CB_SCTLR);
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void __iomem *cb_base = ARM_SMMU_CB(smmu, i);
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arm_smmu_write_context_bank(smmu, i);
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writel_relaxed(FSR_FAULT, cb_base + ARM_SMMU_CB_FSR);
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/*
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* Disable MMU-500's not-particularly-beneficial next-page
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@ -1972,6 +2006,10 @@ static int arm_smmu_device_cfg_probe(struct arm_smmu_device *smmu)
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smmu->cavium_id_base -= smmu->num_context_banks;
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dev_notice(smmu->dev, "\tenabling workaround for Cavium erratum 27704\n");
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}
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smmu->cbs = devm_kcalloc(smmu->dev, smmu->num_context_banks,
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sizeof(*smmu->cbs), GFP_KERNEL);
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if (!smmu->cbs)
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return -ENOMEM;
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/* ID2 */
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id = readl_relaxed(gr0_base + ARM_SMMU_GR0_ID2);
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