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net: mdiobus: add clause 45 mdiobus accessors

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There is a recurring pattern throughout some of the PHY code converting
a devad and regnum to our packed clause 45 representation. Rather than
having this scattered around the code, let's put a common translation
function in mdio.h, and provide some register accessors.

Convert the phylib core, phylink, bcm87xx and cortina to use these.

Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Russell King 2020-05-26 16:29:36 +01:00 committed by David S. Miller
parent 8928e19ad8
commit 90ce665c6a
8 changed files with 52 additions and 36 deletions
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2
drivers/net/phy/bcm87xx.c
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@ -55,7 +55,7 @@ static int bcm87xx_of_reg_init(struct phy_device *phydev)
u16 mask = be32_to_cpup(paddr++); u16 mask = be32_to_cpup(paddr++);
u16 val_bits = be32_to_cpup(paddr++); u16 val_bits = be32_to_cpup(paddr++);
int val; int val;
u32 regnum = MII_ADDR_C45 | (devid << 16) | reg; u32 regnum = mdiobus_c45_addr(devid, reg);
val = 0; val = 0;
if (mask) { if (mask) {
val = phy_read(phydev, regnum); val = phy_read(phydev, regnum);

3
drivers/net/phy/cortina.c
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@ -17,8 +17,7 @@
static int cortina_read_reg(struct phy_device *phydev, u16 regnum) static int cortina_read_reg(struct phy_device *phydev, u16 regnum)
{ {
return mdiobus_read(phydev->mdio.bus, phydev->mdio.addr, return mdiobus_c45_read(phydev->mdio.bus, phydev->mdio.addr, 0, regnum);
MII_ADDR_C45 | regnum);
} }
static int cortina_read_status(struct phy_device *phydev) static int cortina_read_status(struct phy_device *phydev)

11
drivers/net/phy/phy-core.c
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@ -428,9 +428,8 @@ int __phy_read_mmd(struct phy_device *phydev, int devad, u32 regnum)
if (phydev->drv && phydev->drv->read_mmd) { if (phydev->drv && phydev->drv->read_mmd) {
val = phydev->drv->read_mmd(phydev, devad, regnum); val = phydev->drv->read_mmd(phydev, devad, regnum);
} else if (phydev->is_c45) { } else if (phydev->is_c45) {
u32 addr = MII_ADDR_C45 | (devad << 16) | (regnum & 0xffff); val = __mdiobus_c45_read(phydev->mdio.bus, phydev->mdio.addr,
devad, regnum);
val = __mdiobus_read(phydev->mdio.bus, phydev->mdio.addr, addr);
} else { } else {
struct mii_bus *bus = phydev->mdio.bus; struct mii_bus *bus = phydev->mdio.bus;
int phy_addr = phydev->mdio.addr; int phy_addr = phydev->mdio.addr;
@ -485,10 +484,8 @@ int __phy_write_mmd(struct phy_device *phydev, int devad, u32 regnum, u16 val)
if (phydev->drv && phydev->drv->write_mmd) { if (phydev->drv && phydev->drv->write_mmd) {
ret = phydev->drv->write_mmd(phydev, devad, regnum, val); ret = phydev->drv->write_mmd(phydev, devad, regnum, val);
} else if (phydev->is_c45) { } else if (phydev->is_c45) {
u32 addr = MII_ADDR_C45 | (devad << 16) | (regnum & 0xffff); ret = __mdiobus_c45_write(phydev->mdio.bus, phydev->mdio.addr,
devad, regnum, val);
ret = __mdiobus_write(phydev->mdio.bus, phydev->mdio.addr,
addr, val);
} else { } else {
struct mii_bus *bus = phydev->mdio.bus; struct mii_bus *bus = phydev->mdio.bus;
int phy_addr = phydev->mdio.addr; int phy_addr = phydev->mdio.addr;

4
drivers/net/phy/phy.c
View File

@ -361,7 +361,7 @@ int phy_mii_ioctl(struct phy_device *phydev, struct ifreq *ifr, int cmd)
if (mdio_phy_id_is_c45(mii_data->phy_id)) { if (mdio_phy_id_is_c45(mii_data->phy_id)) {
prtad = mdio_phy_id_prtad(mii_data->phy_id); prtad = mdio_phy_id_prtad(mii_data->phy_id);
devad = mdio_phy_id_devad(mii_data->phy_id); devad = mdio_phy_id_devad(mii_data->phy_id);
devad = MII_ADDR_C45 | devad << 16 | mii_data->reg_num; devad = mdiobus_c45_addr(devad, mii_data->reg_num);
} else { } else {
prtad = mii_data->phy_id; prtad = mii_data->phy_id;
devad = mii_data->reg_num; devad = mii_data->reg_num;
@ -374,7 +374,7 @@ int phy_mii_ioctl(struct phy_device *phydev, struct ifreq *ifr, int cmd)
if (mdio_phy_id_is_c45(mii_data->phy_id)) { if (mdio_phy_id_is_c45(mii_data->phy_id)) {
prtad = mdio_phy_id_prtad(mii_data->phy_id); prtad = mdio_phy_id_prtad(mii_data->phy_id);
devad = mdio_phy_id_devad(mii_data->phy_id); devad = mdio_phy_id_devad(mii_data->phy_id);
devad = MII_ADDR_C45 | devad << 16 | mii_data->reg_num; devad = mdiobus_c45_addr(devad, mii_data->reg_num);
} else { } else {
prtad = mii_data->phy_id; prtad = mii_data->phy_id;
devad = mii_data->reg_num; devad = mii_data->reg_num;

20
drivers/net/phy/phy_device.c
View File

@ -675,16 +675,14 @@ EXPORT_SYMBOL(phy_device_create);
static int get_phy_c45_devs_in_pkg(struct mii_bus *bus, int addr, int dev_addr, static int get_phy_c45_devs_in_pkg(struct mii_bus *bus, int addr, int dev_addr,
u32 *devices_in_package) u32 *devices_in_package)
{ {
int phy_reg, reg_addr; int phy_reg;
reg_addr = MII_ADDR_C45 | dev_addr << 16 | MDIO_DEVS2; phy_reg = mdiobus_c45_read(bus, addr, dev_addr, MDIO_DEVS2);
phy_reg = mdiobus_read(bus, addr, reg_addr);
if (phy_reg < 0) if (phy_reg < 0)
return -EIO; return -EIO;
*devices_in_package = phy_reg << 16; *devices_in_package = phy_reg << 16;
reg_addr = MII_ADDR_C45 | dev_addr << 16 | MDIO_DEVS1; phy_reg = mdiobus_c45_read(bus, addr, dev_addr, MDIO_DEVS1);
phy_reg = mdiobus_read(bus, addr, reg_addr);
if (phy_reg < 0) if (phy_reg < 0)
return -EIO; return -EIO;
*devices_in_package |= phy_reg; *devices_in_package |= phy_reg;
@ -709,11 +707,11 @@ static int get_phy_c45_devs_in_pkg(struct mii_bus *bus, int addr, int dev_addr,
* *
*/ */
static int get_phy_c45_ids(struct mii_bus *bus, int addr, u32 *phy_id, static int get_phy_c45_ids(struct mii_bus *bus, int addr, u32 *phy_id,
struct phy_c45_device_ids *c45_ids) { struct phy_c45_device_ids *c45_ids)
int phy_reg; {
int i, reg_addr;
const int num_ids = ARRAY_SIZE(c45_ids->device_ids); const int num_ids = ARRAY_SIZE(c45_ids->device_ids);
u32 *devs = &c45_ids->devices_in_package; u32 *devs = &c45_ids->devices_in_package;
int i, phy_reg;
/* Find first non-zero Devices In package. Device zero is reserved /* Find first non-zero Devices In package. Device zero is reserved
* for 802.3 c45 complied PHYs, so don't probe it at first. * for 802.3 c45 complied PHYs, so don't probe it at first.
@ -747,14 +745,12 @@ static int get_phy_c45_ids(struct mii_bus *bus, int addr, u32 *phy_id,
if (!(c45_ids->devices_in_package & (1 << i))) if (!(c45_ids->devices_in_package & (1 << i)))
continue; continue;
reg_addr = MII_ADDR_C45 | i << 16 | MII_PHYSID1; phy_reg = mdiobus_c45_read(bus, addr, i, MII_PHYSID1);
phy_reg = mdiobus_read(bus, addr, reg_addr);
if (phy_reg < 0) if (phy_reg < 0)
return -EIO; return -EIO;
c45_ids->device_ids[i] = phy_reg << 16; c45_ids->device_ids[i] = phy_reg << 16;
reg_addr = MII_ADDR_C45 | i << 16 | MII_PHYSID2; phy_reg = mdiobus_c45_read(bus, addr, i, MII_PHYSID2);
phy_reg = mdiobus_read(bus, addr, reg_addr);
if (phy_reg < 0) if (phy_reg < 0)
return -EIO; return -EIO;
c45_ids->device_ids[i] |= phy_reg; c45_ids->device_ids[i] |= phy_reg;

11
drivers/net/phy/phylink.c
View File

@ -1631,7 +1631,7 @@ static int phylink_phy_read(struct phylink *pl, unsigned int phy_id,
if (mdio_phy_id_is_c45(phy_id)) { if (mdio_phy_id_is_c45(phy_id)) {
prtad = mdio_phy_id_prtad(phy_id); prtad = mdio_phy_id_prtad(phy_id);
devad = mdio_phy_id_devad(phy_id); devad = mdio_phy_id_devad(phy_id);
devad = MII_ADDR_C45 | devad << 16 | reg; devad = mdiobus_c45_addr(devad, reg);
} else if (phydev->is_c45) { } else if (phydev->is_c45) {
switch (reg) { switch (reg) {
case MII_BMCR: case MII_BMCR:
@ -1654,7 +1654,7 @@ static int phylink_phy_read(struct phylink *pl, unsigned int phy_id,
return -EINVAL; return -EINVAL;
} }
prtad = phy_id; prtad = phy_id;
devad = MII_ADDR_C45 | devad << 16 | reg; devad = mdiobus_c45_addr(devad, reg);
} else { } else {
prtad = phy_id; prtad = phy_id;
devad = reg; devad = reg;
@ -1671,7 +1671,7 @@ static int phylink_phy_write(struct phylink *pl, unsigned int phy_id,
if (mdio_phy_id_is_c45(phy_id)) { if (mdio_phy_id_is_c45(phy_id)) {
prtad = mdio_phy_id_prtad(phy_id); prtad = mdio_phy_id_prtad(phy_id);
devad = mdio_phy_id_devad(phy_id); devad = mdio_phy_id_devad(phy_id);
devad = MII_ADDR_C45 | devad << 16 | reg; devad = mdiobus_c45_addr(devad, reg);
} else if (phydev->is_c45) { } else if (phydev->is_c45) {
switch (reg) { switch (reg) {
case MII_BMCR: case MII_BMCR:
@ -1694,7 +1694,7 @@ static int phylink_phy_write(struct phylink *pl, unsigned int phy_id,
return -EINVAL; return -EINVAL;
} }
prtad = phy_id; prtad = phy_id;
devad = MII_ADDR_C45 | devad << 16 | reg; devad = mdiobus_c45_addr(devad, reg);
} else { } else {
prtad = phy_id; prtad = phy_id;
devad = reg; devad = reg;
@ -2292,7 +2292,6 @@ void phylink_mii_c22_pcs_an_restart(struct mdio_device *pcs)
} }
EXPORT_SYMBOL_GPL(phylink_mii_c22_pcs_an_restart); EXPORT_SYMBOL_GPL(phylink_mii_c22_pcs_an_restart);
#define C45_ADDR(d,a) (MII_ADDR_C45 | (d) << 16 | (a))
void phylink_mii_c45_pcs_get_state(struct mdio_device *pcs, void phylink_mii_c45_pcs_get_state(struct mdio_device *pcs,
struct phylink_link_state *state) struct phylink_link_state *state)
{ {
@ -2300,7 +2299,7 @@ void phylink_mii_c45_pcs_get_state(struct mdio_device *pcs,
int addr = pcs->addr; int addr = pcs->addr;
int stat; int stat;
stat = mdiobus_read(bus, addr, C45_ADDR(MDIO_MMD_PCS, MDIO_STAT1)); stat = mdiobus_c45_read(bus, addr, MDIO_MMD_PCS, MDIO_STAT1);
if (stat < 0) { if (stat < 0) {
state->link = false; state->link = false;
return; return;

31
include/linux/mdio.h
View File

@ -9,6 +9,13 @@
#include <uapi/linux/mdio.h> #include <uapi/linux/mdio.h>
#include <linux/mod_devicetable.h> #include <linux/mod_devicetable.h>
/* Or MII_ADDR_C45 into regnum for read/write on mii_bus to enable the 21 bit
* IEEE 802.3ae clause 45 addressing mode used by 10GIGE phy chips.
*/
#define MII_ADDR_C45 (1<<30)
#define MII_DEVADDR_C45_SHIFT 16
#define MII_REGADDR_C45_MASK GENMASK(15, 0)
struct gpio_desc; struct gpio_desc;
struct mii_bus; struct mii_bus;
@ -326,6 +333,30 @@ int mdiobus_write_nested(struct mii_bus *bus, int addr, u32 regnum, u16 val);
int mdiobus_modify(struct mii_bus *bus, int addr, u32 regnum, u16 mask, int mdiobus_modify(struct mii_bus *bus, int addr, u32 regnum, u16 mask,
u16 set); u16 set);
static inline u32 mdiobus_c45_addr(int devad, u16 regnum)
{
return MII_ADDR_C45 | devad << MII_DEVADDR_C45_SHIFT | regnum;
}
static inline int __mdiobus_c45_read(struct mii_bus *bus, int prtad, int devad,
u16 regnum)
{
return __mdiobus_read(bus, prtad, mdiobus_c45_addr(devad, regnum));
}
static inline int __mdiobus_c45_write(struct mii_bus *bus, int prtad, int devad,
u16 regnum, u16 val)
{
return __mdiobus_write(bus, prtad, mdiobus_c45_addr(devad, regnum),
val);
}
static inline int mdiobus_c45_read(struct mii_bus *bus, int prtad, int devad,
u16 regnum)
{
return mdiobus_read(bus, prtad, mdiobus_c45_addr(devad, regnum));
}
int mdiobus_register_device(struct mdio_device *mdiodev); int mdiobus_register_device(struct mdio_device *mdiodev);
int mdiobus_unregister_device(struct mdio_device *mdiodev); int mdiobus_unregister_device(struct mdio_device *mdiodev);
bool mdiobus_is_registered_device(struct mii_bus *bus, int addr); bool mdiobus_is_registered_device(struct mii_bus *bus, int addr);

6
include/linux/phy.h
View File

@ -209,12 +209,6 @@ static inline const char *phy_modes(phy_interface_t interface)
#define MII_BUS_ID_SIZE 61 #define MII_BUS_ID_SIZE 61
/* Or MII_ADDR_C45 into regnum for read/write on mii_bus to enable the 21 bit
IEEE 802.3ae clause 45 addressing mode used by 10GIGE phy chips. */
#define MII_ADDR_C45 (1<<30)
#define MII_DEVADDR_C45_SHIFT 16
#define MII_REGADDR_C45_MASK GENMASK(15, 0)
struct device; struct device;
struct phylink; struct phylink;
struct sfp_bus; struct sfp_bus;