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phy: qcom-qmp: Add QMP V4 USB3 PHY support for sm8250
Add both the DP and UNI PHY for primary/secondary usb controllers. The tables are very similar to sm8150 (serdes_tbl is identical), but there are some differences. Signed-off-by: Jonathan Marek <jonathan@marek.ca> Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20200524021416.17049-4-jonathan@marek.ca Signed-off-by: Vinod Koul <vkoul@kernel.org>
This commit is contained in:
Jonathan Marek
Vinod Koul
parent
7b675ba1d2
commit
90b65347cf
@ -1607,6 +1607,142 @@ static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_pcs_tbl[] = {
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QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
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};
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static const struct qmp_phy_init_tbl sm8250_usb3_tx_tbl[] = {
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QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_TX, 0x60),
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QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_RX, 0x60),
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QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
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QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x02),
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QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
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QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
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QMP_PHY_INIT_CFG_LANE(QSERDES_V4_TX_PI_QEC_CTRL, 0x40, 1),
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QMP_PHY_INIT_CFG_LANE(QSERDES_V4_TX_PI_QEC_CTRL, 0x54, 2),
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};
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static const struct qmp_phy_init_tbl sm8250_usb3_rx_tbl[] = {
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x06),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
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QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_LOW, 0xff, 1),
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QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f, 2),
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QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f, 1),
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QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff, 2),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x7f),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x97),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_VTH_CODE, 0x10),
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};
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static const struct qmp_phy_init_tbl sm8250_usb3_pcs_tbl[] = {
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QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
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QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
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QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
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QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
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QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
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QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xa9),
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QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
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QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
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QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
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QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
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QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
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QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
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QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
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QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
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};
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static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_tx_tbl[] = {
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QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
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QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
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QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_2, 0x82),
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QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x40),
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QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
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QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x02),
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};
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static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_rx_tbl[] = {
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0xb8),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xff),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xbf),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0a),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x06),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
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};
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static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_pcs_tbl[] = {
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QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
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QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
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QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
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QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
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QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
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QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
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QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xa9),
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QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
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QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2, 0x07),
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QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
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QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
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QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
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QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
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QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
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QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
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QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
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};
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/* struct qmp_phy_cfg - per-PHY initialization config */
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struct qmp_phy_cfg {
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/* phy-type - PCIE/UFS/USB */
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@ -1775,6 +1911,11 @@ static const char * const qmp_v4_phy_clk_l[] = {
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"aux", "ref_clk_src", "ref", "com_aux",
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};
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/* the primary usb3 phy on sm8250 doesn't have a ref clock */
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static const char * const qmp_v4_sm8250_usbphy_clk_l[] = {
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"aux", "ref_clk_src", "com_aux"
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};
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static const char * const sdm845_ufs_phy_clk_l[] = {
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"ref", "ref_aux",
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};
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@ -2246,6 +2387,65 @@ static const struct qmp_phy_cfg sm8150_usb3_uniphy_cfg = {
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.pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
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};
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static const struct qmp_phy_cfg sm8250_usb3phy_cfg = {
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.type = PHY_TYPE_USB3,
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.nlanes = 1,
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.serdes_tbl = sm8150_usb3_serdes_tbl,
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.serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl),
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.tx_tbl = sm8250_usb3_tx_tbl,
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.tx_tbl_num = ARRAY_SIZE(sm8250_usb3_tx_tbl),
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.rx_tbl = sm8250_usb3_rx_tbl,
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.rx_tbl_num = ARRAY_SIZE(sm8250_usb3_rx_tbl),
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.pcs_tbl = sm8250_usb3_pcs_tbl,
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.pcs_tbl_num = ARRAY_SIZE(sm8250_usb3_pcs_tbl),
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.clk_list = qmp_v4_sm8250_usbphy_clk_l,
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.num_clks = ARRAY_SIZE(qmp_v4_sm8250_usbphy_clk_l),
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.reset_list = msm8996_usb3phy_reset_l,
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.num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
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.vreg_list = qmp_phy_vreg_l,
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.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
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.regs = qmp_v4_usb3phy_regs_layout,
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.start_ctrl = SERDES_START | PCS_START,
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.pwrdn_ctrl = SW_PWRDN,
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.has_pwrdn_delay = true,
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.pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
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.pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
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.has_phy_dp_com_ctrl = true,
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.is_dual_lane_phy = true,
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};
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static const struct qmp_phy_cfg sm8250_usb3_uniphy_cfg = {
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.type = PHY_TYPE_USB3,
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.nlanes = 1,
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.serdes_tbl = sm8150_usb3_uniphy_serdes_tbl,
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.serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
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.tx_tbl = sm8250_usb3_uniphy_tx_tbl,
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.tx_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_tx_tbl),
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.rx_tbl = sm8250_usb3_uniphy_rx_tbl,
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.rx_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_rx_tbl),
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.pcs_tbl = sm8250_usb3_uniphy_pcs_tbl,
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.pcs_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_pcs_tbl),
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.clk_list = qmp_v4_phy_clk_l,
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.num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l),
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.reset_list = msm8996_usb3phy_reset_l,
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.num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
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.vreg_list = qmp_phy_vreg_l,
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.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
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.regs = qmp_v4_usb3_uniphy_regs_layout,
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.start_ctrl = SERDES_START | PCS_START,
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.pwrdn_ctrl = SW_PWRDN,
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.has_pwrdn_delay = true,
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.pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
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.pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
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};
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static void qcom_qmp_phy_configure_lane(void __iomem *base,
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const unsigned int *regs,
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const struct qmp_phy_init_tbl tbl[],
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@ -3026,6 +3226,12 @@ static const struct of_device_id qcom_qmp_phy_of_match_table[] = {
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}, {
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.compatible = "qcom,sm8150-qmp-usb3-uni-phy",
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.data = &sm8150_usb3_uniphy_cfg,
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}, {
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.compatible = "qcom,sm8250-qmp-usb3-phy",
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.data = &sm8250_usb3phy_cfg,
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}, {
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.compatible = "qcom,sm8250-qmp-usb3-uni-phy",
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.data = &sm8250_usb3_uniphy_cfg,
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},
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{ },
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};
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@ -364,7 +364,9 @@
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#define QSERDES_V4_TX_RES_CODE_LANE_TX 0x34
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#define QSERDES_V4_TX_RES_CODE_LANE_RX 0x38
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#define QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX 0x3c
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#define QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX 0x40
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#define QSERDES_V4_TX_LANE_MODE_1 0x84
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#define QSERDES_V4_TX_LANE_MODE_2 0x88
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#define QSERDES_V4_TX_RCV_DETECT_LVL_2 0x9c
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#define QSERDES_V4_TX_PWM_GEAR_1_DIVIDER_BAND0_1 0xd8
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#define QSERDES_V4_TX_PWM_GEAR_2_DIVIDER_BAND0_1 0xdC
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