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Alignment in mv643xx_eth

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The driver contains this little piece of candy:

#if defined(CONFIG_DMA_NONCOHERENT) || defined(CONFIG_NOT_COHERENT_CACHE)
#define ETH_DMA_ALIGN           L1_CACHE_BYTES
#else
#define ETH_DMA_ALIGN           8
#endif

Any reason why we're not using dma_get_cache_alignment() instead?

  Ralf

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
This commit is contained in:
Ralf Baechle 2007-02-26 19:52:06 +00:00 committed by Jeff Garzik
parent 92b0c4e240
commit 908b637fe7
2 changed files with 3 additions and 14 deletions
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6
drivers/net/mv643xx_eth.c
View File

@ -147,13 +147,13 @@ static void mv643xx_eth_rx_refill_descs(struct net_device *dev)
int unaligned;
while (mp->rx_desc_count < mp->rx_ring_size) {
skb = dev_alloc_skb(ETH_RX_SKB_SIZE + ETH_DMA_ALIGN);
skb = dev_alloc_skb(ETH_RX_SKB_SIZE + dma_get_cache_alignment());
if (!skb)
break;
mp->rx_desc_count++;
unaligned = (u32)skb->data & (ETH_DMA_ALIGN - 1);
unaligned = (u32)skb->data & (dma_get_cache_alignment() - 1);
if (unaligned)
skb_reserve(skb, ETH_DMA_ALIGN - unaligned);
skb_reserve(skb, dma_get_cache_alignment() - unaligned);
pkt_info.cmd_sts = ETH_RX_ENABLE_INTERRUPT;
pkt_info.byte_cnt = ETH_RX_SKB_SIZE;
pkt_info.buf_ptr = dma_map_single(NULL, skb->data,

11
drivers/net/mv643xx_eth.h
View File

@ -42,17 +42,6 @@
#define MAX_DESCS_PER_SKB 1
#endif
/*
* The MV643XX HW requires 8-byte alignment. However, when I/O
* is non-cache-coherent, we need to ensure that the I/O buffers
* we use don't share cache lines with other data.
*/
#if defined(CONFIG_DMA_NONCOHERENT) || defined(CONFIG_NOT_COHERENT_CACHE)
#define ETH_DMA_ALIGN L1_CACHE_BYTES
#else
#define ETH_DMA_ALIGN 8
#endif
#define ETH_VLAN_HLEN 4
#define ETH_FCS_LEN 4
#define ETH_HW_IP_ALIGN 2 /* hw aligns IP header */