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dma-direct: Force unencrypted DMA under SME for certain DMA masks
If a device doesn't support DMA to a physical address that includes the encryption bit (currently bit 47, so 48-bit DMA), then the DMA must occur to unencrypted memory. SWIOTLB is used to satisfy that requirement if an IOMMU is not active (enabled or configured in passthrough mode). However, commitfafadcd165
("swiotlb: don't dip into swiotlb pool for coherent allocations") modified the coherent allocation support in SWIOTLB to use the DMA direct coherent allocation support. When an IOMMU is not active, this resulted in dma_alloc_coherent() failing for devices that didn't support DMA addresses that included the encryption bit. Addressing this requires changes to the force_dma_unencrypted() function in kernel/dma/direct.c. Since the function is now non-trivial and SME/SEV specific, update the DMA direct support to add an arch override for the force_dma_unencrypted() function. The arch override is selected when CONFIG_AMD_MEM_ENCRYPT is set. The arch override function resides in the arch/x86/mm/mem_encrypt.c file and forces unencrypted DMA when either SEV is active or SME is active and the device does not support DMA to physical addresses that include the encryption bit. Fixes:fafadcd165
("swiotlb: don't dip into swiotlb pool for coherent allocations") Suggested-by: Christoph Hellwig <hch@lst.de> Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Acked-by: Thomas Gleixner <tglx@linutronix.de> [hch: moved the force_dma_unencrypted declaration to dma-mapping.h, fold the s390 fix from Halil Pasic] Signed-off-by: Christoph Hellwig <hch@lst.de>
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9637d51734
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@ -189,6 +189,7 @@ config S390
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select VIRT_CPU_ACCOUNTING
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select ARCH_HAS_SCALED_CPUTIME
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select HAVE_NMI
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select ARCH_HAS_FORCE_DMA_UNENCRYPTED
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select SWIOTLB
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select GENERIC_ALLOCATOR
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@ -30,7 +30,7 @@
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#include <linux/export.h>
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#include <linux/cma.h>
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#include <linux/gfp.h>
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#include <linux/dma-mapping.h>
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#include <linux/dma-direct.h>
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#include <asm/processor.h>
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#include <linux/uaccess.h>
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#include <asm/pgtable.h>
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@ -161,6 +161,11 @@ bool sev_active(void)
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return is_prot_virt_guest();
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}
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bool force_dma_unencrypted(struct device *dev)
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{
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return sev_active();
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}
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/* protected virtualization */
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static void pv_init(void)
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{
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@ -1528,6 +1528,7 @@ config AMD_MEM_ENCRYPT
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depends on X86_64 && CPU_SUP_AMD
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select DYNAMIC_PHYSICAL_MASK
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select ARCH_USE_MEMREMAP_PROT
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select ARCH_HAS_FORCE_DMA_UNENCRYPTED
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---help---
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Say yes to enable support for the encryption of system memory.
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This requires an AMD processor that supports Secure Memory
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@ -15,6 +15,10 @@
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#include <linux/dma-direct.h>
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#include <linux/swiotlb.h>
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#include <linux/mem_encrypt.h>
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#include <linux/device.h>
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#include <linux/kernel.h>
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#include <linux/bitops.h>
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#include <linux/dma-mapping.h>
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#include <asm/tlbflush.h>
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#include <asm/fixmap.h>
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@ -348,6 +352,32 @@ bool sev_active(void)
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}
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EXPORT_SYMBOL(sev_active);
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/* Override for DMA direct allocation check - ARCH_HAS_FORCE_DMA_UNENCRYPTED */
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bool force_dma_unencrypted(struct device *dev)
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{
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/*
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* For SEV, all DMA must be to unencrypted addresses.
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*/
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if (sev_active())
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return true;
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/*
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* For SME, all DMA must be to unencrypted addresses if the
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* device does not support DMA to addresses that include the
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* encryption mask.
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*/
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if (sme_active()) {
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u64 dma_enc_mask = DMA_BIT_MASK(__ffs64(sme_me_mask));
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u64 dma_dev_mask = min_not_zero(dev->coherent_dma_mask,
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dev->bus_dma_mask);
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if (dma_dev_mask <= dma_enc_mask)
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return true;
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}
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return false;
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}
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/* Architecture __weak replacement functions */
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void __init mem_encrypt_free_decrypted_mem(void)
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{
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@ -32,6 +32,15 @@ static inline bool dma_capable(struct device *dev, dma_addr_t addr, size_t size)
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}
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#endif /* !CONFIG_ARCH_HAS_PHYS_TO_DMA */
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#ifdef CONFIG_ARCH_HAS_FORCE_DMA_UNENCRYPTED
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bool force_dma_unencrypted(struct device *dev);
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#else
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static inline bool force_dma_unencrypted(struct device *dev)
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{
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return false;
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}
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#endif /* CONFIG_ARCH_HAS_FORCE_DMA_UNENCRYPTED */
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/*
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* If memory encryption is supported, phys_to_dma will set the memory encryption
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* bit in the DMA address, and dma_to_phys will clear it. The raw __phys_to_dma
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@ -48,6 +48,9 @@ config ARCH_HAS_DMA_COHERENT_TO_PFN
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config ARCH_HAS_DMA_MMAP_PGPROT
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bool
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config ARCH_HAS_FORCE_DMA_UNENCRYPTED
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bool
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config DMA_NONCOHERENT_CACHE_SYNC
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bool
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@ -23,14 +23,6 @@
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#define ARCH_ZONE_DMA_BITS 24
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#endif
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/*
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* For AMD SEV all DMA must be to unencrypted addresses.
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*/
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static inline bool force_dma_unencrypted(void)
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{
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return sev_active();
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}
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static void report_addr(struct device *dev, dma_addr_t dma_addr, size_t size)
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{
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if (!dev->dma_mask) {
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@ -46,7 +38,7 @@ static void report_addr(struct device *dev, dma_addr_t dma_addr, size_t size)
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static inline dma_addr_t phys_to_dma_direct(struct device *dev,
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phys_addr_t phys)
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{
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if (force_dma_unencrypted())
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if (force_dma_unencrypted(dev))
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return __phys_to_dma(dev, phys);
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return phys_to_dma(dev, phys);
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}
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@ -67,7 +59,7 @@ static gfp_t __dma_direct_optimal_gfp_mask(struct device *dev, u64 dma_mask,
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if (dev->bus_dma_mask && dev->bus_dma_mask < dma_mask)
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dma_mask = dev->bus_dma_mask;
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if (force_dma_unencrypted())
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if (force_dma_unencrypted(dev))
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*phys_mask = __dma_to_phys(dev, dma_mask);
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else
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*phys_mask = dma_to_phys(dev, dma_mask);
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@ -159,7 +151,7 @@ void *dma_direct_alloc_pages(struct device *dev, size_t size,
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}
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ret = page_address(page);
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if (force_dma_unencrypted()) {
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if (force_dma_unencrypted(dev)) {
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set_memory_decrypted((unsigned long)ret, 1 << get_order(size));
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*dma_handle = __phys_to_dma(dev, page_to_phys(page));
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} else {
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@ -192,7 +184,7 @@ void dma_direct_free_pages(struct device *dev, size_t size, void *cpu_addr,
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return;
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}
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if (force_dma_unencrypted())
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if (force_dma_unencrypted(dev))
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set_memory_encrypted((unsigned long)cpu_addr, 1 << page_order);
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if (IS_ENABLED(CONFIG_ARCH_HAS_UNCACHED_SEGMENT) &&
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