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net: phy: meson-gxl: check phy_write return value
Always check phy_write return values. Better to be safe than sorry Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -26,27 +26,53 @@
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static int meson_gxl_config_init(struct phy_device *phydev)
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{
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int ret;
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/* Enable Analog and DSP register Bank access by */
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phy_write(phydev, 0x14, 0x0000);
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phy_write(phydev, 0x14, 0x0400);
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phy_write(phydev, 0x14, 0x0000);
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phy_write(phydev, 0x14, 0x0400);
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ret = phy_write(phydev, 0x14, 0x0000);
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if (ret)
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return ret;
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ret = phy_write(phydev, 0x14, 0x0400);
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if (ret)
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return ret;
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ret = phy_write(phydev, 0x14, 0x0000);
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if (ret)
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return ret;
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ret = phy_write(phydev, 0x14, 0x0400);
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if (ret)
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return ret;
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/* Write Analog register 23 */
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phy_write(phydev, 0x17, 0x8E0D);
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phy_write(phydev, 0x14, 0x4417);
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ret = phy_write(phydev, 0x17, 0x8E0D);
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if (ret)
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return ret;
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ret = phy_write(phydev, 0x14, 0x4417);
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if (ret)
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return ret;
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/* Enable fractional PLL */
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phy_write(phydev, 0x17, 0x0005);
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phy_write(phydev, 0x14, 0x5C1B);
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ret = phy_write(phydev, 0x17, 0x0005);
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if (ret)
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return ret;
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ret = phy_write(phydev, 0x14, 0x5C1B);
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if (ret)
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return ret;
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/* Program fraction FR_PLL_DIV1 */
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phy_write(phydev, 0x17, 0x029A);
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phy_write(phydev, 0x14, 0x5C1D);
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ret = phy_write(phydev, 0x17, 0x029A);
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if (ret)
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return ret;
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ret = phy_write(phydev, 0x14, 0x5C1D);
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if (ret)
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return ret;
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/* Program fraction FR_PLL_DIV1 */
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phy_write(phydev, 0x17, 0xAAAA);
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phy_write(phydev, 0x14, 0x5C1C);
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ret = phy_write(phydev, 0x17, 0xAAAA);
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if (ret)
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return ret;
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ret = phy_write(phydev, 0x14, 0x5C1C);
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if (ret)
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return ret;
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return 0;
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}
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