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[ARM] 3404/1: lpd7a40x: AMBA CLCD support
Patch from Marc Singer Board support and LCD panel configurations to integrate lh7a40x's with the amba clcd driver. Signed-off-by: Marc Singer <elf@buici.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Marc Singer
Russell King
parent
2514581eb1
commit
903e2bbda9
241
arch/arm/mach-lh7a40x/clcd.c
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241
arch/arm/mach-lh7a40x/clcd.c
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@ -0,0 +1,241 @@
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/*
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* arch/arm/mach-lh7a40x/clcd.c
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*
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* Copyright (C) 2004 Marc Singer
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* version 2 as published by the Free Software Foundation.
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*
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*/
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#include <linux/config.h>
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#include <linux/init.h>
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#include <linux/device.h>
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#include <linux/dma-mapping.h>
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#include <linux/sysdev.h>
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#include <linux/interrupt.h>
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//#include <linux/module.h>
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//#include <linux/time.h>
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//#include <asm/hardware.h>
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//#include <asm/mach/time.h>
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#include <asm/irq.h>
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#include <asm/mach/irq.h>
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#include <asm/system.h>
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#include <asm/hardware.h>
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#include <linux/amba/bus.h>
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#include <linux/amba/clcd.h>
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#define HRTFTC_HRSETUP __REG(HRTFTC_PHYS + 0x00)
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#define HRTFTC_HRCON __REG(HRTFTC_PHYS + 0x04)
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#define HRTFTC_HRTIMING1 __REG(HRTFTC_PHYS + 0x08)
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#define HRTFTC_HRTIMING2 __REG(HRTFTC_PHYS + 0x0c)
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#define ALI_SETUP __REG(ALI_PHYS + 0x00)
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#define ALI_CONTROL __REG(ALI_PHYS + 0x04)
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#define ALI_TIMING1 __REG(ALI_PHYS + 0x08)
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#define ALI_TIMING2 __REG(ALI_PHYS + 0x0c)
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#include "lcd-panel.h"
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static void lh7a40x_clcd_disable (struct clcd_fb *fb)
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{
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#if defined (CONFIG_MACH_LPD7A400)
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CPLD_CONTROL &= ~(1<<1); /* Disable LCD Vee */
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#endif
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#if defined (CONFIG_MACH_LPD7A404)
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GPIO_PCD &= ~(1<<3); /* Disable LCD Vee */
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#endif
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#if defined (CONFIG_ARCH_LH7A400)
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HRTFTC_HRSETUP &= ~(1<<13); /* Disable HRTFT controller */
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#endif
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#if defined (CONFIG_ARCH_LH7A404)
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ALI_SETUP &= ~(1<<13); /* Disable ALI */
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#endif
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}
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static void lh7a40x_clcd_enable (struct clcd_fb *fb)
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{
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struct clcd_panel_extra* extra
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= (struct clcd_panel_extra*) fb->board_data;
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#if defined (CONFIG_MACH_LPD7A400)
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CPLD_CONTROL |= (1<<1); /* Enable LCD Vee */
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#endif
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#if defined (CONFIG_MACH_LPD7A404)
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GPIO_PCDD &= ~(1<<3); /* Enable LCD Vee */
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GPIO_PCD |= (1<<3);
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#endif
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#if defined (CONFIG_ARCH_LH7A400)
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if (extra) {
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HRTFTC_HRSETUP
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= (1 << 13)
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| ((fb->fb.var.xres - 1) << 4)
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| 0xc
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| (extra->hrmode ? 1 : 0);
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HRTFTC_HRCON
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= ((extra->clsen ? 1 : 0) << 1)
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| ((extra->spsen ? 1 : 0) << 0);
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HRTFTC_HRTIMING1
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= (extra->pcdel << 8)
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| (extra->revdel << 4)
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| (extra->lpdel << 0);
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HRTFTC_HRTIMING2
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= (extra->spldel << 9)
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| (extra->pc2del << 0);
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}
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else
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HRTFTC_HRSETUP
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= (1 << 13)
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| 0xc;
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#endif
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#if defined (CONFIG_ARCH_LH7A404)
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if (extra) {
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ALI_SETUP
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= (1 << 13)
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| ((fb->fb.var.xres - 1) << 4)
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| 0xc
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| (extra->hrmode ? 1 : 0);
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ALI_CONTROL
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= ((extra->clsen ? 1 : 0) << 1)
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| ((extra->spsen ? 1 : 0) << 0);
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ALI_TIMING1
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= (extra->pcdel << 8)
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| (extra->revdel << 4)
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| (extra->lpdel << 0);
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ALI_TIMING2
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= (extra->spldel << 9)
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| (extra->pc2del << 0);
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}
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else
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ALI_SETUP
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= (1 << 13)
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| 0xc;
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#endif
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}
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#define FRAMESIZE(s) (((s) + PAGE_SIZE - 1)&PAGE_MASK)
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static int lh7a40x_clcd_setup (struct clcd_fb *fb)
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{
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dma_addr_t dma;
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u32 len = FRAMESIZE (lcd_panel.mode.xres*lcd_panel.mode.yres
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*(lcd_panel.bpp/8));
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fb->panel = &lcd_panel;
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/* Enforce the sync polarity defaults */
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if (!(fb->panel->tim2 & TIM2_IHS))
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fb->fb.var.sync |= FB_SYNC_HOR_HIGH_ACT;
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if (!(fb->panel->tim2 & TIM2_IVS))
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fb->fb.var.sync |= FB_SYNC_VERT_HIGH_ACT;
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#if defined (HAS_LCD_PANEL_EXTRA)
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fb->board_data = &lcd_panel_extra;
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#endif
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fb->fb.screen_base
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= dma_alloc_writecombine (&fb->dev->dev, len,
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&dma, GFP_KERNEL);
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printk ("CLCD: LCD setup fb virt 0x%p phys 0x%p l %x io 0x%p \n",
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fb->fb.screen_base, (void*) dma, len,
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(void*) io_p2v (CLCDC_PHYS));
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printk ("CLCD: pixclock %d\n", lcd_panel.mode.pixclock);
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if (!fb->fb.screen_base) {
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printk(KERN_ERR "CLCD: unable to map framebuffer\n");
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return -ENOMEM;
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}
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#if defined (USE_RGB555)
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fb->fb.var.green.length = 5; /* Panel uses RGB 5:5:5 */
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#endif
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fb->fb.fix.smem_start = dma;
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fb->fb.fix.smem_len = len;
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/* Drive PE4 high to prevent CPLD crash */
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GPIO_PEDD |= (1<<4);
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GPIO_PED |= (1<<4);
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GPIO_PINMUX |= (1<<1) | (1<<0); /* LCDVD[15:4] */
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// fb->fb.fbops->fb_check_var (&fb->fb.var, &fb->fb);
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// fb->fb.fbops->fb_set_par (&fb->fb);
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return 0;
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}
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static int lh7a40x_clcd_mmap (struct clcd_fb *fb, struct vm_area_struct *vma)
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{
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return dma_mmap_writecombine(&fb->dev->dev, vma,
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fb->fb.screen_base,
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fb->fb.fix.smem_start,
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fb->fb.fix.smem_len);
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}
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static void lh7a40x_clcd_remove (struct clcd_fb *fb)
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{
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dma_free_writecombine (&fb->dev->dev, fb->fb.fix.smem_len,
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fb->fb.screen_base, fb->fb.fix.smem_start);
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}
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static struct clcd_board clcd_platform_data = {
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.name = "lh7a40x FB",
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.check = clcdfb_check,
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.decode = clcdfb_decode,
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.enable = lh7a40x_clcd_enable,
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.setup = lh7a40x_clcd_setup,
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.mmap = lh7a40x_clcd_mmap,
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.remove = lh7a40x_clcd_remove,
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.disable = lh7a40x_clcd_disable,
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};
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#define IRQ_CLCDC (IRQ_LCDINTR)
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#define AMBA_DEVICE(name,busid,base,plat,pid) \
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static struct amba_device name##_device = { \
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.dev = { \
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.coherent_dma_mask = ~0, \
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.bus_id = busid, \
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.platform_data = plat, \
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}, \
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.res = { \
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.start = base##_PHYS, \
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.end = (base##_PHYS) + (4*1024) - 1, \
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.flags = IORESOURCE_MEM, \
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}, \
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.dma_mask = ~0, \
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.irq = { IRQ_##base, }, \
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/* .dma = base##_DMA,*/ \
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.periphid = pid, \
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}
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AMBA_DEVICE(clcd, "cldc-lh7a40x", CLCDC, &clcd_platform_data, 0x41110);
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static struct amba_device *amba_devs[] __initdata = {
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&clcd_device,
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};
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void __init lh7a40x_clcd_init (void)
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{
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int i;
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int result;
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printk ("CLCD: registering amba devices\n");
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for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
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struct amba_device *d = amba_devs[i];
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result = amba_device_register(d, &iomem_resource);
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printk (" %d -> %d\n", i ,result);
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}
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}
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@ -167,6 +167,69 @@ config FB_ARMCLCD
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here and read <file:Documentation/modules.txt>. The module
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will be called amba-clcd.
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choice
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depends on FB_ARMCLCD && (ARCH_LH7A40X || ARCH_LH7952X)
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prompt "LCD Panel"
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default FB_ARMCLCD_SHARP_LQ035Q7DB02
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config FB_ARMCLCD_SHARP_LQ035Q7DB02_HRTFT
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bool "LogicPD LCD 3.5\" QVGA w/HRTFT IC"
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help
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This is an implementation of the Sharp LQ035Q7DB02, a 3.5"
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color QVGA, HRTFT panel. The LogicPD device includes an
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an integrated HRTFT controller IC.
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The native resolution is 240x320.
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config FB_ARMCLCD_SHARP_LQ057Q3DC02
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bool "LogicPD LCD 5.7\" QVGA"
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help
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This is an implementation of the Sharp LQ057Q3DC02, a 5.7"
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color QVGA, TFT panel. The LogicPD device includes an
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The native resolution is 320x240.
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config FB_ARMCLCD_SHARP_LQ64D343
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bool "LogicPD LCD 6.4\" VGA"
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help
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This is an implementation of the Sharp LQ64D343, a 6.4"
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color VGA, TFT panel. The LogicPD device includes an
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The native resolution is 640x480.
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config FB_ARMCLCD_SHARP_LQ10D368
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bool "LogicPD LCD 10.4\" VGA"
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help
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This is an implementation of the Sharp LQ10D368, a 10.4"
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color VGA, TFT panel. The LogicPD device includes an
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The native resolution is 640x480.
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config FB_ARMCLCD_SHARP_LQ121S1DG41
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bool "LogicPD LCD 12.1\" SVGA"
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help
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This is an implementation of the Sharp LQ121S1DG41, a 12.1"
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color SVGA, TFT panel. The LogicPD device includes an
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The native resolution is 800x600.
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This panel requires a clock rate may be an integer fraction
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of the base LCDCLK frequency. The driver will select the
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highest frequency available that is lower than the maximum
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allowed. The panel may flicker if the clock rate is
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slower than the recommended minimum.
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config FB_ARMCLCD_AUO_A070VW01_WIDE
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bool "AU Optronics A070VW01 LCD 7.0\" WIDE"
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help
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This is an implementation of the AU Optronics, a 7.0"
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WIDE Color. The native resolution is 234x480.
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config FB_ARMCLCD_HITACHI
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bool "Hitachi Wide Screen 800x480"
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help
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This is an implementation of the Hitachi 800x480.
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endchoice
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config FB_ACORN
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bool "Acorn VIDC support"
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depends on (FB = y) && ARM && (ARCH_ACORN || ARCH_CLPS7500)
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