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media: staging: atomisp: Don't override D3 delay settings here

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The d3_delay parameter is set by arch/x86/pci/intel_mid_pci.c and
drivers/pci/quirks.c.

No need to override that settings in unrelated driver.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab@s-opensource.com>
This commit is contained in:
Andy Shevchenko 2017-09-01 09:36:35 -04:00 committed by Mauro Carvalho Chehab
parent 5fc90b632e
commit 90154e130f
2 changed files with 0 additions and 41 deletions
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8
drivers/staging/media/atomisp/include/asm/intel_mid_pcihelpers.h
View File

@ -18,14 +18,6 @@
#define PCI_ROOT_MSGBUS_WRITE 0x11
#define PCI_ROOT_MSGBUS_DWORD_ENABLE 0xf0
/* In BYT platform for all internal PCI devices d3 delay
* of 3 ms is sufficient. Default value of 10 ms is overkill.
*/
#define INTERNAL_PCI_PM_D3_WAIT 3
#define ISP_SUB_CLASS 0x80
#define SUB_CLASS_MASK 0xFF00
u32 intel_mid_msgbus_read32_raw(u32 cmd);
u32 intel_mid_msgbus_read32(u8 port, u32 addr);
void intel_mid_msgbus_write32_raw(u32 cmd, u32 data);

33
drivers/staging/media/atomisp/platform/intel-mid/intel_mid_pcihelpers.c
View File

@ -161,36 +161,3 @@ u32 intel_mid_soc_stepping(void)
return pci_root->revision;
}
EXPORT_SYMBOL(intel_mid_soc_stepping);
static bool is_south_complex_device(struct pci_dev *dev)
{
unsigned int base_class = dev->class >> 16;
unsigned int sub_class = (dev->class & SUB_CLASS_MASK) >> 8;
/* other than camera, pci bridges and display,
* everything else are south complex devices.
*/
if (((base_class == PCI_BASE_CLASS_MULTIMEDIA) &&
(sub_class == ISP_SUB_CLASS)) ||
(base_class == PCI_BASE_CLASS_BRIDGE) ||
((base_class == PCI_BASE_CLASS_DISPLAY) && !sub_class))
return false;
else
return true;
}
/* In BYT platform, d3_delay for internal south complex devices,
* they are not subject to 10 ms d3 to d0 delay required by pci spec.
*/
static void pci_d3_delay_fixup(struct pci_dev *dev)
{
if (platform_is(INTEL_ATOM_BYT) ||
platform_is(INTEL_ATOM_CHT)) {
/* All internal devices are in bus 0. */
if (dev->bus->number == 0 && is_south_complex_device(dev)) {
dev->d3_delay = INTERNAL_PCI_PM_D3_WAIT;
dev->d3cold_delay = INTERNAL_PCI_PM_D3_WAIT;
}
}
}
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_d3_delay_fixup);