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drm/amdgpu: remove unsafe optimization to drop preamble ib
[ Upstream commit 7d9c70d23550eb86a1bec1954ccaa8d6ec3a3328 ] Take the situation with gfxoff, the optimization may cause corrupt CE ram contents. In addition emit_cntxcntl callback has similar optimization which firmware can handle properly even for power feature. Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Sasha Levin <sashal@kernel.org>
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@ -128,7 +128,7 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
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struct amdgpu_device *adev = ring->adev;
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struct amdgpu_ib *ib = &ibs[0];
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struct dma_fence *tmp = NULL;
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bool skip_preamble, need_ctx_switch;
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bool need_ctx_switch;
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unsigned patch_offset = ~0;
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struct amdgpu_vm *vm;
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uint64_t fence_ctx;
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@ -221,7 +221,6 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
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if (need_ctx_switch)
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status |= AMDGPU_HAVE_CTX_SWITCH;
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skip_preamble = ring->current_ctx == fence_ctx;
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if (job && ring->funcs->emit_cntxcntl) {
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status |= job->preamble_status;
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status |= job->preemption_status;
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@ -239,14 +238,6 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
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for (i = 0; i < num_ibs; ++i) {
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ib = &ibs[i];
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/* drop preamble IBs if we don't have a context switch */
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if ((ib->flags & AMDGPU_IB_FLAG_PREAMBLE) &&
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skip_preamble &&
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!(status & AMDGPU_PREAMBLE_IB_PRESENT_FIRST) &&
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!amdgpu_mcbp &&
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!amdgpu_sriov_vf(adev)) /* for SRIOV preemption, Preamble CE ib must be inserted anyway */
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continue;
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if (job && ring->funcs->emit_frame_cntl) {
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if (secure != !!(ib->flags & AMDGPU_IB_FLAGS_SECURE)) {
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amdgpu_ring_emit_frame_cntl(ring, false, secure);
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