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drm/i915: Explicitly pin the logical context for execbuf
In order to separate the reservation phase of building a request from its emission phase, we need to pull some of the request alloc activities from deep inside i915_request to the surface, GEM_EXECBUFFER. v2: Be frivolous, use a local drm_i915_private. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190425050143.811-1-chris@chris-wilson.co.uk
This commit is contained in:
Chris Wilson
parent
79ffac8599
commit
8f2a1057d6
@ -34,6 +34,8 @@
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#include <drm/drm_syncobj.h>
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#include <drm/i915_drm.h>
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#include "gt/intel_gt_pm.h"
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#include "i915_drv.h"
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#include "i915_gem_clflush.h"
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#include "i915_trace.h"
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@ -236,7 +238,8 @@ struct i915_execbuffer {
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unsigned int *flags;
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struct intel_engine_cs *engine; /** engine to queue the request to */
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struct i915_gem_context *ctx; /** context for building the request */
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struct intel_context *context; /* logical state for the request */
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struct i915_gem_context *gem_context; /** caller's context */
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struct i915_address_space *vm; /** GTT and vma for the request */
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struct i915_request *request; /** our request to build */
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@ -738,7 +741,7 @@ static int eb_select_context(struct i915_execbuffer *eb)
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if (unlikely(!ctx))
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return -ENOENT;
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eb->ctx = ctx;
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eb->gem_context = ctx;
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if (ctx->ppgtt) {
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eb->vm = &ctx->ppgtt->vm;
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eb->invalid_flags |= EXEC_OBJECT_NEEDS_GTT;
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@ -784,7 +787,6 @@ static struct i915_request *__eb_wait_for_ring(struct intel_ring *ring)
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static int eb_wait_for_ring(const struct i915_execbuffer *eb)
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{
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const struct intel_context *ce;
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struct i915_request *rq;
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int ret = 0;
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@ -794,11 +796,7 @@ static int eb_wait_for_ring(const struct i915_execbuffer *eb)
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* keeping all of their resources pinned.
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*/
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ce = intel_context_lookup(eb->ctx, eb->engine);
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if (!ce || !ce->ring) /* first use, assume empty! */
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return 0;
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rq = __eb_wait_for_ring(ce->ring);
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rq = __eb_wait_for_ring(eb->context->ring);
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if (rq) {
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mutex_unlock(&eb->i915->drm.struct_mutex);
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@ -817,15 +815,15 @@ static int eb_wait_for_ring(const struct i915_execbuffer *eb)
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static int eb_lookup_vmas(struct i915_execbuffer *eb)
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{
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struct radix_tree_root *handles_vma = &eb->ctx->handles_vma;
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struct radix_tree_root *handles_vma = &eb->gem_context->handles_vma;
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struct drm_i915_gem_object *obj;
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unsigned int i, batch;
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int err;
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if (unlikely(i915_gem_context_is_closed(eb->ctx)))
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if (unlikely(i915_gem_context_is_closed(eb->gem_context)))
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return -ENOENT;
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if (unlikely(i915_gem_context_is_banned(eb->ctx)))
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if (unlikely(i915_gem_context_is_banned(eb->gem_context)))
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return -EIO;
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INIT_LIST_HEAD(&eb->relocs);
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@ -870,8 +868,8 @@ static int eb_lookup_vmas(struct i915_execbuffer *eb)
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if (!vma->open_count++)
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i915_vma_reopen(vma);
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list_add(&lut->obj_link, &obj->lut_list);
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list_add(&lut->ctx_link, &eb->ctx->handles_list);
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lut->ctx = eb->ctx;
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list_add(&lut->ctx_link, &eb->gem_context->handles_list);
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lut->ctx = eb->gem_context;
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lut->handle = handle;
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add_vma:
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@ -1227,7 +1225,7 @@ static int __reloc_gpu_alloc(struct i915_execbuffer *eb,
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if (err)
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goto err_unmap;
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rq = i915_request_alloc(eb->engine, eb->ctx);
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rq = i915_request_create(eb->context);
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if (IS_ERR(rq)) {
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err = PTR_ERR(rq);
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goto err_unpin;
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@ -2088,31 +2086,65 @@ static const enum intel_engine_id user_ring_map[I915_USER_RINGS + 1] = {
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[I915_EXEC_VEBOX] = VECS0
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};
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static struct intel_engine_cs *
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eb_select_engine(struct drm_i915_private *dev_priv,
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static int eb_pin_context(struct i915_execbuffer *eb,
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struct intel_engine_cs *engine)
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{
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struct intel_context *ce;
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int err;
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/*
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* ABI: Before userspace accesses the GPU (e.g. execbuffer), report
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* EIO if the GPU is already wedged.
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*/
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err = i915_terminally_wedged(eb->i915);
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if (err)
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return err;
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/*
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* Pinning the contexts may generate requests in order to acquire
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* GGTT space, so do this first before we reserve a seqno for
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* ourselves.
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*/
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ce = intel_context_pin(eb->gem_context, engine);
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if (IS_ERR(ce))
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return PTR_ERR(ce);
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eb->engine = engine;
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eb->context = ce;
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return 0;
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}
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static void eb_unpin_context(struct i915_execbuffer *eb)
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{
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intel_context_unpin(eb->context);
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}
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static int
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eb_select_engine(struct i915_execbuffer *eb,
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struct drm_file *file,
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struct drm_i915_gem_execbuffer2 *args)
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{
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struct drm_i915_private *i915 = eb->i915;
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unsigned int user_ring_id = args->flags & I915_EXEC_RING_MASK;
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struct intel_engine_cs *engine;
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if (user_ring_id > I915_USER_RINGS) {
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DRM_DEBUG("execbuf with unknown ring: %u\n", user_ring_id);
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return NULL;
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return -EINVAL;
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}
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if ((user_ring_id != I915_EXEC_BSD) &&
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((args->flags & I915_EXEC_BSD_MASK) != 0)) {
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DRM_DEBUG("execbuf with non bsd ring but with invalid "
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"bsd dispatch flags: %d\n", (int)(args->flags));
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return NULL;
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return -EINVAL;
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}
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if (user_ring_id == I915_EXEC_BSD && HAS_ENGINE(dev_priv, VCS1)) {
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if (user_ring_id == I915_EXEC_BSD && HAS_ENGINE(i915, VCS1)) {
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unsigned int bsd_idx = args->flags & I915_EXEC_BSD_MASK;
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if (bsd_idx == I915_EXEC_BSD_DEFAULT) {
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bsd_idx = gen8_dispatch_bsd_engine(dev_priv, file);
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bsd_idx = gen8_dispatch_bsd_engine(i915, file);
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} else if (bsd_idx >= I915_EXEC_BSD_RING1 &&
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bsd_idx <= I915_EXEC_BSD_RING2) {
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bsd_idx >>= I915_EXEC_BSD_SHIFT;
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@ -2120,20 +2152,20 @@ eb_select_engine(struct drm_i915_private *dev_priv,
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} else {
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DRM_DEBUG("execbuf with unknown bsd ring: %u\n",
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bsd_idx);
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return NULL;
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return -EINVAL;
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}
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engine = dev_priv->engine[_VCS(bsd_idx)];
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engine = i915->engine[_VCS(bsd_idx)];
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} else {
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engine = dev_priv->engine[user_ring_map[user_ring_id]];
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engine = i915->engine[user_ring_map[user_ring_id]];
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}
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if (!engine) {
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DRM_DEBUG("execbuf with invalid ring: %u\n", user_ring_id);
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return NULL;
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return -EINVAL;
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}
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return engine;
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return eb_pin_context(eb, engine);
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}
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static void
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@ -2275,7 +2307,6 @@ i915_gem_do_execbuffer(struct drm_device *dev,
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struct i915_execbuffer eb;
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struct dma_fence *in_fence = NULL;
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struct sync_file *out_fence = NULL;
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intel_wakeref_t wakeref;
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int out_fence_fd = -1;
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int err;
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@ -2335,12 +2366,6 @@ i915_gem_do_execbuffer(struct drm_device *dev,
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if (unlikely(err))
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goto err_destroy;
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eb.engine = eb_select_engine(eb.i915, file, args);
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if (!eb.engine) {
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err = -EINVAL;
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goto err_engine;
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}
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/*
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* Take a local wakeref for preparing to dispatch the execbuf as
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* we expect to access the hardware fairly frequently in the
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@ -2348,16 +2373,20 @@ i915_gem_do_execbuffer(struct drm_device *dev,
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* wakeref that we hold until the GPU has been idle for at least
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* 100ms.
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*/
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wakeref = intel_runtime_pm_get(eb.i915);
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intel_gt_pm_get(eb.i915);
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err = i915_mutex_lock_interruptible(dev);
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if (err)
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goto err_rpm;
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err = eb_wait_for_ring(&eb); /* may temporarily drop struct_mutex */
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err = eb_select_engine(&eb, file, args);
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if (unlikely(err))
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goto err_unlock;
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err = eb_wait_for_ring(&eb); /* may temporarily drop struct_mutex */
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if (unlikely(err))
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goto err_engine;
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err = eb_relocate(&eb);
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if (err) {
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/*
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@ -2441,7 +2470,7 @@ i915_gem_do_execbuffer(struct drm_device *dev,
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GEM_BUG_ON(eb.reloc_cache.rq);
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/* Allocate a request for this batch buffer nice and early. */
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eb.request = i915_request_alloc(eb.engine, eb.ctx);
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eb.request = i915_request_create(eb.context);
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if (IS_ERR(eb.request)) {
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err = PTR_ERR(eb.request);
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goto err_batch_unpin;
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@ -2479,8 +2508,8 @@ i915_gem_do_execbuffer(struct drm_device *dev,
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trace_i915_request_queue(eb.request, eb.batch_flags);
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err = eb_submit(&eb);
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err_request:
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i915_request_add(eb.request);
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add_to_client(eb.request, file);
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i915_request_add(eb.request);
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if (fences)
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signal_fence_array(&eb, fences);
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@ -2502,12 +2531,13 @@ i915_gem_do_execbuffer(struct drm_device *dev,
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err_vma:
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if (eb.exec)
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eb_release_vmas(&eb);
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err_engine:
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eb_unpin_context(&eb);
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err_unlock:
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mutex_unlock(&dev->struct_mutex);
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err_rpm:
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intel_runtime_pm_put(eb.i915, wakeref);
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err_engine:
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i915_gem_context_put(eb.ctx);
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intel_gt_pm_put(eb.i915);
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i915_gem_context_put(eb.gem_context);
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err_destroy:
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eb_destroy(&eb);
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err_out_fence:
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@ -785,7 +785,6 @@ i915_request_alloc(struct intel_engine_cs *engine, struct i915_gem_context *ctx)
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struct drm_i915_private *i915 = engine->i915;
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struct intel_context *ce;
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struct i915_request *rq;
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int ret;
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/*
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* Preempt contexts are reserved for exclusive use to inject a
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@ -794,14 +793,6 @@ i915_request_alloc(struct intel_engine_cs *engine, struct i915_gem_context *ctx)
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*/
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GEM_BUG_ON(ctx == i915->preempt_context);
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/*
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* ABI: Before userspace accesses the GPU (e.g. execbuffer), report
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* EIO if the GPU is already wedged.
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*/
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ret = i915_terminally_wedged(i915);
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if (ret)
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return ERR_PTR(ret);
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/*
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* Pinning the contexts may generate requests in order to acquire
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* GGTT space, so do this first before we reserve a seqno for
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