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net: dsa: mv88e6xxx: add cap for IRL
Add capability flags to describe the presence of Ingress Rate Limit unit registers and an helper function to clear it. In the meantime, fix a few harmless issues: - 6185 and 6095 don't have such registers (reserved) - the previous code didn't wait for the IRL operation to complete Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Vivien Didelot
David S. Miller
parent
9bda889fae
commit
8ec61c7f7c
@ -3150,6 +3150,29 @@ static int mv88e6xxx_g2_clear_trunk(struct mv88e6xxx_chip *chip)
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return 0;
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}
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static int mv88e6xxx_g2_clear_irl(struct mv88e6xxx_chip *chip)
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{
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int port, err;
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/* Init all Ingress Rate Limit resources of all ports */
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for (port = 0; port < chip->info->num_ports; ++port) {
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/* XXX newer chips (like 88E6390) have different 2-bit ops */
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err = mv88e6xxx_write(chip, REG_GLOBAL2, GLOBAL2_IRL_CMD,
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GLOBAL2_IRL_CMD_OP_INIT_ALL |
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(port << 8));
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if (err)
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break;
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/* Wait for the operation to complete */
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err = _mv88e6xxx_wait(chip, REG_GLOBAL2, GLOBAL2_IRL_CMD,
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GLOBAL2_IRL_CMD_BUSY);
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if (err)
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break;
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}
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return err;
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}
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/* Indirect write to the Switch MAC/WoL/WoF register */
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static int mv88e6xxx_g2_switch_mac_write(struct mv88e6xxx_chip *chip,
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unsigned int pointer, u8 data)
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@ -3198,7 +3221,6 @@ static int mv88e6xxx_g2_setup(struct mv88e6xxx_chip *chip)
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{
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u16 reg;
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int err;
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int i;
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if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_MGMT_EN_2X)) {
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/* Consider the frames with reserved multicast destination
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@ -3243,6 +3265,15 @@ static int mv88e6xxx_g2_setup(struct mv88e6xxx_chip *chip)
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if (err)
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return err;
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if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_IRL)) {
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/* Disable ingress rate limiting by resetting all per port
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* ingress rate limit resources to their initial state.
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*/
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err = mv88e6xxx_g2_clear_irl(chip);
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if (err)
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return err;
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}
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if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_PVT)) {
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/* Initialize Cross-chip Port VLAN Table to reset defaults */
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err = mv88e6xxx_write(chip, REG_GLOBAL2, GLOBAL2_PVT_ADDR,
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@ -3258,23 +3289,6 @@ static int mv88e6xxx_g2_setup(struct mv88e6xxx_chip *chip)
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return err;
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}
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if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
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mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) ||
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mv88e6xxx_6185_family(chip) || mv88e6xxx_6095_family(chip) ||
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mv88e6xxx_6320_family(chip)) {
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/* Disable ingress rate limiting by resetting all
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* ingress rate limit registers to their initial
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* state.
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*/
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for (i = 0; i < chip->info->num_ports; i++) {
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err = _mv88e6xxx_reg_write(chip, REG_GLOBAL2,
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GLOBAL2_INGRESS_OP,
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0x9000 | (i << 8));
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if (err)
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return err;
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}
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}
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return 0;
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}
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@ -298,8 +298,13 @@
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#define GLOBAL2_TRUNK_MAPPING 0x08
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#define GLOBAL2_TRUNK_MAPPING_UPDATE BIT(15)
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#define GLOBAL2_TRUNK_MAPPING_ID_SHIFT 11
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#define GLOBAL2_INGRESS_OP 0x09
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#define GLOBAL2_INGRESS_DATA 0x0a
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#define GLOBAL2_IRL_CMD 0x09
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#define GLOBAL2_IRL_CMD_BUSY BIT(15)
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#define GLOBAL2_IRL_CMD_OP_INIT_ALL ((0x001 << 12) | GLOBAL2_IRL_CMD_BUSY)
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#define GLOBAL2_IRL_CMD_OP_INIT_SEL ((0x010 << 12) | GLOBAL2_IRL_CMD_BUSY)
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#define GLOBAL2_IRL_CMD_OP_WRITE_SEL ((0x011 << 12) | GLOBAL2_IRL_CMD_BUSY)
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#define GLOBAL2_IRL_CMD_OP_READ_SEL ((0x100 << 12) | GLOBAL2_IRL_CMD_BUSY)
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#define GLOBAL2_IRL_DATA 0x0a
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#define GLOBAL2_PVT_ADDR 0x0b
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#define GLOBAL2_PVT_ADDR_BUSY BIT(15)
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#define GLOBAL2_PVT_ADDR_OP_INIT_ONES ((0x01 << 12) | GLOBAL2_PVT_ADDR_BUSY)
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@ -393,6 +398,8 @@ enum mv88e6xxx_cap {
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MV88E6XXX_CAP_GLOBAL2,
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MV88E6XXX_CAP_G2_MGMT_EN_2X, /* (0x02) MGMT Enable Register 2x */
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MV88E6XXX_CAP_G2_MGMT_EN_0X, /* (0x03) MGMT Enable Register 0x */
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MV88E6XXX_CAP_G2_IRL_CMD, /* (0x09) Ingress Rate Command */
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MV88E6XXX_CAP_G2_IRL_DATA, /* (0x0a) Ingress Rate Data */
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MV88E6XXX_CAP_G2_PVT_ADDR, /* (0x0b) Cross Chip Port VLAN Addr */
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MV88E6XXX_CAP_G2_PVT_DATA, /* (0x0c) Cross Chip Port VLAN Data */
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MV88E6XXX_CAP_G2_SWITCH_MAC, /* (0x0d) Switch MAC/WoL/WoF */
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@ -440,6 +447,8 @@ enum mv88e6xxx_cap {
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#define MV88E6XXX_FLAG_GLOBAL2 BIT(MV88E6XXX_CAP_GLOBAL2)
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#define MV88E6XXX_FLAG_G2_MGMT_EN_2X BIT(MV88E6XXX_CAP_G2_MGMT_EN_2X)
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#define MV88E6XXX_FLAG_G2_MGMT_EN_0X BIT(MV88E6XXX_CAP_G2_MGMT_EN_0X)
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#define MV88E6XXX_FLAG_G2_IRL_CMD BIT(MV88E6XXX_CAP_G2_IRL_CMD)
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#define MV88E6XXX_FLAG_G2_IRL_DATA BIT(MV88E6XXX_CAP_G2_IRL_DATA)
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#define MV88E6XXX_FLAG_G2_PVT_ADDR BIT(MV88E6XXX_CAP_G2_PVT_ADDR)
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#define MV88E6XXX_FLAG_G2_PVT_DATA BIT(MV88E6XXX_CAP_G2_PVT_DATA)
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#define MV88E6XXX_FLAG_G2_SWITCH_MAC BIT(MV88E6XXX_CAP_G2_SWITCH_MAC)
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@ -453,6 +462,11 @@ enum mv88e6xxx_cap {
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#define MV88E6XXX_FLAG_TEMP_LIMIT BIT(MV88E6XXX_CAP_TEMP_LIMIT)
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#define MV88E6XXX_FLAG_VTU BIT(MV88E6XXX_CAP_VTU)
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/* Ingress Rate Limit unit */
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#define MV88E6XXX_FLAGS_IRL \
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(MV88E6XXX_FLAG_G2_IRL_CMD | \
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MV88E6XXX_FLAG_G2_IRL_DATA)
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/* Cross-chip Port VLAN Table */
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#define MV88E6XXX_FLAGS_PVT \
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(MV88E6XXX_FLAG_G2_PVT_ADDR | \
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@ -474,6 +488,7 @@ enum mv88e6xxx_cap {
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MV88E6XXX_FLAG_PPU | \
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MV88E6XXX_FLAG_STU | \
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MV88E6XXX_FLAG_VTU | \
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MV88E6XXX_FLAGS_IRL | \
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MV88E6XXX_FLAGS_PVT)
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#define MV88E6XXX_FLAGS_FAMILY_6165 \
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@ -486,6 +501,7 @@ enum mv88e6xxx_cap {
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MV88E6XXX_FLAG_STU | \
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MV88E6XXX_FLAG_TEMP | \
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MV88E6XXX_FLAG_VTU | \
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MV88E6XXX_FLAGS_IRL | \
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MV88E6XXX_FLAGS_PVT)
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#define MV88E6XXX_FLAGS_FAMILY_6185 \
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@ -509,6 +525,7 @@ enum mv88e6xxx_cap {
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MV88E6XXX_FLAG_TEMP | \
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MV88E6XXX_FLAG_TEMP_LIMIT | \
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MV88E6XXX_FLAG_VTU | \
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MV88E6XXX_FLAGS_IRL | \
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MV88E6XXX_FLAGS_PVT)
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#define MV88E6XXX_FLAGS_FAMILY_6351 \
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@ -523,6 +540,7 @@ enum mv88e6xxx_cap {
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MV88E6XXX_FLAG_STU | \
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MV88E6XXX_FLAG_TEMP | \
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MV88E6XXX_FLAG_VTU | \
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MV88E6XXX_FLAGS_IRL | \
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MV88E6XXX_FLAGS_PVT)
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#define MV88E6XXX_FLAGS_FAMILY_6352 \
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@ -540,6 +558,7 @@ enum mv88e6xxx_cap {
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MV88E6XXX_FLAG_TEMP | \
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MV88E6XXX_FLAG_TEMP_LIMIT | \
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MV88E6XXX_FLAG_VTU | \
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MV88E6XXX_FLAGS_IRL | \
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MV88E6XXX_FLAGS_PVT)
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struct mv88e6xxx_info {
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