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drm/amd/display: fix hubp mpcc and opp tracking

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This should be handled by mi and mpc only

Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Dmytro Laktyushkin 2017-07-28 08:16:27 -04:00 committed by Alex Deucher
parent f670af8a95
commit 8eb5def957
3 changed files with 5 additions and 6 deletions
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2
drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c
View File

@ -686,6 +686,8 @@ void dce_mem_input_construct(
dce_mi->shifts = mi_shift;
dce_mi->masks = mi_mask;
dce_mi->base.mpcc_id = 0xf;
dce_mi->base.opp_id = 0xf;
}
void dce112_mem_input_construct(

6
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
View File

@ -1066,9 +1066,6 @@ static void plane_atomic_disable(struct dc *dc,
fe_idx);*/
mi->funcs->set_blank(mi, true);
/*todo: unhack this*/
mi->opp_id = 0xf;
mi->mpcc_id = 0xf;
if (dc->debug.sanity_checks)
verify_allow_pstate_change_high(dc->hwseq);
@ -2304,7 +2301,8 @@ static void update_dchubp_dpp(
&plane_state->dcc,
plane_state->horizontal_mirror);
mi->funcs->set_blank(mi, !is_pipe_tree_visible(pipe_ctx));
if (is_pipe_tree_visible(pipe_ctx))
mi->funcs->set_blank(mi, false);
}

3
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c
View File

@ -51,9 +51,8 @@ static void min10_set_blank(struct mem_input *mem_input, bool blank)
REG_WAIT(DCHUBP_CNTL,
HUBP_NO_OUTSTANDING_REQ, 1,
1, 200);
/*todo: unhack this
mem_input->mpcc_id = 0xf;
mem_input->opp_id = 0xf;*/
mem_input->opp_id = 0xf;
}
}