mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-11-25 00:50:54 +07:00
Merge branch 'x86-platform-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull x86 platform updates from Ingo Molnar: "The main changes in this cycle were: - Intel-SoC enhancements (Andy Shevchenko) - Intel CPU symbolic model definition rework (Dave Hansen) - ... other misc changes" * 'x86-platform-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (25 commits) x86/sfi: Enable enumeration of SD devices x86/pci: Use MRFLD abbreviation for Merrifield x86/platform/intel-mid: Make vertical indentation consistent x86/platform/intel-mid: Mark regulators explicitly defined x86/platform/intel-mid: Rename mrfl.c to mrfld.c x86/platform/intel-mid: Enable spidev on Intel Edison boards x86/platform/intel-mid: Extend PWRMU to support Penwell x86/pci, x86/platform/intel_mid_pci: Remove duplicate power off code x86/platform/intel-mid: Add pinctrl for Intel Merrifield x86/platform/intel-mid: Enable GPIO expanders on Edison x86/platform/intel-mid: Add Power Management Unit driver x86/platform/atom/punit: Enable support for Merrifield x86/platform/intel_mid_pci: Rework IRQ0 workaround x86, thermal: Clean up and fix CPU model detection for intel_soc_dts_thermal x86, mmc: Use Intel family name macros for mmc driver x86/intel_telemetry: Use Intel family name macros for telemetry driver x86/acpi/lss: Use Intel family name macros for the acpi_lpss driver x86/cpufreq: Use Intel family name macros for the intel_pstate cpufreq driver x86/platform: Use new Intel model number macros x86/intel_idle: Use Intel family macros for intel_idle ...
This commit is contained in:
Linus Torvalds
commit
8e466955d6
@ -12,9 +12,17 @@
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#define _ASM_X86_INTEL_MID_H
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#include <linux/sfi.h>
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#include <linux/pci.h>
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#include <linux/platform_device.h>
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extern int intel_mid_pci_init(void);
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extern int intel_mid_pci_set_power_state(struct pci_dev *pdev, pci_power_t state);
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#define INTEL_MID_PWR_LSS_OFFSET 4
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#define INTEL_MID_PWR_LSS_TYPE (1 << 7)
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extern int intel_mid_pwr_get_lss_id(struct pci_dev *pdev);
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extern int get_gpio_by_name(const char *name);
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extern void intel_scu_device_register(struct platform_device *pdev);
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extern int __init sfi_parse_mrtc(struct sfi_table_header *table);
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@ -34,13 +42,28 @@ struct devs_id {
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void *(*get_platform_data)(void *info);
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/* Custom handler for devices */
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void (*device_handler)(struct sfi_device_table_entry *pentry,
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struct devs_id *dev);
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struct devs_id *dev);
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};
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#define sfi_device(i) \
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static const struct devs_id *const __intel_mid_sfi_##i##_dev __used \
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#define sfi_device(i) \
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static const struct devs_id *const __intel_mid_sfi_##i##_dev __used \
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__attribute__((__section__(".x86_intel_mid_dev.init"))) = &i
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/**
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* struct mid_sd_board_info - template for SD device creation
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* @name: identifies the driver
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* @bus_num: board-specific identifier for a given SD controller
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* @max_clk: the maximum frequency device supports
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* @platform_data: the particular data stored there is driver-specific
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*/
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struct mid_sd_board_info {
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char name[SFI_NAME_LEN];
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int bus_num;
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unsigned short addr;
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u32 max_clk;
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void *platform_data;
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};
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/*
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* Medfield is the follow-up of Moorestown, it combines two chip solution into
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* one. Other than that it also added always-on and constant tsc and lapic
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@ -60,7 +83,7 @@ extern enum intel_mid_cpu_type __intel_mid_cpu_chip;
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/**
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* struct intel_mid_ops - Interface between intel-mid & sub archs
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* @arch_setup: arch_setup function to re-initialize platform
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* structures (x86_init, x86_platform_init)
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* structures (x86_init, x86_platform_init)
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*
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* This structure can be extended if any new interface is required
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* between intel-mid & its sub arch files.
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@ -70,20 +93,20 @@ struct intel_mid_ops {
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};
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/* Helper API's for INTEL_MID_OPS_INIT */
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#define DECLARE_INTEL_MID_OPS_INIT(cpuname, cpuid) \
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[cpuid] = get_##cpuname##_ops
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#define DECLARE_INTEL_MID_OPS_INIT(cpuname, cpuid) \
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[cpuid] = get_##cpuname##_ops
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/* Maximum number of CPU ops */
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#define MAX_CPU_OPS(a) (sizeof(a)/sizeof(void *))
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#define MAX_CPU_OPS(a) (sizeof(a)/sizeof(void *))
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/*
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* For every new cpu addition, a weak get_<cpuname>_ops() function needs be
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* declared in arch/x86/platform/intel_mid/intel_mid_weak_decls.h.
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*/
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#define INTEL_MID_OPS_INIT {\
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DECLARE_INTEL_MID_OPS_INIT(penwell, INTEL_MID_CPU_CHIP_PENWELL), \
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DECLARE_INTEL_MID_OPS_INIT(cloverview, INTEL_MID_CPU_CHIP_CLOVERVIEW), \
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DECLARE_INTEL_MID_OPS_INIT(tangier, INTEL_MID_CPU_CHIP_TANGIER) \
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#define INTEL_MID_OPS_INIT { \
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DECLARE_INTEL_MID_OPS_INIT(penwell, INTEL_MID_CPU_CHIP_PENWELL), \
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DECLARE_INTEL_MID_OPS_INIT(cloverview, INTEL_MID_CPU_CHIP_CLOVERVIEW), \
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DECLARE_INTEL_MID_OPS_INIT(tangier, INTEL_MID_CPU_CHIP_TANGIER) \
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};
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#ifdef CONFIG_X86_INTEL_MID
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@ -100,8 +123,8 @@ static inline bool intel_mid_has_msic(void)
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#else /* !CONFIG_X86_INTEL_MID */
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#define intel_mid_identify_cpu() (0)
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#define intel_mid_has_msic() (0)
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#define intel_mid_identify_cpu() 0
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#define intel_mid_has_msic() 0
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#endif /* !CONFIG_X86_INTEL_MID */
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@ -117,35 +140,38 @@ extern enum intel_mid_timer_options intel_mid_timer_options;
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* Penwell uses spread spectrum clock, so the freq number is not exactly
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* the same as reported by MSR based on SDM.
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*/
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#define FSB_FREQ_83SKU 83200
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#define FSB_FREQ_100SKU 99840
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#define FSB_FREQ_133SKU 133000
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#define FSB_FREQ_83SKU 83200
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#define FSB_FREQ_100SKU 99840
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#define FSB_FREQ_133SKU 133000
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#define FSB_FREQ_167SKU 167000
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#define FSB_FREQ_200SKU 200000
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#define FSB_FREQ_267SKU 267000
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#define FSB_FREQ_333SKU 333000
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#define FSB_FREQ_400SKU 400000
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#define FSB_FREQ_167SKU 167000
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#define FSB_FREQ_200SKU 200000
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#define FSB_FREQ_267SKU 267000
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#define FSB_FREQ_333SKU 333000
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#define FSB_FREQ_400SKU 400000
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/* Bus Select SoC Fuse value */
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#define BSEL_SOC_FUSE_MASK 0x7
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#define BSEL_SOC_FUSE_001 0x1 /* FSB 133MHz */
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#define BSEL_SOC_FUSE_101 0x5 /* FSB 100MHz */
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#define BSEL_SOC_FUSE_111 0x7 /* FSB 83MHz */
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#define BSEL_SOC_FUSE_MASK 0x7
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/* FSB 133MHz */
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#define BSEL_SOC_FUSE_001 0x1
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/* FSB 100MHz */
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#define BSEL_SOC_FUSE_101 0x5
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/* FSB 83MHz */
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#define BSEL_SOC_FUSE_111 0x7
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#define SFI_MTMR_MAX_NUM 8
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#define SFI_MRTC_MAX 8
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#define SFI_MTMR_MAX_NUM 8
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#define SFI_MRTC_MAX 8
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extern void intel_scu_devices_create(void);
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extern void intel_scu_devices_destroy(void);
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/* VRTC timer */
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#define MRST_VRTC_MAP_SZ (1024)
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/*#define MRST_VRTC_PGOFFSET (0xc00) */
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#define MRST_VRTC_MAP_SZ 1024
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/* #define MRST_VRTC_PGOFFSET 0xc00 */
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extern void intel_mid_rtc_init(void);
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/* the offset for the mapping of global gpio pin to irq */
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#define INTEL_MID_IRQ_OFFSET 0x100
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/* The offset for the mapping of global gpio pin to irq */
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#define INTEL_MID_IRQ_OFFSET 0x100
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#endif /* _ASM_X86_INTEL_MID_H */
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@ -25,16 +25,6 @@
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#ifndef _ASM_X86_TOPOLOGY_H
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#define _ASM_X86_TOPOLOGY_H
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#ifdef CONFIG_X86_32
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# ifdef CONFIG_SMP
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# define ENABLE_TOPO_DEFINES
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# endif
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#else
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# ifdef CONFIG_SMP
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# define ENABLE_TOPO_DEFINES
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# endif
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#endif
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/*
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* to preserve the visibility of NUMA_NO_NODE definition,
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* moved to there from here. May be used independent of
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@ -123,7 +113,7 @@ extern const struct cpumask *cpu_coregroup_mask(int cpu);
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#define topology_physical_package_id(cpu) (cpu_data(cpu).phys_proc_id)
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#define topology_core_id(cpu) (cpu_data(cpu).cpu_core_id)
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#ifdef ENABLE_TOPO_DEFINES
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#ifdef CONFIG_SMP
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#define topology_core_cpumask(cpu) (per_cpu(cpu_core_map, cpu))
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#define topology_sibling_cpumask(cpu) (per_cpu(cpu_sibling_map, cpu))
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@ -300,15 +300,14 @@ static void intel_workarounds(struct cpuinfo_x86 *c)
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}
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/*
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* P4 Xeon errata 037 workaround.
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* P4 Xeon erratum 037 workaround.
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* Hardware prefetcher may cause stale data to be loaded into the cache.
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*/
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if ((c->x86 == 15) && (c->x86_model == 1) && (c->x86_mask == 1)) {
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if (msr_set_bit(MSR_IA32_MISC_ENABLE,
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MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT)
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> 0) {
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MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT) > 0) {
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pr_info("CPU: C0 stepping P4 Xeon detected.\n");
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pr_info("CPU: Disabling hardware prefetching (Errata 037)\n");
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pr_info("CPU: Disabling hardware prefetching (Erratum 037)\n");
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}
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}
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@ -36,7 +36,8 @@
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#define PCIE_CAP_OFFSET 0x100
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/* Quirks for the listed devices */
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#define PCI_DEVICE_ID_INTEL_MRFL_MMC 0x1190
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#define PCI_DEVICE_ID_INTEL_MRFLD_MMC 0x1190
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#define PCI_DEVICE_ID_INTEL_MRFLD_HSU 0x1191
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/* Fixed BAR fields */
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#define PCIE_VNDR_CAP_ID_FIXED_BAR 0x00 /* Fixed BAR (TBD) */
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@ -224,14 +225,21 @@ static int intel_mid_pci_irq_enable(struct pci_dev *dev)
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/* Special treatment for IRQ0 */
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if (dev->irq == 0) {
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/*
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* Skip HS UART common registers device since it has
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* IRQ0 assigned and not used by the kernel.
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*/
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if (dev->device == PCI_DEVICE_ID_INTEL_MRFLD_HSU)
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return -EBUSY;
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/*
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* TNG has IRQ0 assigned to eMMC controller. But there
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* are also other devices with bogus PCI configuration
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* that have IRQ0 assigned. This check ensures that
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* eMMC gets it.
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* eMMC gets it. The rest of devices still could be
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* enabled without interrupt line being allocated.
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*/
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if (dev->device != PCI_DEVICE_ID_INTEL_MRFL_MMC)
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return -EBUSY;
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if (dev->device != PCI_DEVICE_ID_INTEL_MRFLD_MMC)
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return 0;
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}
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break;
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default:
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@ -308,14 +316,39 @@ static void pci_d3delay_fixup(struct pci_dev *dev)
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}
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DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_d3delay_fixup);
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static void mrst_power_off_unused_dev(struct pci_dev *dev)
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static void mid_power_off_one_device(struct pci_dev *dev)
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{
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u16 pmcsr;
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/*
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* Update current state first, otherwise PCI core enforces PCI_D0 in
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* pci_set_power_state() for devices which status was PCI_UNKNOWN.
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*/
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pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
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dev->current_state = (pci_power_t __force)(pmcsr & PCI_PM_CTRL_STATE_MASK);
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pci_set_power_state(dev, PCI_D3hot);
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}
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DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0801, mrst_power_off_unused_dev);
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DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0809, mrst_power_off_unused_dev);
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DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x080C, mrst_power_off_unused_dev);
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DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0815, mrst_power_off_unused_dev);
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static void mid_power_off_devices(struct pci_dev *dev)
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{
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int id;
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if (!pci_soc_mode)
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return;
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id = intel_mid_pwr_get_lss_id(dev);
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if (id < 0)
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return;
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/*
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* This sets only PMCSR bits. The actual power off will happen in
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* arch/x86/platform/intel-mid/pwr.c.
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*/
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mid_power_off_one_device(dev);
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}
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DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, mid_power_off_devices);
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/*
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* Langwell devices reside at fixed offsets, don't try to move them.
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@ -23,10 +23,9 @@
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#include <linux/seq_file.h>
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#include <linux/io.h>
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#include <asm/cpu_device_id.h>
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#include <asm/intel-family.h>
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#include <asm/iosf_mbi.h>
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/* Power gate status reg */
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#define PWRGT_STATUS 0x61
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/* Subsystem config/status Video processor */
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#define VED_SS_PM0 0x32
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/* Subsystem config/status ISP (Image Signal Processor) */
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@ -35,12 +34,16 @@
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#define MIO_SS_PM 0x3B
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/* Shift bits for getting status for video, isp and i/o */
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#define SSS_SHIFT 24
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/* Power gate status reg */
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#define PWRGT_STATUS 0x61
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/* Shift bits for getting status for graphics rendering */
|
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#define RENDER_POS 0
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/* Shift bits for getting status for media control */
|
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#define MEDIA_POS 2
|
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/* Shift bits for getting status for Valley View/Baytrail display */
|
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#define VLV_DISPLAY_POS 6
|
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|
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/* Subsystem config/status display for Cherry Trail SOC */
|
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#define CHT_DSP_SSS 0x36
|
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/* Shift bits for getting status for display */
|
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@ -52,6 +55,14 @@ struct punit_device {
|
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int sss_pos;
|
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};
|
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|
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static const struct punit_device punit_device_tng[] = {
|
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{ "DISPLAY", CHT_DSP_SSS, SSS_SHIFT },
|
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{ "VED", VED_SS_PM0, SSS_SHIFT },
|
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{ "ISP", ISP_SS_PM0, SSS_SHIFT },
|
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{ "MIO", MIO_SS_PM, SSS_SHIFT },
|
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{ NULL }
|
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};
|
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|
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static const struct punit_device punit_device_byt[] = {
|
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{ "GFX RENDER", PWRGT_STATUS, RENDER_POS },
|
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{ "GFX MEDIA", PWRGT_STATUS, MEDIA_POS },
|
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@ -143,8 +154,9 @@ static void punit_dbgfs_unregister(void)
|
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(kernel_ulong_t)&drv_data }
|
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|
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static const struct x86_cpu_id intel_punit_cpu_ids[] = {
|
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ICPU(55, punit_device_byt), /* Valleyview, Bay Trail */
|
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ICPU(76, punit_device_cht), /* Braswell, Cherry Trail */
|
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ICPU(INTEL_FAM6_ATOM_SILVERMONT1, punit_device_byt),
|
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ICPU(INTEL_FAM6_ATOM_MERRIFIELD1, punit_device_tng),
|
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ICPU(INTEL_FAM6_ATOM_AIRMONT, punit_device_cht),
|
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{}
|
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};
|
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|
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|
||||
@ -1,4 +1,4 @@
|
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obj-$(CONFIG_X86_INTEL_MID) += intel-mid.o intel_mid_vrtc.o mfld.o mrfl.o
|
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obj-$(CONFIG_X86_INTEL_MID) += intel-mid.o intel_mid_vrtc.o mfld.o mrfld.o pwr.o
|
||||
|
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# SFI specific code
|
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ifdef CONFIG_X86_INTEL_MID
|
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|
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@ -1,3 +1,5 @@
|
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# Family-Level Interface Shim (FLIS)
|
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obj-$(subst m,y,$(CONFIG_PINCTRL_MERRIFIELD)) += platform_mrfld_pinctrl.o
|
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# IPC Devices
|
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obj-y += platform_ipc.o
|
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obj-$(subst m,y,$(CONFIG_MFD_INTEL_MSIC)) += platform_msic.o
|
||||
@ -8,14 +10,18 @@ obj-$(subst m,y,$(CONFIG_MFD_INTEL_MSIC)) += platform_msic_battery.o
|
||||
obj-$(subst m,y,$(CONFIG_INTEL_MID_POWER_BUTTON)) += platform_msic_power_btn.o
|
||||
obj-$(subst m,y,$(CONFIG_GPIO_INTEL_PMIC)) += platform_pmic_gpio.o
|
||||
obj-$(subst m,y,$(CONFIG_INTEL_MFLD_THERMAL)) += platform_msic_thermal.o
|
||||
# SPI Devices
|
||||
obj-$(subst m,y,$(CONFIG_SPI_SPIDEV)) += platform_spidev.o
|
||||
# I2C Devices
|
||||
obj-$(subst m,y,$(CONFIG_SENSORS_EMC1403)) += platform_emc1403.o
|
||||
obj-$(subst m,y,$(CONFIG_SENSORS_LIS3LV02D)) += platform_lis331.o
|
||||
obj-$(subst m,y,$(CONFIG_GPIO_PCA953X)) += platform_max7315.o
|
||||
obj-$(subst m,y,$(CONFIG_INPUT_MPU3050)) += platform_mpu3050.o
|
||||
obj-$(subst m,y,$(CONFIG_INPUT_BMA150)) += platform_bma023.o
|
||||
obj-$(subst m,y,$(CONFIG_GPIO_PCA953X)) += platform_tca6416.o
|
||||
obj-$(subst m,y,$(CONFIG_DRM_MEDFIELD)) += platform_tc35876x.o
|
||||
# I2C GPIO Expanders
|
||||
obj-$(subst m,y,$(CONFIG_GPIO_PCA953X)) += platform_max7315.o
|
||||
obj-$(subst m,y,$(CONFIG_GPIO_PCA953X)) += platform_pcal9555a.o
|
||||
obj-$(subst m,y,$(CONFIG_GPIO_PCA953X)) += platform_tca6416.o
|
||||
# MISC Devices
|
||||
obj-$(subst m,y,$(CONFIG_KEYBOARD_GPIO)) += platform_gpio_keys.o
|
||||
obj-$(subst m,y,$(CONFIG_INTEL_MID_WATCHDOG)) += platform_wdt.o
|
||||
|
||||
@ -0,0 +1,43 @@
|
||||
/*
|
||||
* Intel Merrifield FLIS platform device initialization file
|
||||
*
|
||||
* Copyright (C) 2016, Intel Corporation
|
||||
*
|
||||
* Author: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation; version 2
|
||||
* of the License.
|
||||
*/
|
||||
|
||||
#include <linux/init.h>
|
||||
#include <linux/ioport.h>
|
||||
#include <linux/platform_device.h>
|
||||
|
||||
#include <asm/intel-mid.h>
|
||||
|
||||
#define FLIS_BASE_ADDR 0xff0c0000
|
||||
#define FLIS_LENGTH 0x8000
|
||||
|
||||
static struct resource mrfld_pinctrl_mmio_resource = {
|
||||
.start = FLIS_BASE_ADDR,
|
||||
.end = FLIS_BASE_ADDR + FLIS_LENGTH - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
};
|
||||
|
||||
static struct platform_device mrfld_pinctrl_device = {
|
||||
.name = "pinctrl-merrifield",
|
||||
.id = PLATFORM_DEVID_NONE,
|
||||
.resource = &mrfld_pinctrl_mmio_resource,
|
||||
.num_resources = 1,
|
||||
};
|
||||
|
||||
static int __init mrfld_pinctrl_init(void)
|
||||
{
|
||||
if (intel_mid_identify_cpu() == INTEL_MID_CPU_CHIP_TANGIER)
|
||||
return platform_device_register(&mrfld_pinctrl_device);
|
||||
|
||||
return -ENODEV;
|
||||
}
|
||||
arch_initcall(mrfld_pinctrl_init);
|
||||
99
arch/x86/platform/intel-mid/device_libs/platform_pcal9555a.c
Normal file
99
arch/x86/platform/intel-mid/device_libs/platform_pcal9555a.c
Normal file
@ -0,0 +1,99 @@
|
||||
/*
|
||||
* PCAL9555a platform data initilization file
|
||||
*
|
||||
* Copyright (C) 2016, Intel Corporation
|
||||
*
|
||||
* Authors: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
|
||||
* Dan O'Donovan <dan@emutex.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation; version 2
|
||||
* of the License.
|
||||
*/
|
||||
|
||||
#include <linux/gpio.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/i2c.h>
|
||||
#include <linux/platform_data/pca953x.h>
|
||||
#include <linux/sfi.h>
|
||||
|
||||
#include <asm/intel-mid.h>
|
||||
|
||||
#define PCAL9555A_NUM 4
|
||||
|
||||
static struct pca953x_platform_data pcal9555a_pdata[PCAL9555A_NUM];
|
||||
static int nr;
|
||||
|
||||
static void __init *pcal9555a_platform_data(void *info)
|
||||
{
|
||||
struct i2c_board_info *i2c_info = info;
|
||||
char *type = i2c_info->type;
|
||||
struct pca953x_platform_data *pcal9555a;
|
||||
char base_pin_name[SFI_NAME_LEN + 1];
|
||||
char intr_pin_name[SFI_NAME_LEN + 1];
|
||||
int gpio_base, intr;
|
||||
|
||||
snprintf(base_pin_name, sizeof(base_pin_name), "%s_base", type);
|
||||
snprintf(intr_pin_name, sizeof(intr_pin_name), "%s_int", type);
|
||||
|
||||
gpio_base = get_gpio_by_name(base_pin_name);
|
||||
intr = get_gpio_by_name(intr_pin_name);
|
||||
|
||||
/* Check if the SFI record valid */
|
||||
if (gpio_base == -1)
|
||||
return NULL;
|
||||
|
||||
if (nr >= PCAL9555A_NUM) {
|
||||
pr_err("%s: Too many instances, only %d supported\n", __func__,
|
||||
PCAL9555A_NUM);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
pcal9555a = &pcal9555a_pdata[nr++];
|
||||
pcal9555a->gpio_base = gpio_base;
|
||||
|
||||
if (intr >= 0) {
|
||||
i2c_info->irq = intr + INTEL_MID_IRQ_OFFSET;
|
||||
pcal9555a->irq_base = gpio_base + INTEL_MID_IRQ_OFFSET;
|
||||
} else {
|
||||
i2c_info->irq = -1;
|
||||
pcal9555a->irq_base = -1;
|
||||
}
|
||||
|
||||
strcpy(type, "pcal9555a");
|
||||
return pcal9555a;
|
||||
}
|
||||
|
||||
static const struct devs_id pcal9555a_1_dev_id __initconst = {
|
||||
.name = "pcal9555a-1",
|
||||
.type = SFI_DEV_TYPE_I2C,
|
||||
.delay = 1,
|
||||
.get_platform_data = &pcal9555a_platform_data,
|
||||
};
|
||||
|
||||
static const struct devs_id pcal9555a_2_dev_id __initconst = {
|
||||
.name = "pcal9555a-2",
|
||||
.type = SFI_DEV_TYPE_I2C,
|
||||
.delay = 1,
|
||||
.get_platform_data = &pcal9555a_platform_data,
|
||||
};
|
||||
|
||||
static const struct devs_id pcal9555a_3_dev_id __initconst = {
|
||||
.name = "pcal9555a-3",
|
||||
.type = SFI_DEV_TYPE_I2C,
|
||||
.delay = 1,
|
||||
.get_platform_data = &pcal9555a_platform_data,
|
||||
};
|
||||
|
||||
static const struct devs_id pcal9555a_4_dev_id __initconst = {
|
||||
.name = "pcal9555a-4",
|
||||
.type = SFI_DEV_TYPE_I2C,
|
||||
.delay = 1,
|
||||
.get_platform_data = &pcal9555a_platform_data,
|
||||
};
|
||||
|
||||
sfi_device(pcal9555a_1_dev_id);
|
||||
sfi_device(pcal9555a_2_dev_id);
|
||||
sfi_device(pcal9555a_3_dev_id);
|
||||
sfi_device(pcal9555a_4_dev_id);
|
||||
50
arch/x86/platform/intel-mid/device_libs/platform_spidev.c
Normal file
50
arch/x86/platform/intel-mid/device_libs/platform_spidev.c
Normal file
@ -0,0 +1,50 @@
|
||||
/*
|
||||
* spidev platform data initilization file
|
||||
*
|
||||
* (C) Copyright 2014, 2016 Intel Corporation
|
||||
* Authors: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
|
||||
* Dan O'Donovan <dan@emutex.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation; version 2
|
||||
* of the License.
|
||||
*/
|
||||
|
||||
#include <linux/init.h>
|
||||
#include <linux/sfi.h>
|
||||
#include <linux/spi/pxa2xx_spi.h>
|
||||
#include <linux/spi/spi.h>
|
||||
|
||||
#include <asm/intel-mid.h>
|
||||
|
||||
#define MRFLD_SPI_DEFAULT_DMA_BURST 8
|
||||
#define MRFLD_SPI_DEFAULT_TIMEOUT 500
|
||||
|
||||
/* GPIO pin for spidev chipselect */
|
||||
#define MRFLD_SPIDEV_GPIO_CS 111
|
||||
|
||||
static struct pxa2xx_spi_chip spidev_spi_chip = {
|
||||
.dma_burst_size = MRFLD_SPI_DEFAULT_DMA_BURST,
|
||||
.timeout = MRFLD_SPI_DEFAULT_TIMEOUT,
|
||||
.gpio_cs = MRFLD_SPIDEV_GPIO_CS,
|
||||
};
|
||||
|
||||
static void __init *spidev_platform_data(void *info)
|
||||
{
|
||||
struct spi_board_info *spi_info = info;
|
||||
|
||||
spi_info->mode = SPI_MODE_0;
|
||||
spi_info->controller_data = &spidev_spi_chip;
|
||||
|
||||
return NULL;
|
||||
}
|
||||
|
||||
static const struct devs_id spidev_dev_id __initconst = {
|
||||
.name = "spidev",
|
||||
.type = SFI_DEV_TYPE_SPI,
|
||||
.delay = 0,
|
||||
.get_platform_data = &spidev_platform_data,
|
||||
};
|
||||
|
||||
sfi_device(spidev_dev_id);
|
||||
@ -16,6 +16,7 @@
|
||||
#include <linux/init.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/regulator/machine.h>
|
||||
#include <linux/scatterlist.h>
|
||||
#include <linux/sfi.h>
|
||||
#include <linux/irq.h>
|
||||
@ -144,6 +145,15 @@ static void intel_mid_arch_setup(void)
|
||||
out:
|
||||
if (intel_mid_ops->arch_setup)
|
||||
intel_mid_ops->arch_setup();
|
||||
|
||||
/*
|
||||
* Intel MID platforms are using explicitly defined regulators.
|
||||
*
|
||||
* Let the regulator core know that we do not have any additional
|
||||
* regulators left. This lets it substitute unprovided regulators with
|
||||
* dummy ones:
|
||||
*/
|
||||
regulator_has_full_constraints();
|
||||
}
|
||||
|
||||
/* MID systems don't have i8042 controller */
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
/*
|
||||
* mrfl.c: Intel Merrifield platform specific setup code
|
||||
* Intel Merrifield platform specific setup code
|
||||
*
|
||||
* (C) Copyright 2013 Intel Corporation
|
||||
*
|
||||
418
arch/x86/platform/intel-mid/pwr.c
Normal file
418
arch/x86/platform/intel-mid/pwr.c
Normal file
@ -0,0 +1,418 @@
|
||||
/*
|
||||
* Intel MID Power Management Unit (PWRMU) device driver
|
||||
*
|
||||
* Copyright (C) 2016, Intel Corporation
|
||||
*
|
||||
* Author: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* Intel MID Power Management Unit device driver handles the South Complex PCI
|
||||
* devices such as GPDMA, SPI, I2C, PWM, and so on. By default PCI core
|
||||
* modifies bits in PMCSR register in the PCI configuration space. This is not
|
||||
* enough on some SoCs like Intel Tangier. In such case PCI core sets a new
|
||||
* power state of the device in question through a PM hook registered in struct
|
||||
* pci_platform_pm_ops (see drivers/pci/pci-mid.c).
|
||||
*/
|
||||
|
||||
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
|
||||
|
||||
#include <linux/delay.h>
|
||||
#include <linux/errno.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/mutex.h>
|
||||
#include <linux/pci.h>
|
||||
|
||||
#include <asm/intel-mid.h>
|
||||
|
||||
/* Registers */
|
||||
#define PM_STS 0x00
|
||||
#define PM_CMD 0x04
|
||||
#define PM_ICS 0x08
|
||||
#define PM_WKC(x) (0x10 + (x) * 4)
|
||||
#define PM_WKS(x) (0x18 + (x) * 4)
|
||||
#define PM_SSC(x) (0x20 + (x) * 4)
|
||||
#define PM_SSS(x) (0x30 + (x) * 4)
|
||||
|
||||
/* Bits in PM_STS */
|
||||
#define PM_STS_BUSY (1 << 8)
|
||||
|
||||
/* Bits in PM_CMD */
|
||||
#define PM_CMD_CMD(x) ((x) << 0)
|
||||
#define PM_CMD_IOC (1 << 8)
|
||||
#define PM_CMD_D3cold (1 << 21)
|
||||
|
||||
/* List of commands */
|
||||
#define CMD_SET_CFG 0x01
|
||||
|
||||
/* Bits in PM_ICS */
|
||||
#define PM_ICS_INT_STATUS(x) ((x) & 0xff)
|
||||
#define PM_ICS_IE (1 << 8)
|
||||
#define PM_ICS_IP (1 << 9)
|
||||
#define PM_ICS_SW_INT_STS (1 << 10)
|
||||
|
||||
/* List of interrupts */
|
||||
#define INT_INVALID 0
|
||||
#define INT_CMD_COMPLETE 1
|
||||
#define INT_CMD_ERR 2
|
||||
#define INT_WAKE_EVENT 3
|
||||
#define INT_LSS_POWER_ERR 4
|
||||
#define INT_S0iX_MSG_ERR 5
|
||||
#define INT_NO_C6 6
|
||||
#define INT_TRIGGER_ERR 7
|
||||
#define INT_INACTIVITY 8
|
||||
|
||||
/* South Complex devices */
|
||||
#define LSS_MAX_SHARED_DEVS 4
|
||||
#define LSS_MAX_DEVS 64
|
||||
|
||||
#define LSS_WS_BITS 1 /* wake state width */
|
||||
#define LSS_PWS_BITS 2 /* power state width */
|
||||
|
||||
/* Supported device IDs */
|
||||
#define PCI_DEVICE_ID_PENWELL 0x0828
|
||||
#define PCI_DEVICE_ID_TANGIER 0x11a1
|
||||
|
||||
struct mid_pwr_dev {
|
||||
struct pci_dev *pdev;
|
||||
pci_power_t state;
|
||||
};
|
||||
|
||||
struct mid_pwr {
|
||||
struct device *dev;
|
||||
void __iomem *regs;
|
||||
int irq;
|
||||
bool available;
|
||||
|
||||
struct mutex lock;
|
||||
struct mid_pwr_dev lss[LSS_MAX_DEVS][LSS_MAX_SHARED_DEVS];
|
||||
};
|
||||
|
||||
static struct mid_pwr *midpwr;
|
||||
|
||||
static u32 mid_pwr_get_state(struct mid_pwr *pwr, int reg)
|
||||
{
|
||||
return readl(pwr->regs + PM_SSS(reg));
|
||||
}
|
||||
|
||||
static void mid_pwr_set_state(struct mid_pwr *pwr, int reg, u32 value)
|
||||
{
|
||||
writel(value, pwr->regs + PM_SSC(reg));
|
||||
}
|
||||
|
||||
static void mid_pwr_set_wake(struct mid_pwr *pwr, int reg, u32 value)
|
||||
{
|
||||
writel(value, pwr->regs + PM_WKC(reg));
|
||||
}
|
||||
|
||||
static void mid_pwr_interrupt_disable(struct mid_pwr *pwr)
|
||||
{
|
||||
writel(~PM_ICS_IE, pwr->regs + PM_ICS);
|
||||
}
|
||||
|
||||
static bool mid_pwr_is_busy(struct mid_pwr *pwr)
|
||||
{
|
||||
return !!(readl(pwr->regs + PM_STS) & PM_STS_BUSY);
|
||||
}
|
||||
|
||||
/* Wait 500ms that the latest PWRMU command finished */
|
||||
static int mid_pwr_wait(struct mid_pwr *pwr)
|
||||
{
|
||||
unsigned int count = 500000;
|
||||
bool busy;
|
||||
|
||||
do {
|
||||
busy = mid_pwr_is_busy(pwr);
|
||||
if (!busy)
|
||||
return 0;
|
||||
udelay(1);
|
||||
} while (--count);
|
||||
|
||||
return -EBUSY;
|
||||
}
|
||||
|
||||
static int mid_pwr_wait_for_cmd(struct mid_pwr *pwr, u8 cmd)
|
||||
{
|
||||
writel(PM_CMD_CMD(cmd), pwr->regs + PM_CMD);
|
||||
return mid_pwr_wait(pwr);
|
||||
}
|
||||
|
||||
static int __update_power_state(struct mid_pwr *pwr, int reg, int bit, int new)
|
||||
{
|
||||
int curstate;
|
||||
u32 power;
|
||||
int ret;
|
||||
|
||||
/* Check if the device is already in desired state */
|
||||
power = mid_pwr_get_state(pwr, reg);
|
||||
curstate = (power >> bit) & 3;
|
||||
if (curstate == new)
|
||||
return 0;
|
||||
|
||||
/* Update the power state */
|
||||
mid_pwr_set_state(pwr, reg, (power & ~(3 << bit)) | (new << bit));
|
||||
|
||||
/* Send command to SCU */
|
||||
ret = mid_pwr_wait_for_cmd(pwr, CMD_SET_CFG);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
/* Check if the device is already in desired state */
|
||||
power = mid_pwr_get_state(pwr, reg);
|
||||
curstate = (power >> bit) & 3;
|
||||
if (curstate != new)
|
||||
return -EAGAIN;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static pci_power_t __find_weakest_power_state(struct mid_pwr_dev *lss,
|
||||
struct pci_dev *pdev,
|
||||
pci_power_t state)
|
||||
{
|
||||
pci_power_t weakest = PCI_D3hot;
|
||||
unsigned int j;
|
||||
|
||||
/* Find device in cache or first free cell */
|
||||
for (j = 0; j < LSS_MAX_SHARED_DEVS; j++) {
|
||||
if (lss[j].pdev == pdev || !lss[j].pdev)
|
||||
break;
|
||||
}
|
||||
|
||||
/* Store the desired state in cache */
|
||||
if (j < LSS_MAX_SHARED_DEVS) {
|
||||
lss[j].pdev = pdev;
|
||||
lss[j].state = state;
|
||||
} else {
|
||||
dev_WARN(&pdev->dev, "No room for device in PWRMU LSS cache\n");
|
||||
weakest = state;
|
||||
}
|
||||
|
||||
/* Find the power state we may use */
|
||||
for (j = 0; j < LSS_MAX_SHARED_DEVS; j++) {
|
||||
if (lss[j].state < weakest)
|
||||
weakest = lss[j].state;
|
||||
}
|
||||
|
||||
return weakest;
|
||||
}
|
||||
|
||||
static int __set_power_state(struct mid_pwr *pwr, struct pci_dev *pdev,
|
||||
pci_power_t state, int id, int reg, int bit)
|
||||
{
|
||||
const char *name;
|
||||
int ret;
|
||||
|
||||
state = __find_weakest_power_state(pwr->lss[id], pdev, state);
|
||||
name = pci_power_name(state);
|
||||
|
||||
ret = __update_power_state(pwr, reg, bit, (__force int)state);
|
||||
if (ret) {
|
||||
dev_warn(&pdev->dev, "Can't set power state %s: %d\n", name, ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
dev_vdbg(&pdev->dev, "Set power state %s\n", name);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int mid_pwr_set_power_state(struct mid_pwr *pwr, struct pci_dev *pdev,
|
||||
pci_power_t state)
|
||||
{
|
||||
int id, reg, bit;
|
||||
int ret;
|
||||
|
||||
id = intel_mid_pwr_get_lss_id(pdev);
|
||||
if (id < 0)
|
||||
return id;
|
||||
|
||||
reg = (id * LSS_PWS_BITS) / 32;
|
||||
bit = (id * LSS_PWS_BITS) % 32;
|
||||
|
||||
/* We support states between PCI_D0 and PCI_D3hot */
|
||||
if (state < PCI_D0)
|
||||
state = PCI_D0;
|
||||
if (state > PCI_D3hot)
|
||||
state = PCI_D3hot;
|
||||
|
||||
mutex_lock(&pwr->lock);
|
||||
ret = __set_power_state(pwr, pdev, state, id, reg, bit);
|
||||
mutex_unlock(&pwr->lock);
|
||||
return ret;
|
||||
}
|
||||
|
||||
int intel_mid_pci_set_power_state(struct pci_dev *pdev, pci_power_t state)
|
||||
{
|
||||
struct mid_pwr *pwr = midpwr;
|
||||
int ret = 0;
|
||||
|
||||
might_sleep();
|
||||
|
||||
if (pwr && pwr->available)
|
||||
ret = mid_pwr_set_power_state(pwr, pdev, state);
|
||||
dev_vdbg(&pdev->dev, "set_power_state() returns %d\n", ret);
|
||||
|
||||
return 0;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(intel_mid_pci_set_power_state);
|
||||
|
||||
int intel_mid_pwr_get_lss_id(struct pci_dev *pdev)
|
||||
{
|
||||
int vndr;
|
||||
u8 id;
|
||||
|
||||
/*
|
||||
* Mapping to PWRMU index is kept in the Logical SubSystem ID byte of
|
||||
* Vendor capability.
|
||||
*/
|
||||
vndr = pci_find_capability(pdev, PCI_CAP_ID_VNDR);
|
||||
if (!vndr)
|
||||
return -EINVAL;
|
||||
|
||||
/* Read the Logical SubSystem ID byte */
|
||||
pci_read_config_byte(pdev, vndr + INTEL_MID_PWR_LSS_OFFSET, &id);
|
||||
if (!(id & INTEL_MID_PWR_LSS_TYPE))
|
||||
return -ENODEV;
|
||||
|
||||
id &= ~INTEL_MID_PWR_LSS_TYPE;
|
||||
if (id >= LSS_MAX_DEVS)
|
||||
return -ERANGE;
|
||||
|
||||
return id;
|
||||
}
|
||||
|
||||
static irqreturn_t mid_pwr_irq_handler(int irq, void *dev_id)
|
||||
{
|
||||
struct mid_pwr *pwr = dev_id;
|
||||
u32 ics;
|
||||
|
||||
ics = readl(pwr->regs + PM_ICS);
|
||||
if (!(ics & PM_ICS_IP))
|
||||
return IRQ_NONE;
|
||||
|
||||
writel(ics | PM_ICS_IP, pwr->regs + PM_ICS);
|
||||
|
||||
dev_warn(pwr->dev, "Unexpected IRQ: %#x\n", PM_ICS_INT_STATUS(ics));
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
struct mid_pwr_device_info {
|
||||
int (*set_initial_state)(struct mid_pwr *pwr);
|
||||
};
|
||||
|
||||
static int mid_pwr_probe(struct pci_dev *pdev, const struct pci_device_id *id)
|
||||
{
|
||||
struct mid_pwr_device_info *info = (void *)id->driver_data;
|
||||
struct device *dev = &pdev->dev;
|
||||
struct mid_pwr *pwr;
|
||||
int ret;
|
||||
|
||||
ret = pcim_enable_device(pdev);
|
||||
if (ret < 0) {
|
||||
dev_err(&pdev->dev, "error: could not enable device\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = pcim_iomap_regions(pdev, 1 << 0, pci_name(pdev));
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "I/O memory remapping failed\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
pwr = devm_kzalloc(dev, sizeof(*pwr), GFP_KERNEL);
|
||||
if (!pwr)
|
||||
return -ENOMEM;
|
||||
|
||||
pwr->dev = dev;
|
||||
pwr->regs = pcim_iomap_table(pdev)[0];
|
||||
pwr->irq = pdev->irq;
|
||||
|
||||
mutex_init(&pwr->lock);
|
||||
|
||||
/* Disable interrupts */
|
||||
mid_pwr_interrupt_disable(pwr);
|
||||
|
||||
if (info && info->set_initial_state) {
|
||||
ret = info->set_initial_state(pwr);
|
||||
if (ret)
|
||||
dev_warn(dev, "Can't set initial state: %d\n", ret);
|
||||
}
|
||||
|
||||
ret = devm_request_irq(dev, pdev->irq, mid_pwr_irq_handler,
|
||||
IRQF_NO_SUSPEND, pci_name(pdev), pwr);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
pwr->available = true;
|
||||
midpwr = pwr;
|
||||
|
||||
pci_set_drvdata(pdev, pwr);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int mid_set_initial_state(struct mid_pwr *pwr)
|
||||
{
|
||||
unsigned int i, j;
|
||||
int ret;
|
||||
|
||||
/*
|
||||
* Enable wake events.
|
||||
*
|
||||
* PWRMU supports up to 32 sources for wake up the system. Ungate them
|
||||
* all here.
|
||||
*/
|
||||
mid_pwr_set_wake(pwr, 0, 0xffffffff);
|
||||
mid_pwr_set_wake(pwr, 1, 0xffffffff);
|
||||
|
||||
/*
|
||||
* Power off South Complex devices.
|
||||
*
|
||||
* There is a map (see a note below) of 64 devices with 2 bits per each
|
||||
* on 32-bit HW registers. The following calls set all devices to one
|
||||
* known initial state, i.e. PCI_D3hot. This is done in conjunction
|
||||
* with PMCSR setting in arch/x86/pci/intel_mid_pci.c.
|
||||
*
|
||||
* NOTE: The actual device mapping is provided by a platform at run
|
||||
* time using vendor capability of PCI configuration space.
|
||||
*/
|
||||
mid_pwr_set_state(pwr, 0, 0xffffffff);
|
||||
mid_pwr_set_state(pwr, 1, 0xffffffff);
|
||||
mid_pwr_set_state(pwr, 2, 0xffffffff);
|
||||
mid_pwr_set_state(pwr, 3, 0xffffffff);
|
||||
|
||||
/* Send command to SCU */
|
||||
ret = mid_pwr_wait_for_cmd(pwr, CMD_SET_CFG);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
for (i = 0; i < LSS_MAX_DEVS; i++) {
|
||||
for (j = 0; j < LSS_MAX_SHARED_DEVS; j++)
|
||||
pwr->lss[i][j].state = PCI_D3hot;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct mid_pwr_device_info mid_info = {
|
||||
.set_initial_state = mid_set_initial_state,
|
||||
};
|
||||
|
||||
static const struct pci_device_id mid_pwr_pci_ids[] = {
|
||||
{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_PENWELL), (kernel_ulong_t)&mid_info },
|
||||
{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_TANGIER), (kernel_ulong_t)&mid_info },
|
||||
{}
|
||||
};
|
||||
MODULE_DEVICE_TABLE(pci, mid_pwr_pci_ids);
|
||||
|
||||
static struct pci_driver mid_pwr_pci_driver = {
|
||||
.name = "intel_mid_pwr",
|
||||
.probe = mid_pwr_probe,
|
||||
.id_table = mid_pwr_pci_ids,
|
||||
};
|
||||
|
||||
builtin_pci_driver(mid_pwr_pci_driver);
|
||||
@ -407,6 +407,32 @@ static void __init sfi_handle_i2c_dev(struct sfi_device_table_entry *pentry,
|
||||
i2c_register_board_info(pentry->host_num, &i2c_info, 1);
|
||||
}
|
||||
|
||||
static void __init sfi_handle_sd_dev(struct sfi_device_table_entry *pentry,
|
||||
struct devs_id *dev)
|
||||
{
|
||||
struct mid_sd_board_info sd_info;
|
||||
void *pdata;
|
||||
|
||||
memset(&sd_info, 0, sizeof(sd_info));
|
||||
strncpy(sd_info.name, pentry->name, SFI_NAME_LEN);
|
||||
sd_info.bus_num = pentry->host_num;
|
||||
sd_info.max_clk = pentry->max_freq;
|
||||
sd_info.addr = pentry->addr;
|
||||
pr_debug("SD bus = %d, name = %16.16s, max_clk = %d, addr = 0x%x\n",
|
||||
sd_info.bus_num,
|
||||
sd_info.name,
|
||||
sd_info.max_clk,
|
||||
sd_info.addr);
|
||||
pdata = intel_mid_sfi_get_pdata(dev, &sd_info);
|
||||
if (IS_ERR(pdata))
|
||||
return;
|
||||
|
||||
/* Nothing we can do with this for now */
|
||||
sd_info.platform_data = pdata;
|
||||
|
||||
pr_debug("Successfully registered %16.16s", sd_info.name);
|
||||
}
|
||||
|
||||
extern struct devs_id *const __x86_intel_mid_dev_start[],
|
||||
*const __x86_intel_mid_dev_end[];
|
||||
|
||||
@ -490,6 +516,9 @@ static int __init sfi_parse_devs(struct sfi_table_header *table)
|
||||
case SFI_DEV_TYPE_I2C:
|
||||
sfi_handle_i2c_dev(pentry, dev);
|
||||
break;
|
||||
case SFI_DEV_TYPE_SD:
|
||||
sfi_handle_sd_dev(pentry, dev);
|
||||
break;
|
||||
case SFI_DEV_TYPE_UART:
|
||||
case SFI_DEV_TYPE_HSI:
|
||||
default:
|
||||
|
||||
@ -29,6 +29,7 @@ ACPI_MODULE_NAME("acpi_lpss");
|
||||
#ifdef CONFIG_X86_INTEL_LPSS
|
||||
|
||||
#include <asm/cpu_device_id.h>
|
||||
#include <asm/intel-family.h>
|
||||
#include <asm/iosf_mbi.h>
|
||||
#include <asm/pmc_atom.h>
|
||||
|
||||
@ -229,8 +230,8 @@ static const struct lpss_device_desc bsw_spi_dev_desc = {
|
||||
#define ICPU(model) { X86_VENDOR_INTEL, 6, model, X86_FEATURE_ANY, }
|
||||
|
||||
static const struct x86_cpu_id lpss_cpu_ids[] = {
|
||||
ICPU(0x37), /* Valleyview, Bay Trail */
|
||||
ICPU(0x4c), /* Braswell, Cherry Trail */
|
||||
ICPU(INTEL_FAM6_ATOM_SILVERMONT1), /* Valleyview, Bay Trail */
|
||||
ICPU(INTEL_FAM6_ATOM_AIRMONT), /* Braswell, Cherry Trail */
|
||||
{}
|
||||
};
|
||||
|
||||
|
||||
@ -35,6 +35,7 @@
|
||||
#include <asm/msr.h>
|
||||
#include <asm/cpu_device_id.h>
|
||||
#include <asm/cpufeature.h>
|
||||
#include <asm/intel-family.h>
|
||||
|
||||
#define ATOM_RATIOS 0x66a
|
||||
#define ATOM_VIDS 0x66b
|
||||
@ -1334,29 +1335,29 @@ static void intel_pstate_update_util(struct update_util_data *data, u64 time,
|
||||
(unsigned long)&policy }
|
||||
|
||||
static const struct x86_cpu_id intel_pstate_cpu_ids[] = {
|
||||
ICPU(0x2a, core_params),
|
||||
ICPU(0x2d, core_params),
|
||||
ICPU(0x37, silvermont_params),
|
||||
ICPU(0x3a, core_params),
|
||||
ICPU(0x3c, core_params),
|
||||
ICPU(0x3d, core_params),
|
||||
ICPU(0x3e, core_params),
|
||||
ICPU(0x3f, core_params),
|
||||
ICPU(0x45, core_params),
|
||||
ICPU(0x46, core_params),
|
||||
ICPU(0x47, core_params),
|
||||
ICPU(0x4c, airmont_params),
|
||||
ICPU(0x4e, core_params),
|
||||
ICPU(0x4f, core_params),
|
||||
ICPU(0x5e, core_params),
|
||||
ICPU(0x56, core_params),
|
||||
ICPU(0x57, knl_params),
|
||||
ICPU(INTEL_FAM6_SANDYBRIDGE, core_params),
|
||||
ICPU(INTEL_FAM6_SANDYBRIDGE_X, core_params),
|
||||
ICPU(INTEL_FAM6_ATOM_SILVERMONT1, silvermont_params),
|
||||
ICPU(INTEL_FAM6_IVYBRIDGE, core_params),
|
||||
ICPU(INTEL_FAM6_HASWELL_CORE, core_params),
|
||||
ICPU(INTEL_FAM6_BROADWELL_CORE, core_params),
|
||||
ICPU(INTEL_FAM6_IVYBRIDGE_X, core_params),
|
||||
ICPU(INTEL_FAM6_HASWELL_X, core_params),
|
||||
ICPU(INTEL_FAM6_HASWELL_ULT, core_params),
|
||||
ICPU(INTEL_FAM6_HASWELL_GT3E, core_params),
|
||||
ICPU(INTEL_FAM6_BROADWELL_GT3E, core_params),
|
||||
ICPU(INTEL_FAM6_ATOM_AIRMONT, airmont_params),
|
||||
ICPU(INTEL_FAM6_SKYLAKE_MOBILE, core_params),
|
||||
ICPU(INTEL_FAM6_BROADWELL_X, core_params),
|
||||
ICPU(INTEL_FAM6_SKYLAKE_DESKTOP, core_params),
|
||||
ICPU(INTEL_FAM6_BROADWELL_XEON_D, core_params),
|
||||
ICPU(INTEL_FAM6_XEON_PHI_KNL, knl_params),
|
||||
{}
|
||||
};
|
||||
MODULE_DEVICE_TABLE(x86cpu, intel_pstate_cpu_ids);
|
||||
|
||||
static const struct x86_cpu_id intel_pstate_cpu_oob_ids[] = {
|
||||
ICPU(0x56, core_params),
|
||||
ICPU(INTEL_FAM6_BROADWELL_XEON_D, core_params),
|
||||
{}
|
||||
};
|
||||
|
||||
|
||||
@ -62,6 +62,7 @@
|
||||
#include <linux/cpu.h>
|
||||
#include <linux/module.h>
|
||||
#include <asm/cpu_device_id.h>
|
||||
#include <asm/intel-family.h>
|
||||
#include <asm/mwait.h>
|
||||
#include <asm/msr.h>
|
||||
|
||||
@ -1020,38 +1021,38 @@ static const struct idle_cpu idle_cpu_bxt = {
|
||||
{ X86_VENDOR_INTEL, 6, model, X86_FEATURE_MWAIT, (unsigned long)&cpu }
|
||||
|
||||
static const struct x86_cpu_id intel_idle_ids[] __initconst = {
|
||||
ICPU(0x1a, idle_cpu_nehalem),
|
||||
ICPU(0x1e, idle_cpu_nehalem),
|
||||
ICPU(0x1f, idle_cpu_nehalem),
|
||||
ICPU(0x25, idle_cpu_nehalem),
|
||||
ICPU(0x2c, idle_cpu_nehalem),
|
||||
ICPU(0x2e, idle_cpu_nehalem),
|
||||
ICPU(0x1c, idle_cpu_atom),
|
||||
ICPU(0x26, idle_cpu_lincroft),
|
||||
ICPU(0x2f, idle_cpu_nehalem),
|
||||
ICPU(0x2a, idle_cpu_snb),
|
||||
ICPU(0x2d, idle_cpu_snb),
|
||||
ICPU(0x36, idle_cpu_atom),
|
||||
ICPU(0x37, idle_cpu_byt),
|
||||
ICPU(0x4c, idle_cpu_cht),
|
||||
ICPU(0x3a, idle_cpu_ivb),
|
||||
ICPU(0x3e, idle_cpu_ivt),
|
||||
ICPU(0x3c, idle_cpu_hsw),
|
||||
ICPU(0x3f, idle_cpu_hsw),
|
||||
ICPU(0x45, idle_cpu_hsw),
|
||||
ICPU(0x46, idle_cpu_hsw),
|
||||
ICPU(0x4d, idle_cpu_avn),
|
||||
ICPU(0x3d, idle_cpu_bdw),
|
||||
ICPU(0x47, idle_cpu_bdw),
|
||||
ICPU(0x4f, idle_cpu_bdw),
|
||||
ICPU(0x56, idle_cpu_bdw),
|
||||
ICPU(0x4e, idle_cpu_skl),
|
||||
ICPU(0x5e, idle_cpu_skl),
|
||||
ICPU(0x8e, idle_cpu_skl),
|
||||
ICPU(0x9e, idle_cpu_skl),
|
||||
ICPU(0x55, idle_cpu_skx),
|
||||
ICPU(0x57, idle_cpu_knl),
|
||||
ICPU(0x5c, idle_cpu_bxt),
|
||||
ICPU(INTEL_FAM6_NEHALEM_EP, idle_cpu_nehalem),
|
||||
ICPU(INTEL_FAM6_NEHALEM, idle_cpu_nehalem),
|
||||
ICPU(INTEL_FAM6_WESTMERE2, idle_cpu_nehalem),
|
||||
ICPU(INTEL_FAM6_WESTMERE, idle_cpu_nehalem),
|
||||
ICPU(INTEL_FAM6_WESTMERE_EP, idle_cpu_nehalem),
|
||||
ICPU(INTEL_FAM6_NEHALEM_EX, idle_cpu_nehalem),
|
||||
ICPU(INTEL_FAM6_ATOM_PINEVIEW, idle_cpu_atom),
|
||||
ICPU(INTEL_FAM6_ATOM_LINCROFT, idle_cpu_lincroft),
|
||||
ICPU(INTEL_FAM6_WESTMERE_EX, idle_cpu_nehalem),
|
||||
ICPU(INTEL_FAM6_SANDYBRIDGE, idle_cpu_snb),
|
||||
ICPU(INTEL_FAM6_SANDYBRIDGE_X, idle_cpu_snb),
|
||||
ICPU(INTEL_FAM6_ATOM_CEDARVIEW, idle_cpu_atom),
|
||||
ICPU(INTEL_FAM6_ATOM_SILVERMONT1, idle_cpu_byt),
|
||||
ICPU(INTEL_FAM6_ATOM_AIRMONT, idle_cpu_cht),
|
||||
ICPU(INTEL_FAM6_IVYBRIDGE, idle_cpu_ivb),
|
||||
ICPU(INTEL_FAM6_IVYBRIDGE_X, idle_cpu_ivt),
|
||||
ICPU(INTEL_FAM6_HASWELL_CORE, idle_cpu_hsw),
|
||||
ICPU(INTEL_FAM6_HASWELL_X, idle_cpu_hsw),
|
||||
ICPU(INTEL_FAM6_HASWELL_ULT, idle_cpu_hsw),
|
||||
ICPU(INTEL_FAM6_HASWELL_GT3E, idle_cpu_hsw),
|
||||
ICPU(INTEL_FAM6_ATOM_SILVERMONT2, idle_cpu_avn),
|
||||
ICPU(INTEL_FAM6_BROADWELL_CORE, idle_cpu_bdw),
|
||||
ICPU(INTEL_FAM6_BROADWELL_GT3E, idle_cpu_bdw),
|
||||
ICPU(INTEL_FAM6_BROADWELL_X, idle_cpu_bdw),
|
||||
ICPU(INTEL_FAM6_BROADWELL_XEON_D, idle_cpu_bdw),
|
||||
ICPU(INTEL_FAM6_SKYLAKE_MOBILE, idle_cpu_skl),
|
||||
ICPU(INTEL_FAM6_SKYLAKE_DESKTOP, idle_cpu_skl),
|
||||
ICPU(INTEL_FAM6_KABYLAKE_MOBILE, idle_cpu_skl),
|
||||
ICPU(INTEL_FAM6_KABYLAKE_DESKTOP, idle_cpu_skl),
|
||||
ICPU(INTEL_FAM6_SKYLAKE_X, idle_cpu_skx),
|
||||
ICPU(INTEL_FAM6_XEON_PHI_KNL, idle_cpu_knl),
|
||||
ICPU(INTEL_FAM6_ATOM_GOLDMONT, idle_cpu_bxt),
|
||||
{}
|
||||
};
|
||||
MODULE_DEVICE_TABLE(x86cpu, intel_idle_ids);
|
||||
@ -1261,13 +1262,13 @@ static void intel_idle_state_table_update(void)
|
||||
{
|
||||
switch (boot_cpu_data.x86_model) {
|
||||
|
||||
case 0x3e: /* IVT */
|
||||
case INTEL_FAM6_IVYBRIDGE_X:
|
||||
ivt_idle_state_table_update();
|
||||
break;
|
||||
case 0x5c: /* BXT */
|
||||
case INTEL_FAM6_ATOM_GOLDMONT:
|
||||
bxt_idle_state_table_update();
|
||||
break;
|
||||
case 0x5e: /* SKL-H */
|
||||
case INTEL_FAM6_SKYLAKE_DESKTOP:
|
||||
sklh_idle_state_table_update();
|
||||
break;
|
||||
}
|
||||
|
||||
@ -43,6 +43,7 @@
|
||||
|
||||
#ifdef CONFIG_X86
|
||||
#include <asm/cpu_device_id.h>
|
||||
#include <asm/intel-family.h>
|
||||
#include <asm/iosf_mbi.h>
|
||||
#endif
|
||||
|
||||
@ -126,7 +127,7 @@ static const struct sdhci_acpi_chip sdhci_acpi_chip_int = {
|
||||
static bool sdhci_acpi_byt(void)
|
||||
{
|
||||
static const struct x86_cpu_id byt[] = {
|
||||
{ X86_VENDOR_INTEL, 6, 0x37 },
|
||||
{ X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_SILVERMONT1 },
|
||||
{}
|
||||
};
|
||||
|
||||
|
||||
@ -51,6 +51,9 @@ obj-$(CONFIG_ACPI) += pci-acpi.o
|
||||
# SMBIOS provided firmware instance and labels
|
||||
obj-$(CONFIG_PCI_LABEL) += pci-label.o
|
||||
|
||||
# Intel MID platform PM support
|
||||
obj-$(CONFIG_X86_INTEL_MID) += pci-mid.o
|
||||
|
||||
obj-$(CONFIG_PCI_SYSCALL) += syscall.o
|
||||
|
||||
obj-$(CONFIG_PCI_STUB) += pci-stub.o
|
||||
|
||||
77
drivers/pci/pci-mid.c
Normal file
77
drivers/pci/pci-mid.c
Normal file
@ -0,0 +1,77 @@
|
||||
/*
|
||||
* Intel MID platform PM support
|
||||
*
|
||||
* Copyright (C) 2016, Intel Corporation
|
||||
*
|
||||
* Author: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include <linux/init.h>
|
||||
#include <linux/pci.h>
|
||||
|
||||
#include <asm/cpu_device_id.h>
|
||||
#include <asm/intel-family.h>
|
||||
#include <asm/intel-mid.h>
|
||||
|
||||
#include "pci.h"
|
||||
|
||||
static bool mid_pci_power_manageable(struct pci_dev *dev)
|
||||
{
|
||||
return true;
|
||||
}
|
||||
|
||||
static int mid_pci_set_power_state(struct pci_dev *pdev, pci_power_t state)
|
||||
{
|
||||
return intel_mid_pci_set_power_state(pdev, state);
|
||||
}
|
||||
|
||||
static pci_power_t mid_pci_choose_state(struct pci_dev *pdev)
|
||||
{
|
||||
return PCI_D3hot;
|
||||
}
|
||||
|
||||
static int mid_pci_sleep_wake(struct pci_dev *dev, bool enable)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int mid_pci_run_wake(struct pci_dev *dev, bool enable)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static bool mid_pci_need_resume(struct pci_dev *dev)
|
||||
{
|
||||
return false;
|
||||
}
|
||||
|
||||
static struct pci_platform_pm_ops mid_pci_platform_pm = {
|
||||
.is_manageable = mid_pci_power_manageable,
|
||||
.set_state = mid_pci_set_power_state,
|
||||
.choose_state = mid_pci_choose_state,
|
||||
.sleep_wake = mid_pci_sleep_wake,
|
||||
.run_wake = mid_pci_run_wake,
|
||||
.need_resume = mid_pci_need_resume,
|
||||
};
|
||||
|
||||
#define ICPU(model) { X86_VENDOR_INTEL, 6, model, X86_FEATURE_ANY, }
|
||||
|
||||
static const struct x86_cpu_id lpss_cpu_ids[] = {
|
||||
ICPU(INTEL_FAM6_ATOM_MERRIFIELD1),
|
||||
{}
|
||||
};
|
||||
|
||||
static int __init mid_pci_init(void)
|
||||
{
|
||||
const struct x86_cpu_id *id;
|
||||
|
||||
id = x86_match_cpu(lpss_cpu_ids);
|
||||
if (id)
|
||||
pci_set_platform_pm(&mid_pci_platform_pm);
|
||||
return 0;
|
||||
}
|
||||
arch_initcall(mid_pci_init);
|
||||
@ -32,6 +32,7 @@
|
||||
#include <linux/suspend.h>
|
||||
|
||||
#include <asm/cpu_device_id.h>
|
||||
#include <asm/intel-family.h>
|
||||
#include <asm/intel_pmc_ipc.h>
|
||||
#include <asm/intel_punit_ipc.h>
|
||||
#include <asm/intel_telemetry.h>
|
||||
@ -331,7 +332,7 @@ static struct telemetry_debugfs_conf telem_apl_debugfs_conf = {
|
||||
};
|
||||
|
||||
static const struct x86_cpu_id telemetry_debugfs_cpu_ids[] = {
|
||||
TELEM_DEBUGFS_CPU(0x5c, telem_apl_debugfs_conf),
|
||||
TELEM_DEBUGFS_CPU(INTEL_FAM6_ATOM_GOLDMONT, telem_apl_debugfs_conf),
|
||||
{}
|
||||
};
|
||||
|
||||
|
||||
@ -28,6 +28,7 @@
|
||||
#include <linux/platform_device.h>
|
||||
|
||||
#include <asm/cpu_device_id.h>
|
||||
#include <asm/intel-family.h>
|
||||
#include <asm/intel_pmc_ipc.h>
|
||||
#include <asm/intel_punit_ipc.h>
|
||||
#include <asm/intel_telemetry.h>
|
||||
@ -163,7 +164,7 @@ static struct telemetry_plt_config telem_apl_config = {
|
||||
};
|
||||
|
||||
static const struct x86_cpu_id telemetry_cpu_ids[] = {
|
||||
TELEM_CPU(0x5c, telem_apl_config),
|
||||
TELEM_CPU(INTEL_FAM6_ATOM_GOLDMONT, telem_apl_config),
|
||||
{}
|
||||
};
|
||||
|
||||
|
||||
@ -33,6 +33,7 @@
|
||||
|
||||
#include <asm/processor.h>
|
||||
#include <asm/cpu_device_id.h>
|
||||
#include <asm/intel-family.h>
|
||||
|
||||
/* Local defines */
|
||||
#define MSR_PLATFORM_POWER_LIMIT 0x0000065C
|
||||
@ -1096,27 +1097,34 @@ static const struct rapl_defaults rapl_defaults_cht = {
|
||||
}
|
||||
|
||||
static const struct x86_cpu_id rapl_ids[] __initconst = {
|
||||
RAPL_CPU(0x2a, rapl_defaults_core),/* Sandy Bridge */
|
||||
RAPL_CPU(0x2d, rapl_defaults_core),/* Sandy Bridge EP */
|
||||
RAPL_CPU(0x37, rapl_defaults_byt),/* Valleyview */
|
||||
RAPL_CPU(0x3a, rapl_defaults_core),/* Ivy Bridge */
|
||||
RAPL_CPU(0x3c, rapl_defaults_core),/* Haswell */
|
||||
RAPL_CPU(0x3d, rapl_defaults_core),/* Broadwell */
|
||||
RAPL_CPU(0x3f, rapl_defaults_hsw_server),/* Haswell servers */
|
||||
RAPL_CPU(0x4f, rapl_defaults_hsw_server),/* Broadwell servers */
|
||||
RAPL_CPU(0x45, rapl_defaults_core),/* Haswell ULT */
|
||||
RAPL_CPU(0x46, rapl_defaults_core),/* Haswell */
|
||||
RAPL_CPU(0x47, rapl_defaults_core),/* Broadwell-H */
|
||||
RAPL_CPU(0x4E, rapl_defaults_core),/* Skylake */
|
||||
RAPL_CPU(0x4C, rapl_defaults_cht),/* Braswell/Cherryview */
|
||||
RAPL_CPU(0x4A, rapl_defaults_tng),/* Tangier */
|
||||
RAPL_CPU(0x56, rapl_defaults_core),/* Future Xeon */
|
||||
RAPL_CPU(0x5A, rapl_defaults_ann),/* Annidale */
|
||||
RAPL_CPU(0X5C, rapl_defaults_core),/* Broxton */
|
||||
RAPL_CPU(0x5E, rapl_defaults_core),/* Skylake-H/S */
|
||||
RAPL_CPU(0x57, rapl_defaults_hsw_server),/* Knights Landing */
|
||||
RAPL_CPU(0x8E, rapl_defaults_core),/* Kabylake */
|
||||
RAPL_CPU(0x9E, rapl_defaults_core),/* Kabylake */
|
||||
RAPL_CPU(INTEL_FAM6_SANDYBRIDGE, rapl_defaults_core),
|
||||
RAPL_CPU(INTEL_FAM6_SANDYBRIDGE_X, rapl_defaults_core),
|
||||
|
||||
RAPL_CPU(INTEL_FAM6_IVYBRIDGE, rapl_defaults_core),
|
||||
|
||||
RAPL_CPU(INTEL_FAM6_HASWELL_CORE, rapl_defaults_core),
|
||||
RAPL_CPU(INTEL_FAM6_HASWELL_ULT, rapl_defaults_core),
|
||||
RAPL_CPU(INTEL_FAM6_HASWELL_GT3E, rapl_defaults_core),
|
||||
RAPL_CPU(INTEL_FAM6_HASWELL_X, rapl_defaults_hsw_server),
|
||||
|
||||
RAPL_CPU(INTEL_FAM6_BROADWELL_CORE, rapl_defaults_core),
|
||||
RAPL_CPU(INTEL_FAM6_BROADWELL_GT3E, rapl_defaults_core),
|
||||
RAPL_CPU(INTEL_FAM6_BROADWELL_XEON_D, rapl_defaults_core),
|
||||
RAPL_CPU(INTEL_FAM6_BROADWELL_X, rapl_defaults_hsw_server),
|
||||
|
||||
RAPL_CPU(INTEL_FAM6_SKYLAKE_DESKTOP, rapl_defaults_core),
|
||||
RAPL_CPU(INTEL_FAM6_SKYLAKE_MOBILE, rapl_defaults_core),
|
||||
RAPL_CPU(INTEL_FAM6_SKYLAKE_X, rapl_defaults_hsw_server),
|
||||
RAPL_CPU(INTEL_FAM6_KABYLAKE_MOBILE, rapl_defaults_core),
|
||||
RAPL_CPU(INTEL_FAM6_KABYLAKE_DESKTOP, rapl_defaults_core),
|
||||
|
||||
RAPL_CPU(INTEL_FAM6_ATOM_SILVERMONT1, rapl_defaults_byt),
|
||||
RAPL_CPU(INTEL_FAM6_ATOM_AIRMONT, rapl_defaults_cht),
|
||||
RAPL_CPU(INTEL_FAM6_ATOM_MERRIFIELD1, rapl_defaults_tng),
|
||||
RAPL_CPU(INTEL_FAM6_ATOM_MERRIFIELD2, rapl_defaults_ann),
|
||||
RAPL_CPU(INTEL_FAM6_ATOM_GOLDMONT, rapl_defaults_core),
|
||||
|
||||
RAPL_CPU(INTEL_FAM6_XEON_PHI_KNL, rapl_defaults_hsw_server),
|
||||
{}
|
||||
};
|
||||
MODULE_DEVICE_TABLE(x86cpu, rapl_ids);
|
||||
|
||||
@ -18,6 +18,7 @@
|
||||
#include <linux/module.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <asm/cpu_device_id.h>
|
||||
#include <asm/intel-family.h>
|
||||
#include "intel_soc_dts_iosf.h"
|
||||
|
||||
#define CRITICAL_OFFSET_FROM_TJ_MAX 5000
|
||||
@ -42,7 +43,8 @@ static irqreturn_t soc_irq_thread_fn(int irq, void *dev_data)
|
||||
}
|
||||
|
||||
static const struct x86_cpu_id soc_thermal_ids[] = {
|
||||
{ X86_VENDOR_INTEL, X86_FAMILY_ANY, 0x37, 0, BYT_SOC_DTS_APIC_IRQ},
|
||||
{ X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_SILVERMONT1, 0,
|
||||
BYT_SOC_DTS_APIC_IRQ},
|
||||
{}
|
||||
};
|
||||
MODULE_DEVICE_TABLE(x86cpu, soc_thermal_ids);
|
||||
|
||||
@ -156,6 +156,7 @@ struct sfi_device_table_entry {
|
||||
#define SFI_DEV_TYPE_UART 2
|
||||
#define SFI_DEV_TYPE_HSI 3
|
||||
#define SFI_DEV_TYPE_IPC 4
|
||||
#define SFI_DEV_TYPE_SD 5
|
||||
|
||||
u8 host_num; /* attached to host 0, 1...*/
|
||||
u16 addr;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user