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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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OMAPFB: Remove OMAP2/3 support from old omapfb driver
Old omapfb driver (drivers/video/omap/) is no longer used for OMAP2+ devices, and thus we can remove OMAP2+ support from it and make it an OMAP1 omapfb driver. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
This commit is contained in:
Tomi Valkeinen
parent
fdcb68884b
commit
8dc50ec775
@ -1,11 +1,10 @@
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config FB_OMAP
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tristate "OMAP frame buffer support (EXPERIMENTAL)"
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depends on FB && (OMAP2_DSS = "n")
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depends on ARCH_OMAP1 || ARCH_OMAP2 || ARCH_OMAP3
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depends on FB
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depends on ARCH_OMAP1
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select FB_CFB_FILLRECT
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select FB_CFB_COPYAREA
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select FB_CFB_IMAGEBLIT
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select TWL4030_CORE if MACH_OMAP_2430SDP
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help
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Frame buffer driver for OMAP based boards.
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@ -42,7 +41,7 @@ config FB_OMAP_LCD_MIPID
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config FB_OMAP_BOOTLOADER_INIT
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bool "Check bootloader initialization"
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depends on FB_OMAP || FB_OMAP2
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depends on FB_OMAP
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help
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Say Y here if you want to enable checking if the bootloader has
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already initialized the display controller. In this case the
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@ -61,7 +60,7 @@ config FB_OMAP_CONSISTENT_DMA_SIZE
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config FB_OMAP_DMA_TUNE
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bool "Set DMA SDRAM access priority high"
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depends on FB_OMAP && ARCH_OMAP1
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depends on FB_OMAP
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help
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On systems in which video memory is in system memory
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(SDRAM) this will speed up graphics DMA operations.
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@ -1,5 +1,5 @@
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#
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# Makefile for the new OMAP framebuffer device driver
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# Makefile for the OMAP1 framebuffer device driver
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#
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obj-$(CONFIG_FB_OMAP) += omapfb.o
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@ -7,11 +7,8 @@ obj-$(CONFIG_FB_OMAP) += omapfb.o
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objs-yy := omapfb_main.o
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objs-y$(CONFIG_ARCH_OMAP1) += lcdc.o
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objs-y$(CONFIG_ARCH_OMAP2) += dispc.o
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objs-y$(CONFIG_ARCH_OMAP3) += dispc.o
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objs-$(CONFIG_ARCH_OMAP1)$(CONFIG_FB_OMAP_LCDC_EXTERNAL) += sossi.o
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objs-$(CONFIG_ARCH_OMAP2)$(CONFIG_FB_OMAP_LCDC_EXTERNAL) += rfbi.o
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objs-y$(CONFIG_FB_OMAP_LCDC_HWA742) += hwa742.o
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File diff suppressed because it is too large
Load Diff
@ -1,46 +0,0 @@
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#ifndef _DISPC_H
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#define _DISPC_H
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#include <linux/interrupt.h>
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#define DISPC_PLANE_GFX 0
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#define DISPC_PLANE_VID1 1
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#define DISPC_PLANE_VID2 2
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#define DISPC_RGB_1_BPP 0x00
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#define DISPC_RGB_2_BPP 0x01
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#define DISPC_RGB_4_BPP 0x02
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#define DISPC_RGB_8_BPP 0x03
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#define DISPC_RGB_12_BPP 0x04
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#define DISPC_RGB_16_BPP 0x06
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#define DISPC_RGB_24_BPP 0x08
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#define DISPC_RGB_24_BPP_UNPACK_32 0x09
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#define DISPC_YUV2_422 0x0a
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#define DISPC_UYVY_422 0x0b
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#define DISPC_BURST_4x32 0
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#define DISPC_BURST_8x32 1
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#define DISPC_BURST_16x32 2
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#define DISPC_LOAD_CLUT_AND_FRAME 0x00
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#define DISPC_LOAD_CLUT_ONLY 0x01
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#define DISPC_LOAD_FRAME_ONLY 0x02
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#define DISPC_LOAD_CLUT_ONCE_FRAME 0x03
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#define DISPC_TFT_DATA_LINES_12 0
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#define DISPC_TFT_DATA_LINES_16 1
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#define DISPC_TFT_DATA_LINES_18 2
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#define DISPC_TFT_DATA_LINES_24 3
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extern void omap_dispc_set_lcd_size(int width, int height);
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extern void omap_dispc_enable_lcd_out(int enable);
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extern void omap_dispc_enable_digit_out(int enable);
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extern int omap_dispc_request_irq(unsigned long irq_mask,
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void (*callback)(void *data), void *data);
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extern void omap_dispc_free_irq(unsigned long irq_mask,
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void (*callback)(void *data), void *data);
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extern const struct lcd_ctrl omap2_int_ctrl;
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#endif
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@ -207,11 +207,7 @@ struct omapfb_device {
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struct platform_device *dssdev; /* dummy dev for clocks */
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};
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#ifdef CONFIG_ARCH_OMAP1
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extern struct lcd_ctrl omap1_lcd_ctrl;
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#else
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extern struct lcd_ctrl omap2_disp_ctrl;
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#endif
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extern void omapfb_register_panel(struct lcd_panel *panel);
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extern void omapfb_write_first_pixel(struct omapfb_device *fbdev, u16 pixval);
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@ -34,7 +34,6 @@
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#include "omapfb.h"
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#include "lcdc.h"
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#include "dispc.h"
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#define MODULE_NAME "omapfb"
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@ -106,11 +105,7 @@ static struct platform_device omapdss_device = {
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extern struct lcd_ctrl hwa742_ctrl;
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static const struct lcd_ctrl *ctrls[] = {
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#ifdef CONFIG_ARCH_OMAP1
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&omap1_int_ctrl,
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#else
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&omap2_int_ctrl,
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#endif
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#ifdef CONFIG_FB_OMAP_LCDC_HWA742
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&hwa742_ctrl,
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@ -118,11 +113,7 @@ static const struct lcd_ctrl *ctrls[] = {
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};
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#ifdef CONFIG_FB_OMAP_LCDC_EXTERNAL
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#ifdef CONFIG_ARCH_OMAP1
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extern struct lcd_ctrl_extif omap1_ext_if;
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#else
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extern struct lcd_ctrl_extif omap2_ext_if;
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#endif
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#endif
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static void omapfb_rqueue_lock(struct omapfb_device *fbdev)
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@ -1717,16 +1708,9 @@ static int omapfb_do_probe(struct platform_device *pdev,
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mutex_init(&fbdev->rqueue_mutex);
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#ifdef CONFIG_ARCH_OMAP1
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fbdev->int_ctrl = &omap1_int_ctrl;
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#ifdef CONFIG_FB_OMAP_LCDC_EXTERNAL
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fbdev->ext_if = &omap1_ext_if;
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#endif
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#else /* OMAP2 */
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fbdev->int_ctrl = &omap2_int_ctrl;
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#ifdef CONFIG_FB_OMAP_LCDC_EXTERNAL
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fbdev->ext_if = &omap2_ext_if;
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#endif
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#endif
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if (omapfb_find_ctrl(fbdev) < 0) {
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dev_err(fbdev->dev,
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@ -1,598 +0,0 @@
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/*
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* OMAP2 Remote Frame Buffer Interface support
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*
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* Copyright (C) 2005 Nokia Corporation
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* Author: Juha Yrjölä <juha.yrjola@nokia.com>
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* Imre Deak <imre.deak@nokia.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*/
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#include <linux/module.h>
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#include <linux/delay.h>
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#include <linux/i2c.h>
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#include <linux/err.h>
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#include <linux/interrupt.h>
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <linux/platform_device.h>
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#include "omapfb.h"
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#include "dispc.h"
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/* To work around an RFBI transfer rate limitation */
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#define OMAP_RFBI_RATE_LIMIT 1
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#define RFBI_BASE 0x48050800
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#define RFBI_REVISION 0x0000
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#define RFBI_SYSCONFIG 0x0010
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#define RFBI_SYSSTATUS 0x0014
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#define RFBI_CONTROL 0x0040
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#define RFBI_PIXEL_CNT 0x0044
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#define RFBI_LINE_NUMBER 0x0048
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#define RFBI_CMD 0x004c
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#define RFBI_PARAM 0x0050
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#define RFBI_DATA 0x0054
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#define RFBI_READ 0x0058
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#define RFBI_STATUS 0x005c
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#define RFBI_CONFIG0 0x0060
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#define RFBI_ONOFF_TIME0 0x0064
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#define RFBI_CYCLE_TIME0 0x0068
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#define RFBI_DATA_CYCLE1_0 0x006c
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#define RFBI_DATA_CYCLE2_0 0x0070
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#define RFBI_DATA_CYCLE3_0 0x0074
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#define RFBI_VSYNC_WIDTH 0x0090
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#define RFBI_HSYNC_WIDTH 0x0094
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#define DISPC_BASE 0x48050400
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#define DISPC_CONTROL 0x0040
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#define DISPC_IRQ_FRAMEMASK 0x0001
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static struct {
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void __iomem *base;
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void (*lcdc_callback)(void *data);
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void *lcdc_callback_data;
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unsigned long l4_khz;
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int bits_per_cycle;
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struct omapfb_device *fbdev;
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struct clk *dss_ick;
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struct clk *dss1_fck;
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unsigned tearsync_pin_cnt;
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unsigned tearsync_mode;
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} rfbi;
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static inline void rfbi_write_reg(int idx, u32 val)
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{
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__raw_writel(val, rfbi.base + idx);
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}
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static inline u32 rfbi_read_reg(int idx)
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{
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return __raw_readl(rfbi.base + idx);
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}
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static int rfbi_get_clocks(void)
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{
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rfbi.dss_ick = clk_get(&rfbi.fbdev->dssdev->dev, "ick");
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if (IS_ERR(rfbi.dss_ick)) {
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dev_err(rfbi.fbdev->dev, "can't get ick\n");
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return PTR_ERR(rfbi.dss_ick);
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}
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rfbi.dss1_fck = clk_get(&rfbi.fbdev->dssdev->dev, "fck");
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if (IS_ERR(rfbi.dss1_fck)) {
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dev_err(rfbi.fbdev->dev, "can't get dss1_fck\n");
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clk_put(rfbi.dss_ick);
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return PTR_ERR(rfbi.dss1_fck);
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}
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return 0;
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}
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static void rfbi_put_clocks(void)
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{
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clk_put(rfbi.dss1_fck);
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clk_put(rfbi.dss_ick);
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}
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static void rfbi_enable_clocks(int enable)
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{
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if (enable) {
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clk_enable(rfbi.dss_ick);
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clk_enable(rfbi.dss1_fck);
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} else {
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clk_disable(rfbi.dss1_fck);
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clk_disable(rfbi.dss_ick);
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}
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}
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#ifdef VERBOSE
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static void rfbi_print_timings(void)
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{
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u32 l;
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u32 time;
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l = rfbi_read_reg(RFBI_CONFIG0);
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time = 1000000000 / rfbi.l4_khz;
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if (l & (1 << 4))
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time *= 2;
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dev_dbg(rfbi.fbdev->dev, "Tick time %u ps\n", time);
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l = rfbi_read_reg(RFBI_ONOFF_TIME0);
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dev_dbg(rfbi.fbdev->dev,
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"CSONTIME %d, CSOFFTIME %d, WEONTIME %d, WEOFFTIME %d, "
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"REONTIME %d, REOFFTIME %d\n",
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l & 0x0f, (l >> 4) & 0x3f, (l >> 10) & 0x0f, (l >> 14) & 0x3f,
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(l >> 20) & 0x0f, (l >> 24) & 0x3f);
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l = rfbi_read_reg(RFBI_CYCLE_TIME0);
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dev_dbg(rfbi.fbdev->dev,
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"WECYCLETIME %d, RECYCLETIME %d, CSPULSEWIDTH %d, "
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"ACCESSTIME %d\n",
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(l & 0x3f), (l >> 6) & 0x3f, (l >> 12) & 0x3f,
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(l >> 22) & 0x3f);
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}
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#else
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static void rfbi_print_timings(void) {}
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#endif
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static void rfbi_set_timings(const struct extif_timings *t)
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{
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u32 l;
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BUG_ON(!t->converted);
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rfbi_enable_clocks(1);
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rfbi_write_reg(RFBI_ONOFF_TIME0, t->tim[0]);
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rfbi_write_reg(RFBI_CYCLE_TIME0, t->tim[1]);
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l = rfbi_read_reg(RFBI_CONFIG0);
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l &= ~(1 << 4);
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l |= (t->tim[2] ? 1 : 0) << 4;
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rfbi_write_reg(RFBI_CONFIG0, l);
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rfbi_print_timings();
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rfbi_enable_clocks(0);
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}
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static void rfbi_get_clk_info(u32 *clk_period, u32 *max_clk_div)
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{
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*clk_period = 1000000000 / rfbi.l4_khz;
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*max_clk_div = 2;
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}
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static int ps_to_rfbi_ticks(int time, int div)
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{
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unsigned long tick_ps;
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int ret;
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/* Calculate in picosecs to yield more exact results */
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tick_ps = 1000000000 / (rfbi.l4_khz) * div;
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ret = (time + tick_ps - 1) / tick_ps;
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return ret;
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}
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#ifdef OMAP_RFBI_RATE_LIMIT
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static unsigned long rfbi_get_max_tx_rate(void)
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{
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unsigned long l4_rate, dss1_rate;
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int min_l4_ticks = 0;
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int i;
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/* According to TI this can't be calculated so make the
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* adjustments for a couple of known frequencies and warn for
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* others.
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*/
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static const struct {
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unsigned long l4_clk; /* HZ */
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unsigned long dss1_clk; /* HZ */
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unsigned long min_l4_ticks;
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} ftab[] = {
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{ 55, 132, 7, }, /* 7.86 MPix/s */
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{ 110, 110, 12, }, /* 9.16 MPix/s */
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{ 110, 132, 10, }, /* 11 Mpix/s */
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{ 120, 120, 10, }, /* 12 Mpix/s */
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{ 133, 133, 10, }, /* 13.3 Mpix/s */
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};
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l4_rate = rfbi.l4_khz / 1000;
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dss1_rate = clk_get_rate(rfbi.dss1_fck) / 1000000;
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for (i = 0; i < ARRAY_SIZE(ftab); i++) {
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/* Use a window instead of an exact match, to account
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* for different DPLL multiplier / divider pairs.
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*/
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if (abs(ftab[i].l4_clk - l4_rate) < 3 &&
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abs(ftab[i].dss1_clk - dss1_rate) < 3) {
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min_l4_ticks = ftab[i].min_l4_ticks;
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break;
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}
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}
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if (i == ARRAY_SIZE(ftab)) {
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/* Can't be sure, return anyway the maximum not
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* rate-limited. This might cause a problem only for the
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* tearing synchronisation.
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*/
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dev_err(rfbi.fbdev->dev,
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"can't determine maximum RFBI transfer rate\n");
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return rfbi.l4_khz * 1000;
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}
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return rfbi.l4_khz * 1000 / min_l4_ticks;
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}
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#else
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static int rfbi_get_max_tx_rate(void)
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{
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return rfbi.l4_khz * 1000;
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}
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#endif
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static int rfbi_convert_timings(struct extif_timings *t)
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{
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u32 l;
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int reon, reoff, weon, weoff, cson, csoff, cs_pulse;
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int actim, recyc, wecyc;
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int div = t->clk_div;
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if (div <= 0 || div > 2)
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return -1;
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/* Make sure that after conversion it still holds that:
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* weoff > weon, reoff > reon, recyc >= reoff, wecyc >= weoff,
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* csoff > cson, csoff >= max(weoff, reoff), actim > reon
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*/
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weon = ps_to_rfbi_ticks(t->we_on_time, div);
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weoff = ps_to_rfbi_ticks(t->we_off_time, div);
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if (weoff <= weon)
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weoff = weon + 1;
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if (weon > 0x0f)
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return -1;
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if (weoff > 0x3f)
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return -1;
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reon = ps_to_rfbi_ticks(t->re_on_time, div);
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reoff = ps_to_rfbi_ticks(t->re_off_time, div);
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if (reoff <= reon)
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reoff = reon + 1;
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if (reon > 0x0f)
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return -1;
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if (reoff > 0x3f)
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return -1;
|
||||
|
||||
cson = ps_to_rfbi_ticks(t->cs_on_time, div);
|
||||
csoff = ps_to_rfbi_ticks(t->cs_off_time, div);
|
||||
if (csoff <= cson)
|
||||
csoff = cson + 1;
|
||||
if (csoff < max(weoff, reoff))
|
||||
csoff = max(weoff, reoff);
|
||||
if (cson > 0x0f)
|
||||
return -1;
|
||||
if (csoff > 0x3f)
|
||||
return -1;
|
||||
|
||||
l = cson;
|
||||
l |= csoff << 4;
|
||||
l |= weon << 10;
|
||||
l |= weoff << 14;
|
||||
l |= reon << 20;
|
||||
l |= reoff << 24;
|
||||
|
||||
t->tim[0] = l;
|
||||
|
||||
actim = ps_to_rfbi_ticks(t->access_time, div);
|
||||
if (actim <= reon)
|
||||
actim = reon + 1;
|
||||
if (actim > 0x3f)
|
||||
return -1;
|
||||
|
||||
wecyc = ps_to_rfbi_ticks(t->we_cycle_time, div);
|
||||
if (wecyc < weoff)
|
||||
wecyc = weoff;
|
||||
if (wecyc > 0x3f)
|
||||
return -1;
|
||||
|
||||
recyc = ps_to_rfbi_ticks(t->re_cycle_time, div);
|
||||
if (recyc < reoff)
|
||||
recyc = reoff;
|
||||
if (recyc > 0x3f)
|
||||
return -1;
|
||||
|
||||
cs_pulse = ps_to_rfbi_ticks(t->cs_pulse_width, div);
|
||||
if (cs_pulse > 0x3f)
|
||||
return -1;
|
||||
|
||||
l = wecyc;
|
||||
l |= recyc << 6;
|
||||
l |= cs_pulse << 12;
|
||||
l |= actim << 22;
|
||||
|
||||
t->tim[1] = l;
|
||||
|
||||
t->tim[2] = div - 1;
|
||||
|
||||
t->converted = 1;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int rfbi_setup_tearsync(unsigned pin_cnt,
|
||||
unsigned hs_pulse_time, unsigned vs_pulse_time,
|
||||
int hs_pol_inv, int vs_pol_inv, int extif_div)
|
||||
{
|
||||
int hs, vs;
|
||||
int min;
|
||||
u32 l;
|
||||
|
||||
if (pin_cnt != 1 && pin_cnt != 2)
|
||||
return -EINVAL;
|
||||
|
||||
hs = ps_to_rfbi_ticks(hs_pulse_time, 1);
|
||||
vs = ps_to_rfbi_ticks(vs_pulse_time, 1);
|
||||
if (hs < 2)
|
||||
return -EDOM;
|
||||
if (pin_cnt == 2)
|
||||
min = 2;
|
||||
else
|
||||
min = 4;
|
||||
if (vs < min)
|
||||
return -EDOM;
|
||||
if (vs == hs)
|
||||
return -EINVAL;
|
||||
rfbi.tearsync_pin_cnt = pin_cnt;
|
||||
dev_dbg(rfbi.fbdev->dev,
|
||||
"setup_tearsync: pins %d hs %d vs %d hs_inv %d vs_inv %d\n",
|
||||
pin_cnt, hs, vs, hs_pol_inv, vs_pol_inv);
|
||||
|
||||
rfbi_enable_clocks(1);
|
||||
rfbi_write_reg(RFBI_HSYNC_WIDTH, hs);
|
||||
rfbi_write_reg(RFBI_VSYNC_WIDTH, vs);
|
||||
|
||||
l = rfbi_read_reg(RFBI_CONFIG0);
|
||||
if (hs_pol_inv)
|
||||
l &= ~(1 << 21);
|
||||
else
|
||||
l |= 1 << 21;
|
||||
if (vs_pol_inv)
|
||||
l &= ~(1 << 20);
|
||||
else
|
||||
l |= 1 << 20;
|
||||
rfbi_enable_clocks(0);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int rfbi_enable_tearsync(int enable, unsigned line)
|
||||
{
|
||||
u32 l;
|
||||
|
||||
dev_dbg(rfbi.fbdev->dev, "tearsync %d line %d mode %d\n",
|
||||
enable, line, rfbi.tearsync_mode);
|
||||
if (line > (1 << 11) - 1)
|
||||
return -EINVAL;
|
||||
|
||||
rfbi_enable_clocks(1);
|
||||
l = rfbi_read_reg(RFBI_CONFIG0);
|
||||
l &= ~(0x3 << 2);
|
||||
if (enable) {
|
||||
rfbi.tearsync_mode = rfbi.tearsync_pin_cnt;
|
||||
l |= rfbi.tearsync_mode << 2;
|
||||
} else
|
||||
rfbi.tearsync_mode = 0;
|
||||
rfbi_write_reg(RFBI_CONFIG0, l);
|
||||
rfbi_write_reg(RFBI_LINE_NUMBER, line);
|
||||
rfbi_enable_clocks(0);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void rfbi_write_command(const void *buf, unsigned int len)
|
||||
{
|
||||
rfbi_enable_clocks(1);
|
||||
if (rfbi.bits_per_cycle == 16) {
|
||||
const u16 *w = buf;
|
||||
BUG_ON(len & 1);
|
||||
for (; len; len -= 2)
|
||||
rfbi_write_reg(RFBI_CMD, *w++);
|
||||
} else {
|
||||
const u8 *b = buf;
|
||||
BUG_ON(rfbi.bits_per_cycle != 8);
|
||||
for (; len; len--)
|
||||
rfbi_write_reg(RFBI_CMD, *b++);
|
||||
}
|
||||
rfbi_enable_clocks(0);
|
||||
}
|
||||
|
||||
static void rfbi_read_data(void *buf, unsigned int len)
|
||||
{
|
||||
rfbi_enable_clocks(1);
|
||||
if (rfbi.bits_per_cycle == 16) {
|
||||
u16 *w = buf;
|
||||
BUG_ON(len & ~1);
|
||||
for (; len; len -= 2) {
|
||||
rfbi_write_reg(RFBI_READ, 0);
|
||||
*w++ = rfbi_read_reg(RFBI_READ);
|
||||
}
|
||||
} else {
|
||||
u8 *b = buf;
|
||||
BUG_ON(rfbi.bits_per_cycle != 8);
|
||||
for (; len; len--) {
|
||||
rfbi_write_reg(RFBI_READ, 0);
|
||||
*b++ = rfbi_read_reg(RFBI_READ);
|
||||
}
|
||||
}
|
||||
rfbi_enable_clocks(0);
|
||||
}
|
||||
|
||||
static void rfbi_write_data(const void *buf, unsigned int len)
|
||||
{
|
||||
rfbi_enable_clocks(1);
|
||||
if (rfbi.bits_per_cycle == 16) {
|
||||
const u16 *w = buf;
|
||||
BUG_ON(len & 1);
|
||||
for (; len; len -= 2)
|
||||
rfbi_write_reg(RFBI_PARAM, *w++);
|
||||
} else {
|
||||
const u8 *b = buf;
|
||||
BUG_ON(rfbi.bits_per_cycle != 8);
|
||||
for (; len; len--)
|
||||
rfbi_write_reg(RFBI_PARAM, *b++);
|
||||
}
|
||||
rfbi_enable_clocks(0);
|
||||
}
|
||||
|
||||
static void rfbi_transfer_area(int width, int height,
|
||||
void (callback)(void * data), void *data)
|
||||
{
|
||||
u32 w;
|
||||
|
||||
BUG_ON(callback == NULL);
|
||||
|
||||
rfbi_enable_clocks(1);
|
||||
omap_dispc_set_lcd_size(width, height);
|
||||
|
||||
rfbi.lcdc_callback = callback;
|
||||
rfbi.lcdc_callback_data = data;
|
||||
|
||||
rfbi_write_reg(RFBI_PIXEL_CNT, width * height);
|
||||
|
||||
w = rfbi_read_reg(RFBI_CONTROL);
|
||||
w |= 1; /* enable */
|
||||
if (!rfbi.tearsync_mode)
|
||||
w |= 1 << 4; /* internal trigger, reset by HW */
|
||||
rfbi_write_reg(RFBI_CONTROL, w);
|
||||
|
||||
omap_dispc_enable_lcd_out(1);
|
||||
}
|
||||
|
||||
static inline void _stop_transfer(void)
|
||||
{
|
||||
u32 w;
|
||||
|
||||
w = rfbi_read_reg(RFBI_CONTROL);
|
||||
rfbi_write_reg(RFBI_CONTROL, w & ~(1 << 0));
|
||||
rfbi_enable_clocks(0);
|
||||
}
|
||||
|
||||
static void rfbi_dma_callback(void *data)
|
||||
{
|
||||
_stop_transfer();
|
||||
rfbi.lcdc_callback(rfbi.lcdc_callback_data);
|
||||
}
|
||||
|
||||
static void rfbi_set_bits_per_cycle(int bpc)
|
||||
{
|
||||
u32 l;
|
||||
|
||||
rfbi_enable_clocks(1);
|
||||
l = rfbi_read_reg(RFBI_CONFIG0);
|
||||
l &= ~(0x03 << 0);
|
||||
|
||||
switch (bpc) {
|
||||
case 8:
|
||||
break;
|
||||
case 16:
|
||||
l |= 3;
|
||||
break;
|
||||
default:
|
||||
BUG();
|
||||
}
|
||||
rfbi_write_reg(RFBI_CONFIG0, l);
|
||||
rfbi.bits_per_cycle = bpc;
|
||||
rfbi_enable_clocks(0);
|
||||
}
|
||||
|
||||
static int rfbi_init(struct omapfb_device *fbdev)
|
||||
{
|
||||
u32 l;
|
||||
int r;
|
||||
|
||||
rfbi.fbdev = fbdev;
|
||||
rfbi.base = ioremap(RFBI_BASE, SZ_1K);
|
||||
if (!rfbi.base) {
|
||||
dev_err(fbdev->dev, "can't ioremap RFBI\n");
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
if ((r = rfbi_get_clocks()) < 0)
|
||||
return r;
|
||||
rfbi_enable_clocks(1);
|
||||
|
||||
rfbi.l4_khz = clk_get_rate(rfbi.dss_ick) / 1000;
|
||||
|
||||
/* Reset */
|
||||
rfbi_write_reg(RFBI_SYSCONFIG, 1 << 1);
|
||||
while (!(rfbi_read_reg(RFBI_SYSSTATUS) & (1 << 0)));
|
||||
|
||||
l = rfbi_read_reg(RFBI_SYSCONFIG);
|
||||
/* Enable autoidle and smart-idle */
|
||||
l |= (1 << 0) | (2 << 3);
|
||||
rfbi_write_reg(RFBI_SYSCONFIG, l);
|
||||
|
||||
/* 16-bit interface, ITE trigger mode, 16-bit data */
|
||||
l = (0x03 << 0) | (0x00 << 2) | (0x01 << 5) | (0x02 << 7);
|
||||
l |= (0 << 9) | (1 << 20) | (1 << 21);
|
||||
rfbi_write_reg(RFBI_CONFIG0, l);
|
||||
|
||||
rfbi_write_reg(RFBI_DATA_CYCLE1_0, 0x00000010);
|
||||
|
||||
l = rfbi_read_reg(RFBI_CONTROL);
|
||||
/* Select CS0, clear bypass mode */
|
||||
l = (0x01 << 2);
|
||||
rfbi_write_reg(RFBI_CONTROL, l);
|
||||
|
||||
r = omap_dispc_request_irq(DISPC_IRQ_FRAMEMASK, rfbi_dma_callback,
|
||||
NULL);
|
||||
if (r < 0) {
|
||||
dev_err(fbdev->dev, "can't get DISPC irq\n");
|
||||
rfbi_enable_clocks(0);
|
||||
return r;
|
||||
}
|
||||
|
||||
l = rfbi_read_reg(RFBI_REVISION);
|
||||
pr_info("omapfb: RFBI version %d.%d initialized\n",
|
||||
(l >> 4) & 0x0f, l & 0x0f);
|
||||
|
||||
rfbi_enable_clocks(0);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void rfbi_cleanup(void)
|
||||
{
|
||||
omap_dispc_free_irq(DISPC_IRQ_FRAMEMASK, rfbi_dma_callback, NULL);
|
||||
rfbi_put_clocks();
|
||||
iounmap(rfbi.base);
|
||||
}
|
||||
|
||||
const struct lcd_ctrl_extif omap2_ext_if = {
|
||||
.init = rfbi_init,
|
||||
.cleanup = rfbi_cleanup,
|
||||
.get_clk_info = rfbi_get_clk_info,
|
||||
.get_max_tx_rate = rfbi_get_max_tx_rate,
|
||||
.set_bits_per_cycle = rfbi_set_bits_per_cycle,
|
||||
.convert_timings = rfbi_convert_timings,
|
||||
.set_timings = rfbi_set_timings,
|
||||
.write_command = rfbi_write_command,
|
||||
.read_data = rfbi_read_data,
|
||||
.write_data = rfbi_write_data,
|
||||
.transfer_area = rfbi_transfer_area,
|
||||
.setup_tearsync = rfbi_setup_tearsync,
|
||||
.enable_tearsync = rfbi_enable_tearsync,
|
||||
|
||||
.max_transmit_size = (u32) ~0,
|
||||
};
|
||||
|
||||
Loading…
Reference in New Issue
Block a user