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drm/amd/pp: Clear smu response register before send smu message

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smu firmware do not update response register immediately under
some delay tasks, we may read out the original value.

so need to clear the register before send smu message.

Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Rex Zhu 2018-04-11 18:11:49 +08:00 committed by Alex Deucher
parent 5b79d0482f
commit 8db42a7013
2 changed files with 2 additions and 3 deletions
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4
drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c
View File

@ -208,9 +208,7 @@ static int ci_send_msg_to_smc(struct pp_hwmgr *hwmgr, uint16_t msg)
{
int ret;
if (!ci_is_smc_ram_running(hwmgr))
return -EINVAL;
cgs_write_register(hwmgr->device, mmSMC_RESP_0, 0);
cgs_write_register(hwmgr->device, mmSMC_MESSAGE_0, msg);
PHM_WAIT_FIELD_UNEQUAL(hwmgr, SMC_RESP_0, SMC_RESP, 0);

1
drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c
View File

@ -176,6 +176,7 @@ int smu7_send_msg_to_smc(struct pp_hwmgr *hwmgr, uint16_t msg)
else if (ret != 1)
pr_info("\n last message was failed ret is %d\n", ret);
cgs_write_register(hwmgr->device, mmSMC_RESP_0, 0);
cgs_write_register(hwmgr->device, mmSMC_MESSAGE_0, msg);
PHM_WAIT_FIELD_UNEQUAL(hwmgr, SMC_RESP_0, SMC_RESP, 0);