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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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ARM: clocksource: Add asm9260_timer driver
In some cases asm9260 looks similar to iMX2x. One of exceptions is timer controller. So this patch introduces new driver for this special case. Signed-off-by: Oleksij Rempel <linux@rempel-privat.de> Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
This commit is contained in:
Oleksij Rempel
Daniel Lezcano
parent
5833ac9865
commit
8d8bd7be8b
@ -229,4 +229,14 @@ config CLKSRC_MIPS_GIC
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depends on MIPS_GIC
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select CLKSRC_OF
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config ASM9260_TIMER
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bool "Alphascale ASM9260 timer driver"
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depends on GENERIC_CLOCKEVENTS
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select CLKSRC_MMIO
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select CLKSRC_OF
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default y if MACH_ASM9260
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help
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This enables build of a clocksource and clockevent driver for
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the 32-bit System Timer hardware available on a Alphascale ASM9260.
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endmenu
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@ -48,3 +48,4 @@ obj-$(CONFIG_ARCH_KEYSTONE) += timer-keystone.o
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obj-$(CONFIG_ARCH_INTEGRATOR_AP) += timer-integrator-ap.o
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obj-$(CONFIG_CLKSRC_VERSATILE) += versatile.o
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obj-$(CONFIG_CLKSRC_MIPS_GIC) += mips-gic-timer.o
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obj-$(CONFIG_ASM9260_TIMER) += asm9260_timer.o
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220
drivers/clocksource/asm9260_timer.c
Normal file
220
drivers/clocksource/asm9260_timer.c
Normal file
@ -0,0 +1,220 @@
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/*
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* Copyright (C) 2014 Oleksij Rempel <linux@rempel-privat.de>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/sched.h>
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#include <linux/clk.h>
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#include <linux/clocksource.h>
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#include <linux/clockchips.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/bitops.h>
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#define DRIVER_NAME "asm9260-timer"
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/*
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* this device provide 4 offsets for each register:
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* 0x0 - plain read write mode
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* 0x4 - set mode, OR logic.
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* 0x8 - clr mode, XOR logic.
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* 0xc - togle mode.
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*/
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#define SET_REG 4
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#define CLR_REG 8
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#define HW_IR 0x0000 /* RW. Interrupt */
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#define BM_IR_CR0 BIT(4)
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#define BM_IR_MR3 BIT(3)
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#define BM_IR_MR2 BIT(2)
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#define BM_IR_MR1 BIT(1)
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#define BM_IR_MR0 BIT(0)
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#define HW_TCR 0x0010 /* RW. Timer controller */
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/* BM_C*_RST
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* Timer Counter and the Prescale Counter are synchronously reset on the
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* next positive edge of PCLK. The counters remain reset until TCR[1] is
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* returned to zero. */
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#define BM_C3_RST BIT(7)
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#define BM_C2_RST BIT(6)
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#define BM_C1_RST BIT(5)
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#define BM_C0_RST BIT(4)
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/* BM_C*_EN
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* 1 - Timer Counter and Prescale Counter are enabled for counting
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* 0 - counters are disabled */
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#define BM_C3_EN BIT(3)
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#define BM_C2_EN BIT(2)
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#define BM_C1_EN BIT(1)
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#define BM_C0_EN BIT(0)
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#define HW_DIR 0x0020 /* RW. Direction? */
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/* 00 - count up
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* 01 - count down
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* 10 - ?? 2^n/2 */
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#define BM_DIR_COUNT_UP 0
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#define BM_DIR_COUNT_DOWN 1
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#define BM_DIR0_SHIFT 0
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#define BM_DIR1_SHIFT 4
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#define BM_DIR2_SHIFT 8
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#define BM_DIR3_SHIFT 12
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#define BM_DIR_DEFAULT (BM_DIR_COUNT_UP << BM_DIR0_SHIFT | \
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BM_DIR_COUNT_UP << BM_DIR1_SHIFT | \
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BM_DIR_COUNT_UP << BM_DIR2_SHIFT | \
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BM_DIR_COUNT_UP << BM_DIR3_SHIFT)
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#define HW_TC0 0x0030 /* RO. Timer counter 0 */
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/* HW_TC*. Timer counter owerflow (0xffff.ffff to 0x0000.0000) do not generate
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* interrupt. This registers can be used to detect overflow */
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#define HW_TC1 0x0040
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#define HW_TC2 0x0050
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#define HW_TC3 0x0060
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#define HW_PR 0x0070 /* RW. prescaler */
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#define BM_PR_DISABLE 0
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#define HW_PC 0x0080 /* RO. Prescaler counter */
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#define HW_MCR 0x0090 /* RW. Match control */
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/* enable interrupt on match */
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#define BM_MCR_INT_EN(n) (1 << (n * 3 + 0))
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/* enable TC reset on match */
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#define BM_MCR_RES_EN(n) (1 << (n * 3 + 1))
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/* enable stop TC on match */
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#define BM_MCR_STOP_EN(n) (1 << (n * 3 + 2))
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#define HW_MR0 0x00a0 /* RW. Match reg */
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#define HW_MR1 0x00b0
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#define HW_MR2 0x00C0
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#define HW_MR3 0x00D0
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#define HW_CTCR 0x0180 /* Counter control */
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#define BM_CTCR0_SHIFT 0
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#define BM_CTCR1_SHIFT 2
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#define BM_CTCR2_SHIFT 4
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#define BM_CTCR3_SHIFT 6
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#define BM_CTCR_TM 0 /* Timer mode. Every rising PCLK edge. */
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#define BM_CTCR_DEFAULT (BM_CTCR_TM << BM_CTCR0_SHIFT | \
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BM_CTCR_TM << BM_CTCR1_SHIFT | \
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BM_CTCR_TM << BM_CTCR2_SHIFT | \
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BM_CTCR_TM << BM_CTCR3_SHIFT)
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static struct asm9260_timer_priv {
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void __iomem *base;
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unsigned long ticks_per_jiffy;
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} priv;
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static int asm9260_timer_set_next_event(unsigned long delta,
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struct clock_event_device *evt)
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{
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/* configure match count for TC0 */
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writel_relaxed(delta, priv.base + HW_MR0);
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/* enable TC0 */
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writel_relaxed(BM_C0_EN, priv.base + HW_TCR + SET_REG);
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return 0;
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}
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static void asm9260_timer_set_mode(enum clock_event_mode mode,
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struct clock_event_device *evt)
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{
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/* stop timer0 */
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writel_relaxed(BM_C0_EN, priv.base + HW_TCR + CLR_REG);
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switch (mode) {
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case CLOCK_EVT_MODE_PERIODIC:
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/* disable reset and stop on match */
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writel_relaxed(BM_MCR_RES_EN(0) | BM_MCR_STOP_EN(0),
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priv.base + HW_MCR + CLR_REG);
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/* configure match count for TC0 */
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writel_relaxed(priv.ticks_per_jiffy, priv.base + HW_MR0);
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/* enable TC0 */
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writel_relaxed(BM_C0_EN, priv.base + HW_TCR + SET_REG);
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break;
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case CLOCK_EVT_MODE_ONESHOT:
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/* enable reset and stop on match */
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writel_relaxed(BM_MCR_RES_EN(0) | BM_MCR_STOP_EN(0),
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priv.base + HW_MCR + SET_REG);
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break;
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default:
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break;
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}
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}
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static struct clock_event_device event_dev = {
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.name = DRIVER_NAME,
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.rating = 200,
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.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
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.set_next_event = asm9260_timer_set_next_event,
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.set_mode = asm9260_timer_set_mode,
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};
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static irqreturn_t asm9260_timer_interrupt(int irq, void *dev_id)
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{
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struct clock_event_device *evt = dev_id;
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evt->event_handler(evt);
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writel_relaxed(BM_IR_MR0, priv.base + HW_IR);
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return IRQ_HANDLED;
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}
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/*
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* ---------------------------------------------------------------------------
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* Timer initialization
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* ---------------------------------------------------------------------------
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*/
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static void __init asm9260_timer_init(struct device_node *np)
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{
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int irq;
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struct clk *clk;
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int ret;
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unsigned long rate;
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priv.base = of_io_request_and_map(np, 0, np->name);
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if (!priv.base)
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panic("%s: unable to map resource", np->name);
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clk = of_clk_get(np, 0);
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ret = clk_prepare_enable(clk);
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if (ret)
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panic("Failed to enable clk!\n");
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irq = irq_of_parse_and_map(np, 0);
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ret = request_irq(irq, asm9260_timer_interrupt, IRQF_TIMER,
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DRIVER_NAME, &event_dev);
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if (ret)
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panic("Failed to setup irq!\n");
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/* set all timers for count-up */
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writel_relaxed(BM_DIR_DEFAULT, priv.base + HW_DIR);
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/* disable divider */
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writel_relaxed(BM_PR_DISABLE, priv.base + HW_PR);
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/* make sure all timers use every rising PCLK edge. */
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writel_relaxed(BM_CTCR_DEFAULT, priv.base + HW_CTCR);
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/* enable interrupt for TC0 and clean setting for all other lines */
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writel_relaxed(BM_MCR_INT_EN(0) , priv.base + HW_MCR);
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rate = clk_get_rate(clk);
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clocksource_mmio_init(priv.base + HW_TC1, DRIVER_NAME, rate,
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200, 32, clocksource_mmio_readl_up);
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/* Seems like we can't use counter without match register even if
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* actions for MR are disabled. So, set MR to max value. */
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writel_relaxed(0xffffffff, priv.base + HW_MR1);
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/* enable TC1 */
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writel_relaxed(BM_C1_EN, priv.base + HW_TCR + SET_REG);
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priv.ticks_per_jiffy = DIV_ROUND_CLOSEST(rate, HZ);
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event_dev.cpumask = cpumask_of(0);
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clockevents_config_and_register(&event_dev, rate, 0x2c00, 0xfffffffe);
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}
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CLOCKSOURCE_OF_DECLARE(asm9260_timer, "alphascale,asm9260-timer",
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asm9260_timer_init);
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