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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-11 17:56:49 +07:00
iwlwifi: move rx queue read pointer into rxq
This patch moves rx status/read registers into iwl_rx_queue structures. This solution is more memory hungry but is more structured and provides needed RX/TX separation Signed-off-by: Tomas Winkler <tomas.winkler@intel.com> Signed-off-by: Reinette Chatre <reinette.chatre@intel.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
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@ -927,33 +927,6 @@ struct iwl4965_schedq_bc_tbl {
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*/
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struct iwl4965_shared {
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struct iwl4965_schedq_bc_tbl queues_bc_tbls[IWL49_NUM_QUEUES];
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__le32 rb_closed;
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/* __le32 rb_closed_stts_rb_num:12; */
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#define IWL_rb_closed_stts_rb_num_POS 0
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#define IWL_rb_closed_stts_rb_num_LEN 12
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#define IWL_rb_closed_stts_rb_num_SYM rb_closed
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/* __le32 rsrv1:4; */
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/* __le32 rb_closed_stts_rx_frame_num:12; */
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#define IWL_rb_closed_stts_rx_frame_num_POS 16
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#define IWL_rb_closed_stts_rx_frame_num_LEN 12
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#define IWL_rb_closed_stts_rx_frame_num_SYM rb_closed
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/* __le32 rsrv2:4; */
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__le32 frm_finished;
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/* __le32 frame_finished_stts_rb_num:12; */
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#define IWL_frame_finished_stts_rb_num_POS 0
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#define IWL_frame_finished_stts_rb_num_LEN 12
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#define IWL_frame_finished_stts_rb_num_SYM frm_finished
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/* __le32 rsrv3:4; */
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/* __le32 frame_finished_stts_rx_frame_num:12; */
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#define IWL_frame_finished_stts_rx_frame_num_POS 16
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#define IWL_frame_finished_stts_rx_frame_num_LEN 12
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#define IWL_frame_finished_stts_rx_frame_num_SYM frm_finished
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/* __le32 rsrv4:4; */
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__le32 padding1; /* so that allocation will be aligned to 16B */
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__le32 padding2;
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} __attribute__ ((packed));
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#endif /* __iwl4965_4965_hw_h__ */
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@ -1631,12 +1631,6 @@ static int iwl4965_hw_channel_switch(struct iwl_priv *priv, u16 channel)
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}
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#endif
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static int iwl4965_shared_mem_rx_idx(struct iwl_priv *priv)
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{
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struct iwl4965_shared *s = priv->shared_virt;
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return le32_to_cpu(s->rb_closed) & 0xFFF;
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}
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static int iwl4965_alloc_shared_mem(struct iwl_priv *priv)
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{
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priv->shared_virt = pci_alloc_consistent(priv->pci_dev,
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@ -1647,8 +1641,6 @@ static int iwl4965_alloc_shared_mem(struct iwl_priv *priv)
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memset(priv->shared_virt, 0, sizeof(struct iwl4965_shared));
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priv->rb_closed_offset = offsetof(struct iwl4965_shared, rb_closed);
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return 0;
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}
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@ -2306,7 +2298,6 @@ static struct iwl_lib_ops iwl4965_lib = {
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.set_hw_params = iwl4965_hw_set_hw_params,
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.alloc_shared_mem = iwl4965_alloc_shared_mem,
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.free_shared_mem = iwl4965_free_shared_mem,
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.shared_mem_rx_idx = iwl4965_shared_mem_rx_idx,
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.txq_update_byte_cnt_tbl = iwl4965_txq_update_byte_cnt_tbl,
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.txq_set_sched = iwl4965_txq_set_sched,
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.txq_agg_enable = iwl4965_txq_agg_enable,
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@ -96,38 +96,9 @@ struct iwl5000_schedq_bc_tbl {
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/**
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* struct iwl5000_shared
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* @rb_closed
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* address is provided to FH_RSCSR_CHNL0_STTS_WPTR_REG
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*/
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struct iwl5000_shared {
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struct iwl5000_schedq_bc_tbl queues_bc_tbls[IWL50_NUM_QUEUES];
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__le32 rb_closed;
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/* __le32 rb_closed_stts_rb_num:12; */
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#define IWL_rb_closed_stts_rb_num_POS 0
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#define IWL_rb_closed_stts_rb_num_LEN 12
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#define IWL_rb_closed_stts_rb_num_SYM rb_closed
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/* __le32 rsrv1:4; */
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/* __le32 rb_closed_stts_rx_frame_num:12; */
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#define IWL_rb_closed_stts_rx_frame_num_POS 16
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#define IWL_rb_closed_stts_rx_frame_num_LEN 12
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#define IWL_rb_closed_stts_rx_frame_num_SYM rb_closed
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/* __le32 rsrv2:4; */
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__le32 frm_finished;
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/* __le32 frame_finished_stts_rb_num:12; */
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#define IWL_frame_finished_stts_rb_num_POS 0
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#define IWL_frame_finished_stts_rb_num_LEN 12
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#define IWL_frame_finished_stts_rb_num_SYM frm_finished
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/* __le32 rsrv3:4; */
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/* __le32 frame_finished_stts_rx_frame_num:12; */
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#define IWL_frame_finished_stts_rx_frame_num_POS 16
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#define IWL_frame_finished_stts_rx_frame_num_LEN 12
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#define IWL_frame_finished_stts_rx_frame_num_SYM frm_finished
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/* __le32 rsrv4:4; */
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__le32 padding1; /* so that allocation will be aligned to 16B */
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__le32 padding2;
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} __attribute__ ((packed));
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#endif /* __iwl_5000_hw_h__ */
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@ -863,8 +863,6 @@ static int iwl5000_alloc_shared_mem(struct iwl_priv *priv)
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memset(priv->shared_virt, 0, sizeof(struct iwl5000_shared));
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priv->rb_closed_offset = offsetof(struct iwl5000_shared, rb_closed);
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return 0;
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}
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@ -877,12 +875,6 @@ static void iwl5000_free_shared_mem(struct iwl_priv *priv)
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priv->shared_phys);
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}
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static int iwl5000_shared_mem_rx_idx(struct iwl_priv *priv)
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{
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struct iwl5000_shared *s = priv->shared_virt;
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return le32_to_cpu(s->rb_closed) & 0xFFF;
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}
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/**
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* iwl5000_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array
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*/
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@ -1460,7 +1452,6 @@ static struct iwl_lib_ops iwl5000_lib = {
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.set_hw_params = iwl5000_hw_set_hw_params,
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.alloc_shared_mem = iwl5000_alloc_shared_mem,
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.free_shared_mem = iwl5000_free_shared_mem,
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.shared_mem_rx_idx = iwl5000_shared_mem_rx_idx,
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.txq_update_byte_cnt_tbl = iwl5000_txq_update_byte_cnt_tbl,
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.txq_inval_byte_cnt_tbl = iwl5000_txq_inval_byte_cnt_tbl,
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.txq_set_sched = iwl5000_txq_set_sched,
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@ -1359,7 +1359,7 @@ void iwl_rx_handle(struct iwl_priv *priv)
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/* uCode's read index (stored in shared DRAM) indicates the last Rx
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* buffer that the driver may process (last buffer filled by ucode). */
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r = priv->cfg->ops->lib->shared_mem_rx_idx(priv);
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r = le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF;
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i = rxq->read;
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/* Rx interrupt, but nothing sent from uCode */
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@ -105,7 +105,6 @@ struct iwl_lib_ops {
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/* ucode shared memory */
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int (*alloc_shared_mem)(struct iwl_priv *priv);
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void (*free_shared_mem)(struct iwl_priv *priv);
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int (*shared_mem_rx_idx)(struct iwl_priv *priv);
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/* Handling TX */
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void (*txq_update_byte_cnt_tbl)(struct iwl_priv *priv,
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struct iwl_tx_queue *txq,
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@ -301,7 +301,6 @@ struct iwl_host_cmd {
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/**
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* struct iwl_rx_queue - Rx queue
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* @processed: Internal index to last handled Rx packet
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* @read: Shared index to newest available Rx buffer
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* @write: Shared index to oldest written Rx packet
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* @free_count: Number of pre-allocated buffers in rx_free
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@ -316,13 +315,14 @@ struct iwl_rx_queue {
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dma_addr_t dma_addr;
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struct iwl_rx_mem_buffer pool[RX_QUEUE_SIZE + RX_FREE_BUFFERS];
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struct iwl_rx_mem_buffer *queue[RX_QUEUE_SIZE];
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u32 processed;
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u32 read;
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u32 write;
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u32 free_count;
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struct list_head rx_free;
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struct list_head rx_used;
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int need_update;
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struct iwl_rb_status *rb_stts;
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dma_addr_t rb_stts_dma;
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spinlock_t lock;
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};
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@ -967,10 +967,9 @@ struct iwl_priv {
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struct ieee80211_vif *vif;
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struct iwl_hw_params hw_params;
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/* driver/uCode shared Tx Byte Counts and Rx status */
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/* driver/uCode shared Tx Byte Counts */
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void *shared_virt;
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int rb_closed_offset;
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/* Physical Pointer to Tx Byte Counts and Rx status */
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/* Physical Pointer to Tx Byte Counts */
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dma_addr_t shared_phys;
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/* Current association information needed to configure the
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@ -403,5 +403,21 @@
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#define TFD_QUEUE_SIZE_BC_DUP (64)
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#define TFD_QUEUE_BC_SIZE (TFD_QUEUE_SIZE_MAX + TFD_QUEUE_SIZE_BC_DUP)
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/**
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* struct iwl_rb_status - reseve buffer status
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* host memory mapped FH registers
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* @closed_rb_num [0:11] - Indicates the index of the RB which was closed
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* @closed_fr_num [0:11] - Indicates the index of the RX Frame which was closed
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* @finished_rb_num [0:11] - Indicates the index of the current RB
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* in which the last frame was written to
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* @finished_fr_num [0:11] - Indicates the index of the RX Frame
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* which was transfered
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*/
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struct iwl_rb_status {
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__le16 closed_rb_num;
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__le16 closed_fr_num;
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__le16 finished_rb_num;
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__le16 finished_fr_nam;
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} __attribute__ ((packed));
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#endif /* !__iwl_fh_h__ */
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@ -317,7 +317,10 @@ void iwl_rx_queue_free(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
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pci_free_consistent(priv->pci_dev, 4 * RX_QUEUE_SIZE, rxq->bd,
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rxq->dma_addr);
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pci_free_consistent(priv->pci_dev, sizeof(struct iwl_rb_status),
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rxq->rb_stts, rxq->rb_stts_dma);
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rxq->bd = NULL;
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rxq->rb_stts = NULL;
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}
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EXPORT_SYMBOL(iwl_rx_queue_free);
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@ -334,7 +337,12 @@ int iwl_rx_queue_alloc(struct iwl_priv *priv)
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/* Alloc the circular buffer of Read Buffer Descriptors (RBDs) */
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rxq->bd = pci_alloc_consistent(dev, 4 * RX_QUEUE_SIZE, &rxq->dma_addr);
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if (!rxq->bd)
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return -ENOMEM;
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goto err_bd;
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rxq->rb_stts = pci_alloc_consistent(dev, sizeof(struct iwl_rb_status),
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&rxq->rb_stts_dma);
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if (!rxq->rb_stts)
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goto err_rb;
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/* Fill the rx_used queue with _all_ of the Rx buffers */
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for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++)
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@ -346,6 +354,12 @@ int iwl_rx_queue_alloc(struct iwl_priv *priv)
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rxq->free_count = 0;
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rxq->need_update = 0;
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return 0;
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err_rb:
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pci_free_consistent(priv->pci_dev, 4 * RX_QUEUE_SIZE, rxq->bd,
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rxq->dma_addr);
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err_bd:
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return -ENOMEM;
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}
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EXPORT_SYMBOL(iwl_rx_queue_alloc);
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@ -412,7 +426,7 @@ int iwl_rx_init(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
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/* Tell device where in DRAM to update its Rx status */
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iwl_write_direct32(priv, FH_RSCSR_CHNL0_STTS_WPTR_REG,
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(priv->shared_phys + priv->rb_closed_offset) >> 4);
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rxq->rb_stts_dma >> 4);
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/* Enable Rx DMA
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* FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY is set because of HW bug in
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