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spi: lantiq: Move interrupt control register offesets to SoC specific data structure
Address of Interrupt control registers are different on new chipsets. So move them to SoC specific data structure. Signed-off-by: Dilip Kota <eswara.kota@linux.intel.com> Link: https://lore.kernel.org/r/f0f9723a30ea9c2ee48d2199f7512af9e15803b0.1594957019.git.eswara.kota@linux.intel.com Signed-off-by: Mark Brown <broonie@kernel.org>
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@ -49,8 +49,6 @@
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#define LTQ_SPI_RXCNT 0x84
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#define LTQ_SPI_DMACON 0xec
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#define LTQ_SPI_IRNEN 0xf4
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#define LTQ_SPI_IRNICR 0xf8
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#define LTQ_SPI_IRNCR 0xfc
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#define LTQ_SPI_CLC_SMC_S 16 /* Clock divider for sleep mode */
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#define LTQ_SPI_CLC_SMC_M (0xFF << LTQ_SPI_CLC_SMC_S)
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@ -158,8 +156,10 @@
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#define LTQ_SPI_IRNEN_ALL 0x1F
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struct lantiq_ssc_hwcfg {
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unsigned int irnen_r;
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unsigned int irnen_t;
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unsigned int irnen_r;
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unsigned int irnen_t;
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unsigned int irncr;
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unsigned int irnicr;
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};
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struct lantiq_ssc_spi {
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@ -792,13 +792,17 @@ static int lantiq_ssc_transfer_one(struct spi_master *master,
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}
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static const struct lantiq_ssc_hwcfg lantiq_ssc_xway = {
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.irnen_r = LTQ_SPI_IRNEN_R_XWAY,
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.irnen_t = LTQ_SPI_IRNEN_T_XWAY,
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.irnen_r = LTQ_SPI_IRNEN_R_XWAY,
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.irnen_t = LTQ_SPI_IRNEN_T_XWAY,
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.irnicr = 0xF8,
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.irncr = 0xFC,
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};
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static const struct lantiq_ssc_hwcfg lantiq_ssc_xrx = {
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.irnen_r = LTQ_SPI_IRNEN_R_XRX,
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.irnen_t = LTQ_SPI_IRNEN_T_XRX,
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.irnen_r = LTQ_SPI_IRNEN_R_XRX,
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.irnen_t = LTQ_SPI_IRNEN_T_XRX,
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.irnicr = 0xF8,
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.irncr = 0xFC,
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};
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static const struct of_device_id lantiq_ssc_match[] = {
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