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drm/amd/display: clean up DCHUBBUB register definition in hwseq
Cleanup to remove unused register definition from hw sequencer header file since implementation moved from hw sequencer to dchubub file. Signed-off-by: Eric Bernstein <eric.bernstein@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -141,25 +141,7 @@
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#define HWSEQ_DCN_REG_LIST()\
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SR(REFCLK_CNTL), \
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SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A),\
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SR(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A),\
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SR(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A),\
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SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B),\
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SR(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B),\
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SR(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B),\
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SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C),\
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SR(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C),\
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SR(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C),\
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SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D),\
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SR(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D),\
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SR(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D),\
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SR(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL),\
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SR(DCHUBBUB_ARB_DRAM_STATE_CNTL),\
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SR(DCHUBBUB_ARB_SAT_LEVEL),\
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SR(DCHUBBUB_ARB_DF_REQ_OUTSTAND),\
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SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \
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SR(DCHUBBUB_TEST_DEBUG_INDEX), \
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SR(DCHUBBUB_TEST_DEBUG_DATA), \
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SR(DIO_MEM_PWR_CTRL), \
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SR(DCCG_GATE_DISABLE_CNTL), \
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SR(DCCG_GATE_DISABLE_CNTL2), \
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@ -179,22 +161,10 @@
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MMHUB_SR(MC_VM_SYSTEM_APERTURE_LOW_ADDR),\
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MMHUB_SR(MC_VM_SYSTEM_APERTURE_HIGH_ADDR)
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#define HWSEQ_SR_WATERMARK_REG_LIST()\
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SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A),\
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SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A),\
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SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B),\
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SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B),\
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SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C),\
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SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C),\
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SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D),\
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SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D)
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#define HWSEQ_DCN1_REG_LIST()\
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HWSEQ_DCN_REG_LIST(), \
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HWSEQ_SR_WATERMARK_REG_LIST(), \
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HWSEQ_PIXEL_RATE_REG_LIST(OTG), \
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HWSEQ_PHYPLL_REG_LIST(OTG), \
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SR(DCHUBBUB_SDPIF_FB_TOP),\
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SR(DCHUBBUB_SDPIF_FB_BASE),\
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SR(DCHUBBUB_SDPIF_FB_OFFSET),\
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SR(DCHUBBUB_SDPIF_AGP_BASE),\
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@ -245,34 +215,8 @@ struct dce_hwseq_registers {
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uint32_t DCHUB_AGP_TOP;
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uint32_t REFCLK_CNTL;
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uint32_t DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A;
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uint32_t DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A;
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uint32_t DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A;
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uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A;
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uint32_t DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A;
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uint32_t DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B;
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uint32_t DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B;
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uint32_t DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B;
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uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B;
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uint32_t DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B;
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uint32_t DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C;
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uint32_t DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C;
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uint32_t DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C;
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uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C;
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uint32_t DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C;
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uint32_t DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D;
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uint32_t DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D;
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uint32_t DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D;
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uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D;
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uint32_t DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D;
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uint32_t DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL;
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uint32_t DCHUBBUB_ARB_SAT_LEVEL;
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uint32_t DCHUBBUB_ARB_DF_REQ_OUTSTAND;
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uint32_t DCHUBBUB_GLOBAL_TIMER_CNTL;
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uint32_t DCHUBBUB_ARB_DRAM_STATE_CNTL;
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uint32_t DCHUBBUB_TEST_DEBUG_INDEX;
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uint32_t DCHUBBUB_TEST_DEBUG_DATA;
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uint32_t DCHUBBUB_SDPIF_FB_TOP;
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uint32_t DCHUBBUB_SDPIF_FB_BASE;
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uint32_t DCHUBBUB_SDPIF_FB_OFFSET;
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uint32_t DCHUBBUB_SDPIF_AGP_BASE;
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@ -414,20 +358,11 @@ struct dce_hwseq_registers {
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HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, OTG0_),\
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HWS_SF1(OTG0_, PHYPLL_PIXEL_RATE_CNTL, PHYPLL_PIXEL_RATE_SOURCE, mask_sh), \
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HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, mask_sh), \
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HWS_SF(, DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL, DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST, mask_sh), \
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HWS_SF(, DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL, DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_DISABLE, mask_sh), \
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HWS_SF(, DCHUBBUB_ARB_DRAM_STATE_CNTL, DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_VALUE, mask_sh), \
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HWS_SF(, DCHUBBUB_ARB_DRAM_STATE_CNTL, DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE, mask_sh), \
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HWS_SF(, DCHUBBUB_ARB_DRAM_STATE_CNTL, DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_VALUE, mask_sh), \
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HWS_SF(, DCHUBBUB_ARB_DRAM_STATE_CNTL, DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_ENABLE, mask_sh), \
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HWS_SF(, DCHUBBUB_ARB_SAT_LEVEL, DCHUBBUB_ARB_SAT_LEVEL, mask_sh), \
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HWS_SF(, DCHUBBUB_ARB_DF_REQ_OUTSTAND, DCHUBBUB_ARB_MIN_REQ_OUTSTAND, mask_sh), \
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HWS_SF(, DCFCLK_CNTL, DCFCLK_GATE_DIS, mask_sh)
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#define HWSEQ_DCN1_MASK_SH_LIST(mask_sh)\
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HWSEQ_DCN_MASK_SH_LIST(mask_sh), \
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HWS_SF1(OTG0_, PHYPLL_PIXEL_RATE_CNTL, PIXEL_RATE_PLL_SOURCE, mask_sh), \
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HWS_SF(, DCHUBBUB_SDPIF_FB_TOP, SDPIF_FB_TOP, mask_sh), \
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HWS_SF(, DCHUBBUB_SDPIF_FB_BASE, SDPIF_FB_BASE, mask_sh), \
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HWS_SF(, DCHUBBUB_SDPIF_FB_OFFSET, SDPIF_FB_OFFSET, mask_sh), \
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HWS_SF(, DCHUBBUB_SDPIF_AGP_BASE, SDPIF_AGP_BASE, mask_sh), \
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@ -507,7 +442,6 @@ struct dce_hwseq_registers {
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type HUBP_VTG_SEL; \
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type HUBP_CLOCK_ENABLE; \
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type DPP_CLOCK_ENABLE; \
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type SDPIF_FB_TOP;\
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type SDPIF_FB_BASE;\
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type SDPIF_FB_OFFSET;\
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type SDPIF_AGP_BASE;\
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@ -520,14 +454,6 @@ struct dce_hwseq_registers {
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type AGP_BOT;\
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type AGP_TOP;\
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type DCHUBBUB_GLOBAL_TIMER_ENABLE; \
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type DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST;\
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type DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_DISABLE;\
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type DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_VALUE;\
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type DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE;\
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type DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_VALUE;\
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type DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_ENABLE;\
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type DCHUBBUB_ARB_SAT_LEVEL;\
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type DCHUBBUB_ARB_MIN_REQ_OUTSTAND;\
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type OPP_PIPE_CLOCK_EN;\
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type IP_REQUEST_EN; \
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type DOMAIN0_POWER_FORCEON; \
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