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arm64: Always enable spectre-v2 vulnerability detection
Ensure we are always able to detect whether or not the CPU is affected by Spectre-v2, so that we can later advertise this to userspace. Signed-off-by: Jeremy Linton <jeremy.linton@arm.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Tested-by: Stefan Wahren <stefan.wahren@i2se.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
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@ -109,7 +109,6 @@ cpu_enable_trap_ctr_access(const struct arm64_cpu_capabilities *__unused)
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atomic_t arm64_el2_vector_last_slot = ATOMIC_INIT(-1);
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#ifdef CONFIG_HARDEN_BRANCH_PREDICTOR
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#include <asm/mmu_context.h>
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#include <asm/cacheflush.h>
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@ -270,11 +269,11 @@ static int detect_harden_bp_fw(void)
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((midr & MIDR_CPU_MODEL_MASK) == MIDR_QCOM_FALKOR_V1))
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cb = qcom_link_stack_sanitization;
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install_bp_hardening_cb(cb, smccc_start, smccc_end);
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if (IS_ENABLED(CONFIG_HARDEN_BRANCH_PREDICTOR))
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install_bp_hardening_cb(cb, smccc_start, smccc_end);
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return 1;
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}
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#endif /* CONFIG_HARDEN_BRANCH_PREDICTOR */
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#ifdef CONFIG_ARM64_SSBD
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DEFINE_PER_CPU_READ_MOSTLY(u64, arm64_ssbd_callback_required);
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@ -513,7 +512,6 @@ cpu_enable_cache_maint_trap(const struct arm64_cpu_capabilities *__unused)
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.type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, \
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CAP_MIDR_RANGE_LIST(midr_list)
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#ifdef CONFIG_HARDEN_BRANCH_PREDICTOR
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/*
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* List of CPUs that do not need any Spectre-v2 mitigation at all.
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*/
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@ -545,6 +543,12 @@ check_branch_predictor(const struct arm64_cpu_capabilities *entry, int scope)
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if (!need_wa)
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return false;
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if (!IS_ENABLED(CONFIG_HARDEN_BRANCH_PREDICTOR)) {
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pr_warn_once("spectrev2 mitigation disabled by kernel configuration\n");
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__hardenbp_enab = false;
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return false;
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}
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/* forced off */
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if (__nospectre_v2) {
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pr_info_once("spectrev2 mitigation disabled by command line option\n");
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@ -556,7 +560,6 @@ check_branch_predictor(const struct arm64_cpu_capabilities *entry, int scope)
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return (need_wa > 0);
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}
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#endif
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#ifdef CONFIG_HARDEN_EL2_VECTORS
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@ -731,13 +734,11 @@ const struct arm64_cpu_capabilities arm64_errata[] = {
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ERRATA_MIDR_ALL_VERSIONS(MIDR_CORTEX_A73),
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},
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#endif
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#ifdef CONFIG_HARDEN_BRANCH_PREDICTOR
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{
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.capability = ARM64_HARDEN_BRANCH_PREDICTOR,
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.type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
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.matches = check_branch_predictor,
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},
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#endif
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#ifdef CONFIG_HARDEN_EL2_VECTORS
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{
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.desc = "EL2 vector hardening",
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