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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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ath10k: Add hw register/values for QCA99X0 chip
This is to prepare the driver for QCA99X0 chip support. This commit adds hw_params, hw register table and hw_values table for QCA99X0 chip. Please note this is only a partial patch adding support for QCA99X0, so the device id is not yet added to pci device table. Signed-off-by: Vasanthakumar Thiagarajan <vthiagar@qti.qualcomm.com> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
This commit is contained in:
Vasanthakumar Thiagarajan
Kalle Valo
parent
a521ee983d
commit
8bd4702103
@ -101,6 +101,20 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
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.board_ext_size = QCA6174_BOARD_EXT_DATA_SZ,
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},
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},
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{
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.id = QCA99X0_HW_2_0_DEV_VERSION,
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.name = "qca99x0 hw2.0",
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.patch_load_addr = QCA99X0_HW_2_0_PATCH_LOAD_ADDR,
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.uart_pin = 7,
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.fw = {
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.dir = QCA99X0_HW_2_0_FW_DIR,
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.fw = QCA99X0_HW_2_0_FW_FILE,
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.otp = QCA99X0_HW_2_0_OTP_FILE,
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.board = QCA99X0_HW_2_0_BOARD_DATA_FILE,
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.board_size = QCA99X0_BOARD_DATA_SZ,
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.board_ext_size = QCA99X0_BOARD_EXT_DATA_SZ,
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},
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},
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};
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static const char *const ath10k_core_fw_feature_str[] = {
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@ -1520,6 +1534,10 @@ struct ath10k *ath10k_core_create(size_t priv_size, struct device *dev,
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ar->regs = &qca6174_regs;
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ar->hw_values = &qca6174_values;
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break;
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case ATH10K_HW_QCA99X0:
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ar->regs = &qca99x0_regs;
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ar->hw_values = &qca99x0_values;
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break;
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default:
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ath10k_err(ar, "unsupported core hardware revision %d\n",
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hw_rev);
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@ -72,6 +72,43 @@ const struct ath10k_hw_regs qca6174_regs = {
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.pcie_intr_clr_address = 0x00000014,
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};
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const struct ath10k_hw_regs qca99x0_regs = {
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.rtc_state_cold_reset_mask = 0x00000400,
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.rtc_soc_base_address = 0x00080000,
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.rtc_wmac_base_address = 0x00000000,
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.soc_core_base_address = 0x00082000,
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.ce_wrapper_base_address = 0x0004d000,
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.ce0_base_address = 0x0004a000,
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.ce1_base_address = 0x0004a400,
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.ce2_base_address = 0x0004a800,
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.ce3_base_address = 0x0004ac00,
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.ce4_base_address = 0x0004b000,
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.ce5_base_address = 0x0004b400,
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.ce6_base_address = 0x0004b800,
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.ce7_base_address = 0x0004bc00,
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/* Note: qca99x0 supports upto 12 Copy Engines. Other than address of
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* CE0 and CE1 no other copy engine is directly referred in the code.
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* It is not really neccessary to assign address for newly supported
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* CEs in this address table.
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* Copy Engine Address
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* CE8 0x0004c000
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* CE9 0x0004c400
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* CE10 0x0004c800
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* CE11 0x0004cc00
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*/
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.soc_reset_control_si0_rst_mask = 0x00000001,
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.soc_reset_control_ce_rst_mask = 0x00000100,
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.soc_chip_id_address = 0x000000ec,
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.scratch_3_address = 0x00040050,
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.fw_indicator_address = 0x00040050,
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.pcie_local_base_address = 0x00000000,
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.ce_wrap_intr_sum_host_msi_lsb = 0x0000000c,
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.ce_wrap_intr_sum_host_msi_mask = 0x00fff000,
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.pcie_intr_fw_mask = 0x00100000,
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.pcie_intr_ce_mask_all = 0x000fff00,
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.pcie_intr_clr_address = 0x00000010,
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};
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const struct ath10k_hw_values qca988x_values = {
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.rtc_state_val_on = 3,
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.ce_count = 8,
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@ -86,6 +123,13 @@ const struct ath10k_hw_values qca6174_values = {
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.num_target_ce_config_wlan = 7,
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};
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const struct ath10k_hw_values qca99x0_values = {
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.rtc_state_val_on = 5,
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.ce_count = 12,
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.msi_assign_ce_max = 12,
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.num_target_ce_config_wlan = 10,
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};
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void ath10k_hw_fill_survey_time(struct ath10k *ar, struct survey_info *survey,
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u32 cc, u32 rcc, u32 cc_prev, u32 rcc_prev)
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{
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@ -72,6 +72,18 @@ enum qca6174_chip_id_rev {
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#define QCA6174_HW_3_0_BOARD_DATA_FILE "board.bin"
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#define QCA6174_HW_3_0_PATCH_LOAD_ADDR 0x1234
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/* QCA99X0 1.0 definitions (unsupported) */
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#define QCA99X0_HW_1_0_CHIP_ID_REV 0x0
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/* QCA99X0 2.0 definitions */
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#define QCA99X0_HW_2_0_DEV_VERSION 0x01000000
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#define QCA99X0_HW_2_0_CHIP_ID_REV 0x1
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#define QCA99X0_HW_2_0_FW_DIR ATH10K_FW_DIR "/QCA99X0/hw2.0"
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#define QCA99X0_HW_2_0_FW_FILE "firmware.bin"
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#define QCA99X0_HW_2_0_OTP_FILE "otp.bin"
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#define QCA99X0_HW_2_0_BOARD_DATA_FILE "board.bin"
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#define QCA99X0_HW_2_0_PATCH_LOAD_ADDR 0x1234
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#define ATH10K_FW_API2_FILE "firmware-2.bin"
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#define ATH10K_FW_API3_FILE "firmware-3.bin"
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@ -144,6 +156,7 @@ enum ath10k_fw_htt_op_version {
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enum ath10k_hw_rev {
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ATH10K_HW_QCA988X,
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ATH10K_HW_QCA6174,
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ATH10K_HW_QCA99X0,
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};
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struct ath10k_hw_regs {
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@ -175,6 +188,7 @@ struct ath10k_hw_regs {
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extern const struct ath10k_hw_regs qca988x_regs;
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extern const struct ath10k_hw_regs qca6174_regs;
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extern const struct ath10k_hw_regs qca99x0_regs;
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struct ath10k_hw_values {
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u32 rtc_state_val_on;
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@ -185,12 +199,14 @@ struct ath10k_hw_values {
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extern const struct ath10k_hw_values qca988x_values;
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extern const struct ath10k_hw_values qca6174_values;
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extern const struct ath10k_hw_values qca99x0_values;
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void ath10k_hw_fill_survey_time(struct ath10k *ar, struct survey_info *survey,
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u32 cc, u32 rcc, u32 cc_prev, u32 rcc_prev);
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#define QCA_REV_988X(ar) ((ar)->hw_rev == ATH10K_HW_QCA988X)
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#define QCA_REV_6174(ar) ((ar)->hw_rev == ATH10K_HW_QCA6174)
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#define QCA_REV_99X0(ar) ((ar)->hw_rev == ATH10K_HW_QCA99X0)
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/* Known pecularities:
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* - current FW doesn't support raw rx mode (last tested v599)
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@ -485,6 +501,8 @@ enum ath10k_hw_rate_cck {
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#define DRAM_BASE_ADDRESS 0x00400000
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#define PCIE_BAR_REG_ADDRESS 0x40030
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#define MISSING 0
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#define SYSTEM_SLEEP_OFFSET SOC_SYSTEM_SLEEP_OFFSET
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@ -59,6 +59,7 @@ MODULE_PARM_DESC(reset_mode, "0: auto, 1: warm only (default: 0)");
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#define QCA988X_2_0_DEVICE_ID (0x003c)
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#define QCA6174_2_1_DEVICE_ID (0x003e)
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#define QCA99X0_2_0_DEVICE_ID (0x0040)
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static const struct pci_device_id ath10k_pci_id_table[] = {
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{ PCI_VDEVICE(ATHEROS, QCA988X_2_0_DEVICE_ID) }, /* PCI-E QCA988X V2 */
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@ -1699,6 +1700,7 @@ static int ath10k_pci_get_num_banks(struct ath10k *ar)
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switch (ar_pci->pdev->device) {
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case QCA988X_2_0_DEVICE_ID:
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case QCA99X0_2_0_DEVICE_ID:
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return 1;
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case QCA6174_2_1_DEVICE_ID:
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switch (MS(ar->chip_id, SOC_CHIP_ID_REV)) {
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@ -2758,6 +2760,9 @@ static int ath10k_pci_probe(struct pci_dev *pdev,
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case QCA6174_2_1_DEVICE_ID:
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hw_rev = ATH10K_HW_QCA6174;
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break;
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case QCA99X0_2_0_DEVICE_ID:
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hw_rev = ATH10K_HW_QCA99X0;
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break;
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default:
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WARN_ON(1);
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return -ENOTSUPP;
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@ -450,4 +450,7 @@ Fw Mode/SubMode Mask
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#define QCA6174_BOARD_DATA_SZ 8192
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#define QCA6174_BOARD_EXT_DATA_SZ 0
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#define QCA99X0_BOARD_DATA_SZ 12288
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#define QCA99X0_BOARD_EXT_DATA_SZ 0
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#endif /* __TARGADDRS_H__ */
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