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drm/i915: Move vlv/chv display irq code to a more logical place
Reshuffle the code a bit to move the vlv/chv display irq functions away from the main irq hooks, next to the other sub (de,gt,etc.) hooks. v2: Rebased due to changes in vlv_display_irq_reset() Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Imre Deak <imre.deak@intel.com> (v1) Link: http://patchwork.freedesktop.org/patch/msgid/1460476604-2035-1-git-send-email-ville.syrjala@linux.intel.com
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@ -3285,23 +3285,6 @@ static void gen5_gt_irq_reset(struct drm_device *dev)
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GEN5_IRQ_RESET(GEN6_PM);
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GEN5_IRQ_RESET(GEN6_PM);
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}
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}
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/* drm_dma.h hooks
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*/
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static void ironlake_irq_reset(struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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I915_WRITE(HWSTAM, 0xffffffff);
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GEN5_IRQ_RESET(DE);
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if (IS_GEN7(dev))
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I915_WRITE(GEN7_ERR_INT, 0xffffffff);
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gen5_gt_irq_reset(dev);
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ibx_irq_reset(dev);
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}
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static void vlv_display_irq_reset(struct drm_i915_private *dev_priv)
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static void vlv_display_irq_reset(struct drm_i915_private *dev_priv)
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{
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{
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enum pipe pipe;
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enum pipe pipe;
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@ -3320,6 +3303,57 @@ static void vlv_display_irq_reset(struct drm_i915_private *dev_priv)
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dev_priv->irq_mask = ~0;
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dev_priv->irq_mask = ~0;
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}
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}
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static void vlv_display_irq_postinstall(struct drm_i915_private *dev_priv)
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{
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u32 pipestat_mask;
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u32 iir_mask;
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enum pipe pipe;
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pipestat_mask = PIPESTAT_INT_STATUS_MASK |
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PIPE_FIFO_UNDERRUN_STATUS;
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for_each_pipe(dev_priv, pipe)
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I915_WRITE(PIPESTAT(pipe), pipestat_mask);
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POSTING_READ(PIPESTAT(PIPE_A));
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pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV |
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PIPE_CRC_DONE_INTERRUPT_STATUS;
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i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
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for_each_pipe(dev_priv, pipe)
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i915_enable_pipestat(dev_priv, pipe, pipestat_mask);
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iir_mask = I915_DISPLAY_PORT_INTERRUPT |
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I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
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I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
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if (IS_CHERRYVIEW(dev_priv))
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iir_mask |= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
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dev_priv->irq_mask &= ~iir_mask;
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I915_WRITE(VLV_IIR, iir_mask);
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I915_WRITE(VLV_IIR, iir_mask);
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I915_WRITE(VLV_IER, ~dev_priv->irq_mask);
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I915_WRITE(VLV_IMR, dev_priv->irq_mask);
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POSTING_READ(VLV_IMR);
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}
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/* drm_dma.h hooks
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*/
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static void ironlake_irq_reset(struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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I915_WRITE(HWSTAM, 0xffffffff);
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GEN5_IRQ_RESET(DE);
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if (IS_GEN7(dev))
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I915_WRITE(GEN7_ERR_INT, 0xffffffff);
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gen5_gt_irq_reset(dev);
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ibx_irq_reset(dev);
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}
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static void valleyview_irq_preinstall(struct drm_device *dev)
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static void valleyview_irq_preinstall(struct drm_device *dev)
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{
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct drm_i915_private *dev_priv = dev->dev_private;
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@ -3656,40 +3690,6 @@ static int ironlake_irq_postinstall(struct drm_device *dev)
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return 0;
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return 0;
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}
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}
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static void vlv_display_irq_postinstall(struct drm_i915_private *dev_priv)
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{
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u32 pipestat_mask;
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u32 iir_mask;
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enum pipe pipe;
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pipestat_mask = PIPESTAT_INT_STATUS_MASK |
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PIPE_FIFO_UNDERRUN_STATUS;
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for_each_pipe(dev_priv, pipe)
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I915_WRITE(PIPESTAT(pipe), pipestat_mask);
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POSTING_READ(PIPESTAT(PIPE_A));
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pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV |
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PIPE_CRC_DONE_INTERRUPT_STATUS;
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i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
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for_each_pipe(dev_priv, pipe)
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i915_enable_pipestat(dev_priv, pipe, pipestat_mask);
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iir_mask = I915_DISPLAY_PORT_INTERRUPT |
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I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
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I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
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if (IS_CHERRYVIEW(dev_priv))
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iir_mask |= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
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dev_priv->irq_mask &= ~iir_mask;
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I915_WRITE(VLV_IIR, iir_mask);
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I915_WRITE(VLV_IIR, iir_mask);
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I915_WRITE(VLV_IER, ~dev_priv->irq_mask);
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I915_WRITE(VLV_IMR, dev_priv->irq_mask);
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POSTING_READ(VLV_IMR);
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}
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void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv)
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void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv)
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{
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{
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assert_spin_locked(&dev_priv->irq_lock);
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assert_spin_locked(&dev_priv->irq_lock);
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